[gem5-users] problem regarding using m5ops in Java code

2013-01-30 Thread Jiachen Xue
Hi, I tried to followed the link: http://www.m5sim.org/M5ops to insert M5ops into java code, but still having some issues with it. The followings are the steps I took: Step 1: To get "jni_gem5Op.h": javac jni/gem5op.java javah -jni jni.gem5Op Step 2: To get

Re: [gem5-users] how to run interconnect network in gems

2013-01-30 Thread Tushar Krishna
Hi Dehghani, I just pulled out the latest repo and ran the same simulation and it worked fine. The error itself is due to older python/c++ libraries. Note sure why it did not show up without garnet. Can you double check if all your libraries match the version numbers listed here: http://gem5.org/

[gem5-users] Problem with booting Android

2013-01-30 Thread Wahid
Hi, I am trying to boot up ARM based Ice Cream Sandwich kernel in Full System mode. command: gem5 # ./build/ARM/gem5.opt configs/example/fs.py --disk-image=/dist/m5/system/disks/ARMv7a-ICS-Android.SMP.nolock.img but after a while I get this warning at simulation prompt: ... warn: Tried to write

[gem5-users] Running multiple instances of gem5 on a cluster?

2013-01-30 Thread Gabriel Yessin
Should there be any problem with running a large number of instances of gem5 out of the same gem5/ folder (also using the same checkpoint, .img file, kernel, and etc) and just varying the CPU parameters (i.e. cache size(s), cpu freq, etc) and changing the output directories? >From my understanding

Re: [gem5-users] Understanding the dcache.overall_miss_rate in stat.txt

2013-01-30 Thread Fangfei Liu
Hi Ali, I want to confirm that when we report the miss rate for detailed mode (data cache), should we use dcache.overall_mshr_miss_rate or dcache.overall_miss_rate? How is the dcache.overall_mshr_miss_rate calculated? Is it # mshr misses/# overall accesses? If I understand correctly, using dcac

[gem5-users] Using standard switch to fastforward to a particular tick?

2013-01-30 Thread Gabriel Yessin
I'm sorry if this is a stupid question. It's my understanding that --frame-capture outputs to fb.tick#.bmp.gz, that checkpoints are in the form of cpt.tick# and that the standards switch option works by switching after instructions. How could I make it that makes my simulation switch after a gi

Re: [gem5-users] how to run interconnect network in gems

2013-01-30 Thread abbas
Dear Tushar, thanks for your reply I have the correct python and C++ libraries If the last parameter (--garnet...) is removed then this simulation will run. could you tell me how do i solve it? best regards, ___ gem5-users mailing list gem5-users@ge

Re: [gem5-users] Error when running bbench under arm_detailed

2013-01-30 Thread Si Chen
Hi Ali, Thank you so much for your reply. I will take a look at the new version first. Thanks, Si ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Understanding the dcache.overall_miss_rate in stat.txt

2013-01-30 Thread Fangfei Liu
我刚看到Ali回复了你，他还提到了应该看overall_mshr_miss_rate，你能不能问下这个是怎么计算的，是不是mshr miss占总的cache access数的比例。。。 From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Si Chen Sent: 2013年1月30日 10:36 To: gem5-users@gem5.org Subject: [gem5-users] Understanding the dcache.overall_miss_rate

Re: [gem5-users] Understanding the dcache.overall_miss_rate in stat.txt

2013-01-30 Thread Ali Saidi
Hi Si, I imagine you're sampling multiple times? THe cpu.data vs switch_cpu.data is because the transition between CPU models when you restored from a checkpoint. I imagine the second switch_cpus is a another sample. Note you probably want overall_mshr_miss_rate. Thanks, Ali On 30.01.201

[gem5-users] Multi level cache

2013-01-30 Thread SHARAN MORA (RIT Student)
I have forgot to reference big tsunami PAL code. I am able to run it now. I am trying to implement L3 cache using the same 2 level coherence protocol by adding L3 between L2 and mem using toL3bus. How should I implement connectAllPorts(). I have done it as if options.l3cache: system.cp

[gem5-users] Understanding the dcache.overall_miss_rate in stat.txt

2013-01-30 Thread Si Chen
Hi all, I am running bbench on arm detailed mode. But I have some trouble of understanding the stat results. I found that there are five different values in the stat for the dcache.overall_miss_rate. system.cpu.dcache.overall_miss_rate::switch_cpus.data 0.163675 # mis

Re: [gem5-users] About statistics

2013-01-30 Thread Rodrigo Reynolds Ramírez
Fernando thanks for your reply, but I have a question, I put a printf in the three functions that are used buy simple Memory: Tick SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt) Tick SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt) bool SimpleTimingPort::recvTimingReq(PacketPtr pkt)

Re: [gem5-users] About statistics

2013-01-30 Thread Fernando Endo
Hello, In my se.py file, if you don't set the --cpu-type option, the default is atomic cpu. So, no timing! Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2013/1/25 Rodrigo Reynolds Ramírez > I added the -s option to execution line, after includ

[gem5-users] Doubt about the checkpoint for disk image

2013-01-30 Thread huangyongbing
Hi all, I want to know that which information about disk image are recorded in the checkpoint files. If I create a checkpoint using image A and then add an application APP1 into image A, whether APP1 is available when I restore from the checkpoint. Thanks! Best regards