Re: [gem5-users] Average network latency in Ruby simple network

2012-08-31 Thread Jun Pang
Great! Thanks! Jun On Sat, Sep 1, 2012 at 1:27 AM, Tushar Krishna wrote: > Hi Jun, > You are right. It will work with hammer. The LD, IFETCH and ST will not > make any physical sense as they are generated randomly, but that should be > good to stress the protocol and your topology. > > - Tushar

Re: [gem5-users] Average network latency in Ruby simple network

2012-08-31 Thread Tushar Krishna
Hi Jun, You are right. It will work with hammer. The LD, IFETCH and ST will not make any physical sense as they are generated randomly, but that should be good to stress the protocol and your topology. - Tushar On Sep 1, 2012, at 1:25 AM, Jun Pang wrote: > Hi Tushar, > > Thanks for your reply

Re: [gem5-users] Average network latency in Ruby simple network

2012-08-31 Thread Jun Pang
Hi Tushar, Thanks for your reply. I feel like that the NetworkTest should also work with hammer protocol. As I understand it, the network_test.cc will generate three events for cache, which are LD, IFETCH and ST. Hammer also has those events, but hammer's directory will not drop those messages r

Re: [gem5-users] Average network latency in Ruby simple network

2012-08-31 Thread Tushar Krishna
Hi Jun, I am not very familiar with the stats generated from simple network. You'll have to dig into the code to see what those histograms mean. The network tester is supposed to be run with the NetworkTest coherence protocol, not MI_example, or MOESI_hammer. The network tester allows you to i

Re: [gem5-users] Question about running the Gem5

2012-08-31 Thread wael Amr
Hello There is no difference ,ALPHA is used to put in it all the configurations you need. You have to specify the full system in the ALPHA as shown "FULL_SYSTEM = 1" . You can check the per configuration section at http://www.m5sim.org/Build_System Wish this helps. Thanks Best Regards Wael AMR O

Re: [gem5-users] Checkpointing possible with Ruby, X86, TimingSimpleCPU and O3CPU?

2012-08-31 Thread Marco Elver
Hi Joel, Thank you for trying to fix this; if you say you have already fixed this issue partially, I'll wait for the final patches. -- Marco On 31/08/12 20:52, Joel Hestness wrote: > Hi Marco, > Thanks for sending this. Based on what I see here, I'm pretty > confident that one of my new patch

Re: [gem5-users] Checkpointing possible with Ruby, X86, TimingSimpleCPU and O3CPU?

2012-08-31 Thread Joel Hestness
Hi Marco, Thanks for sending this. Based on what I see here, I'm pretty confident that one of my new patches will fix this issue. Unfortunately, sending you that patch would only get you to the next bug that currently exists in Ruby's draining functionality. It appears as though these deeper

Re: [gem5-users] Checkpointing possible with Ruby, X86, TimingSimpleCPU and O3CPU?

2012-08-31 Thread Marco Elver
Hi Joel, I ran with 1 CPU and 16 CPUs and get essentially the same result. Attachments: - gdb-n1.log: Terminal output of gdb session for the 1 CPU case. - gdb-n16.log: Terminal output of gdb session for 16 CPU case. - gem5-n1.log.bz2: Gem5 output for 1 CPU case. - gem5-n16.log.bz2

Re: [gem5-users] cache_impl bug

2012-08-31 Thread Andreas Hansson
Hi Ali, I think this is related to a bug in the cache, and I am pretty sure this patch: http://reviews.gem5.org/r/1294/ will fix it. Could you give it a go? Andreas From: Ali chaker mailto:ali.chaker2...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Friday,

[gem5-users] cache_impl bug

2012-08-31 Thread Ali chaker
HI, I'm running bbench in gem5 with 2 cores and I've the following error: gem5.debug: build/ARM/mem/cache/cache_impl.hh:893: void Cache::handleResponse(Packet*) [with TagStore = LRU]: Assertion `pkt->req->masterId() < system->maxMasters()' failed. Program received signal SIGABRT, Aborted. 0x00