Re: [gem5-users] Problem with dma ports draining.

I've determined this is because drainEvent()->process() is being called when the port has properly drained. However, once it signals that it has drained, it gets another request. After this the l2 cpu-side port and and itb walker itself signal drained and drain() exits. Seems there is a race condit

Re: [gem5-users] Problem with dma ports draining.

I've added some more DPRINTF's to the dma port to track what is happening with the pendingCount: 5403270500: system.switch_cpus.itb.walker.dma: Starting DMA for addr: 0xfffa7c4 size: 4 sched: 0 pending count: 0 5403270500: system.switch_cpus.itb.walker.dma: incrementing pendingCount: 0->1 54032705

[gem5-users] How to get IPC in FS mode

Hi all, I have a question here, when I use SE mode to run SPEC 2006, the default stats will give results like "system.cpu.ipc". While I use FS mode to run some benchmarks like NetperfMaerts, it will only give "system.cpu.numCycles" and "system.cpu.committedInsts" but no "IPC" anymore. I ran FS mod

Re: [gem5-users] compile Linux kernel for X86 FS

Hi, But i made Cd for the linux-2.6.28.4 then i typed the command as shown : make -C /Mac/gem5/linux-2.6.28.4 O=/Mac/gem5/linux-2.6.28.4 CC=gcc-4.4 I got this error : make: *** /Mac/gem5/linux-2.6.28.4: No such file or directory. Stop. So is there anything missing ? Thanks Best Regards Wael AMR

Re: [gem5-users] problem with read/write SYSFLAG register when caches turned on

On 11.07.2012 03:35, Samuel Hitz wrote: > Hi there, > I have a problem reading/writing to the SYSFLAG register when caches are turned on. I wan to write the entry point for the new core in there, which works fine when caches are turned of. However when caches are turned on I get > > gem5.de

Re: [gem5-users] Problem with dma ports draining.

On 11.07.2012 17:15, Anthony Gutierrez wrote: > Hello, > I am having a problem when switching between two arm_detailed model CPUs. I am getting the following assertion failure: > > m5.opt: build/ARM/dev/dma_device.cc:90: virtual bool DmaPort::recvTimingResp(Packet*): Assertion `pendingCount

[gem5-users] Problem with dma ports draining.

Hello, I am having a problem when switching between two arm_detailed model CPUs. I am getting the following assertion failure: m5.opt: build/ARM/dev/dma_device.cc:90: virtual bool DmaPort::recvTimingResp(Packet*): Assertion `pendingCount >= 0' failed. Program aborted at cycle 5403285000 As can b

[gem5-users] ruby messages VS packets

Hi all, I want to implement a special interconnection network: a request from one node is always broadcast to all the other nodes with real destination ID/address set in the request. For all the other nodes, after they receive the broadcast request, they compare their own ID/address with the desti

Re: [gem5-users] Branch prediction issue in InOrder CPU

Hey Korey, I saw the thread from back than and changed the architecture according to it using also as reference the 9 stage pipeline_traits.cc. Yuval. -Original Message- From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Korey Sewell Sent: Monday, July 0

Re: [gem5-users] Transactional Memory Experiment Support on Gem5

No, gem5 as it stands does not support Transactional Memory. There are patches at www.eecs.umich.edu/~blakeg for making a very old version of gem5 (5+ year old version) support transactional memory. I'd recommend using it as a starting point for fitting in your own version of TM to the current gem

Re: [gem5-users] SimpleTimingCPU for ARM: Thumb instructions are request two times in the I-Cache.

On Wed, July 11, 2012 5:55 am, Nathanaël Prémillieu wrote: > Hi all, > > It seems that in the Timing CPU model, there are sometimes two requests > to the same address in a row. After some digging, it seems that it > happens because of thumb instructions. The first request is for the the > first t

[gem5-users] SimpleTimingCPU for ARM: Thumb instructions are request two times in the I-Cache.

Hi all, It seems that in the Timing CPU model, there are sometimes two requests to the same address in a row. After some digging, it seems that it happens because of thumb instructions. The first request is for the the first thumb instruction and the second request is for the second thumb ins

[gem5-users] Some problems in the Documents generated from doxygen

Hi everyone: I found some problems in the HTML Documents generated from doxygen. For example: Using the Browser (e.g. IE or Firefox) to see the HTML file "arch_2arm_2types_8hh.html". You will see the contents of "arch/arm/types.hh Files Reference". But there is no type at "ArmISA::cond" in the "Var

Re: [gem5-users] compile Linux kernel for X86 FS

wael Amr writes: > Hi, > what do you mean by "-C /path/to/src/linux O=/path/to/build/linux" ? 'make -C /foo' is similar to '(cd /foo ; make)'. See 'make -C /path/to/src/linux help' for a description of the 'O' variable. Lluis > As i typed the command " make CC=gcc-4.4",but i got this error m

[gem5-users] problem with read/write SYSFLAG register when caches turned on

Hi there, I have a problem reading/writing to the SYSFLAG register when caches are turned on. I wan to write the entry point for the new core in there, which works fine when caches are turned of. However when caches are turned on I get gem5.debug: build/ARM/dev/arm/rv_ctrl.cc:55: virtual Tick Re