Kai-Martin Knaak writes:
> Sorry, I should have checked. Their domain is genuinely German:
> http://basista.de
>^^
> BTW, the website just got a redesign. It looks much fancier than last
> week. Their pcb service is high quality,though. Last time I got shorted
> tr
Duncan Drennan writes:
> Double-clicking moves the cursor to the violation.
Yes, absolutely wonderful.
Except, ... it centers the cursor on violating entity, and does not show
the second entity that violates the clearance.
I've got 14 DRC violations left mostly on the power plane, that I can
Peter Clifton writes:
> On Fri, 2010-03-26 at 16:00 +0100, Stephan Boettcher wrote:
>> This is the board:
>>
>> http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
>>
>> Any idea if it is a good idea to just ignore these violations?
>
gene glick writes:
>> This is the board:
>>
>> http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
>>
>> Any idea if it is a good idea to just ignore these violations?
>>
>
> Blindly ignoring violations is probably not a good idea. Better to
> understand them first.
Well, I
Stephan Boettcher writes:
> Thank you very much for you review!
>
> I need to go now, when I am back later today I will tell you what the
> board is supposed to do.
I did not dare to ask for so detailed reviews of this board, I just
wanted to present a test case where DRC either r
Peter Clifton writes:
> On Sat, 2010-03-27 at 08:57 +0100, Stephan Boettcher wrote:
>> gene glick writes:
>>
>> >> This is the board:
>> >>
>> >> http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
>> >>
>
timecop writes:
>> Yep, look for example, at X2/C10 (at X=3426, Y=2381) it is so close to X2/R9
>> and X2/R5. How will you avoid solder bridges there? In fact, the solder
>
> well, that particular area doesnt matter since they're actually
> connected together anyway but yeah i agree placing pads
gene glick writes:
> Stephan Boettcher wrote:
>> Stephan Boettcher writes:
>
>> I did not dare to ask for so detailed reviews of this board,
>
> Hi Stephan,
>
> Sorry about that - it's a habit of mine.
Please keep that habit alive!
> Your system sound
timecop writes:
>> Yep, look for example, at X2/C10 (at X=3426, Y=2381) it is so close to X2/R9
>> and X2/R5. How will you avoid solder bridges there? In fact, the solder
>
> well, that particular area doesnt matter since they're actually
> connected together anyway but yeah i agree placing pad
Stephan Boettcher writes:
> Peter Clifton writes:
>
>> On Sat, 2010-03-27 at 08:57 +0100, Stephan Boettcher wrote:
>>> gene glick writes:
>>>
>>> >> This is the board:
>>> >>
>>> >> http://www.ieap.uni-kiel.de/et/peo
John Luciani writes:
> On Sat, Apr 10, 2010 at 6:58 PM, DJ Delorie wrote:
>>
>>> I can think of a few uses for your USB GPIO pod!-Patrick
>>
>> I use it mostly for testing out new components. I have added a
>> micro-sd module for it, and most recently it's wired up to a new
>> ethernet chip fro
Eric Brombaugh writes:
> On Apr 11, 2010, at 2:59 AM, Stephan Boettcher wrote:
>>
>> microSD are not required to support the SPI protocol. Do they usually
>> do? What brands?
>
> Interesting. I've tried a half-dozen different brands and haven't had
&g
timecop writes:
> just get used to typing
> gtk_ridiculously_long_function_names_with_lots_of_underscores() and
> wearing your keyboard out since not a single IDE under Lunix would
> have code complete or any other code editor improvements us Windows
> programmers have been taking for granted for
timecop writes:
> i'm pretty sure the guy is talking about a situation when
>
> 1) new user makes a board not knowing much about the tools involved
> 2) default via size is set smaller than default DRC check.
But isn't that perfect? When you start a new board it is mandatory to
first think abou
Mike Bushroe writes:
> John,
> Thanks for the clarification. I checked and I have created a unique
> 'name':'number' for each net attribute, and matched input to output names.
> If a net is formed for each unique name:number, and all inputs and outputs
> with that unique name are combined toget
DJ Delorie writes:
> It works, for mm, um, in, and mil suffixes on any number:
>
> {FLOATINGMM} { return parse_number(3937.0079); }
> {FLOATINGUM} { return parse_number(3.9370079); }
> {FLOATINGIN} { return parse_number(10.0); }
> {FLOATINGMIL}
Gabriel Paubert writes:
> Now the right solution to avoid having a proliferation
> of symnbols might be to have a way to specify attributes
> that map from pin name to pin numbers on every instance.
There _are_ attributes available that map from pinseq to pin number.
--
Stephan
___
writes:
> The minimum copper spacing is set to 10.0 mill and the distance between
> the two polygons is 15 mill.
I usually get a lot of DRC violations on planes with multiple polygons,
although the polygon spacing is comfortably more than the DRC clearance
setting. Moving the polygon edges fur
Tamas Szabo writes:
> I would create a schematic symbol for AT91SAM7 device: 64 pins, lots
> of them with multiplexed functions.
>
> 1. I can number pins round, 1 to 64 sequentially:
> + easily fit to the schematic, 4x16 pin
> + easy to create the symbol
> - no functional grouping
> - ha
John Doty writes:
> On Aug 8, 2010, at 3:47 PM, kai-martin knaak wrote:
>
>> John Doty wrote:
>>>
>>> Gnetlist is the *key* utility in the flow.
>>
>> It is just the glue between major components. No need to glorify this role.
>
> On the contrary, there is every need to glorify this role. An en
John Griessen writes:
> It's not pie in the sky. Some of these ideas to use sets and lists
> and groups are the easiest kind to implement... Zones in layout are
> an easy part of what it already does, when we have more layers for
> intermediate calculations. net attribs plus layout zones get u
Stefan Salewski writes:
> On Mon, 2010-08-16 at 10:09 +0200, Stephan Boettcher wrote:
>> John Griessen writes:
>>
>> If there is work put into partitioning a layout, can't we please have
>> hierarchical layout instead?
>>
> I have still problem
kai-martin knaak writes:
> Larry Doolittle wrote:
>
>>> All the cutting, sed-ing and pasting of the subcircuits to multiple
>>> instances, with replication of later changes on all copies is pretty
>>> unflexible.
>>
>> Agree 100%.
>
> +1
>
> Cloning, referencing, or whatever we may call it, woul
Stefan Salewski writes:
> On Sun, 2010-09-05 at 09:30 -0600, John Doty wrote:
>> All of this discussion of formats misses the shining example that's
>> already in gEDA: the schematic format.
>
> Yes. Recently I begun studying that format and started writing a parser
> in Ruby -- really easy.
>
>
John Doty writes:
> On Sep 5, 2010, at 10:43 AM, Stephan Boettcher wrote:
>
>> Yes, the gschem file format is much less accessible for
>> hand/awk/sed-editing than the pcb file format.
>
> Huh? gschem format is *trivial* to parse in awk. Use rules like:
>
> $1==
DJ Delorie writes:
> But I figure the top/inner/bottom "class" is what we need for
> importing footprints. They'd be layered by class, not number, so they
> can adapt to whatever number of layers the board has.
Rigid-Flex boards have pads on more than two layers. There are pads on
the rigid PC
DJ Delorie writes:
>> And I think the only way to do ... in a non-kludgy way
>
> Yet another example of you automatically putting down any idea that
> isn't yours. Please stop that. Please consider the possibility that
> someone might come up with a better (or even equally good) idea than
> you
Andrew Poelstra writes:
> On Sun, Sep 12, 2010 at 03:40:24PM -0400, DJ Delorie wrote:
>>
>> > > With flex cable, "top" and "bottom" aren't limited to one layer each.
>> >
>> > Aren't they?
>>
>> No. Different areas of the cable may have extra layers or pcbs
>> attached, changing the number of
DJ Delorie writes:
>> Now, the question becomes "which is more fundamental?". I think
>> it's geometry.
>
> A hole is the same geometry regardless of what level of the heirarchy
> it's placed at. So let me rephrase: Why have seven geometric holes,
> one for each layer, when we can have one geom
I prefer:
# -*- makefile -*-
CSA-L%.sch: CSA-1.sch Makefile
sed 's,^\(refdes\|netname\)=,&L$*_,' $< > $@
CSA-N%.sch: CSA-2.sch Makefile
sed 's,^\(refdes\|netname\)=,&N$*_,' $< > $@
FSH-S%.sch: FSH-1.sch Makefile
sed 's,^\(refdes\|netname\)=,&S$*_,' $< > $@
Steven Michalske writes:
> Now we may want to write a parser, and emitter, but that is a good
> amount of work, to serialize a data structure in the code that could
> be output be a data serializer that just works.
The emitter shall conserve order and formatting (probably not) or at
least be det
Phil Frost writes:
> I would point out a valid YAML representation of the above is also:
>
> {pin: {pinNumber: 2, pinName: rst, x1: 1234, y1: 4321, x2: 2345, y2: 4321,
> layer: component}}
> Neither sed nor awk can process XML or YAML the right way in all cases
> without reimplementing a libyam
k...@aspodata.se (Karl Hammar) writes:
> I would like the file format to be "programmable", at least at the
> footprint level.
We had that: M4 footprints. I never liked those, I could not figure out
how to use them. But if you drop the parameters, and make a
non-parameterized top-level file for
kai-martin knaak writes:
> John Doty wrote:
>> and thereby gaining unusual flexibility. Genius.
>
> ... µ and ?, let alone right to left scripting, or Chinese ...
> The flexibility you praise, is very narrowly defined.
Well, yes, that kind of flexibility you can get with all the other EDA
offe
DJ Delorie writes:
> PCB elements only have silk on the top layer, sorry.
But you could place the footprint on the bottom layer, if that helps.
--
Stephan
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/list
Rick Collins writes:
> To be perfectly correct, anyone who needs more than 84x84 inch boards
> will need to recompile PCB with 64-bit units. If it is me, I have no
> idea how to, so I can not. But I don't plan to. If I need boards
> larger than 84x84 inches, I will hire one of you to either la
Rick Collins writes:
> At 03:36 PM 10/9/2010, you wrote:
>>Rick Collins writes:
>>
>> > To be perfectly correct, anyone who needs more than 84x84 inch boards
>> > will need to recompile PCB with 64-bit units. If it is me, I have no
>> > idea how to, so I can not. But I don't plan to. If I nee
Andrew Poelstra writes:
> ... To the best of my knowledge, gcc uses a 32-bit long
> even on 64-bit systems, to maintain compatibility with old code.
> This was true last I checked, a year or two ago.
main(){printf("%lx\n",(long)(-1));}
yields
with
gcc (Debian 4.4.4-
Markus Hitter writes:
> Am 17.10.2010 um 17:16 schrieb Levente Kovacs:
>
>> I think that is why X11 has its coordinate system as is; and that is
>> why PCB developers went that way. But a CAD tool is not about CRT
>> display or image processing. I think we should change it; it looks
>> very awkwa
Stefan Salewski writes:
> What I wanted to say was: "Move to current Layer" makes not much sense
> for footprints, because we can have inner layers,
it does make sense, sometimes ...
> but we can not move footprints to that layers.
... pity
--
Stephan
_
Markus Hitter writes:
> - Get that thing packaged as soon as a new release is done. Only
> software developers install from source these days. As far as I can
> see, Debian and the just released Ubuntu 10.10 still distribute the
> Nov 2009 release.
I am using Debian unstable (sid). Even there I
John Griessen writes:
> Rearranging some sets of files' locations is faster by GUI than by
> commands, since whole swaths of files can be moved at once after a
> quick selection task done visually.
not, when I count the time for cleaning up after fat-fingering a mouse
button during the operation
Vanessa Ezekowitz writes:
> On Mon, 1 Nov 2010 13:46:51 -0700
> Steven Michalske wrote:
>
>> I code the latter way, writing a good low level API that has a simple
>> command line UI, then I add the GUI on top of it when it is warranted.
>
> Which is precisely what I was suggesting; since such to
Peter TB Brett writes:
> Obviously, since this is an unofficial branch, please don't submit
> patches or bugs to the official gEDA trackers. ;-)
What is the reason why this cannot be merged soon/immediately? From the
description is seems to be a clean addition, that should not interfere
signifi
John Griessen writes:
> copying scheme files
> cp: target `./gnetlist.scm' is not a directory
>
> Seems like a simple usage problem of the cp program... maybe it goes away
> the second time through?
This looks as if a variable that defines the target directory is
undefined or empty.
--
Steph
Markus Hitter writes:
> Exactly. A rectangle, or any number of lines drawing another
> area. Milled is always a rectangle, though.
Hmm, why? The outline layer is especially useful for boards that are
not rectangular shaped.
--
Stephan
___
geda-u
chrysn writes:
> hi geda-users,
>
> in the process of cnc-milling a pcb with a custom shape using pcb2gcode
> [1], i created a polygon on a separate layer. in the following
> processing steps, i need a gerber file that contains just that polygon
> (without holes for the pins, becaus they don't be
Kai-Martin Knaak writes:
> But if I try to access the produced pdf file with
> lp -d PDF -t "mosfet-node"; mv $HOME/PDF/mosfet-node.pdf .
> the second command seems to act on the state before the print command. If
> there was no PDF file before, I get:
> mv: cannot stat `/home/kmk/m
Kai-Martin Knaak writes:
> Hi.
> I just hit a legitimate use case for mirrored footprints:
> A layout sketch for dead-bug-prototyping. That is, glue the component
> with its back to the board and do the wires manually. However, there seems
> to be no way to mirror a footprint.
I guess it is sa
DJ Delorie writes:
> If you want to become a PCB committer, the process starts by writing
> good patches, reviewing other people's patches, and being involved in
> design discussions. When it gets to the point where the maintainers
> are just checking in whatever you ask, you're in :-)
Well, ob
DJ Delorie writes:
>> Layers in the footprint have to be mapped according to the principle
>> of least surprise.
>
> Last we talked of this, I mentioned symbolic layer tags vs physical
> layer tags. So footprints would have top/inner/bottom layers, boards
> would have 1(top)/2/3/4(bottom) layers
Kai-Martin Knaak writes:
> Pick one item a day and present it to the mailing list for comments?
Maybe not one item, but one set of related items a day? From your last
couple of lines, four of six items are about gschem text.
>
> ---<)kaimartin(>---
>
> PS: This is what the last couple of lin
Steven Michalske writes:
> See FAQ for pcb
This one? http://pcb.gpleda.org/faq.html
> On Dec 18, 2010, at 12:01 PM, jeffrey antony wrote:
>
>>Hello,
>>Is there a functionality in PCB to rotate a component in 45 degree
>>instead of 90 degree which is available at present?
>>Tha
kai-martin knaak writes:
> Stephan Boettcher wrote:
>
>>> See FAQ for pcb
>>
>> This one? http://pcb.gpleda.org/faq.html
>
> No, this one:
> http://geda.seul.org/wiki/geda:pcb_tips
> Although the page name says "pcb tips, it really conta
Peter TB Brett writes:
> On Wednesday 22 December 2010 19:17:14 Johnny Rosenberg wrote:
>
>> When I open a new page, a ”title block” is all I see, and there I can read
>> things like ”DRAWN BY”, ”TITLE”, ”REVISION” and so on. Am I supposed to
>> fill that in by using the Text tool ...?
>
> Yes!
"Johnny Rosenberg" writes:
> Den 2010-12-22 20:47:41 skrev DJ Delorie :
>
>>
>> The small circle is the snap-to-pin feature. You can disable it (I
>> leave it on) via Options->Toggle Magnetic Net
>>
>>
I disable the magnetic net most of the time. It does seldom what i want
it to do.
--
Steph
blueeag...@gmail.com writes:
> I really like the gSchema program and after getting used to it, I find it
> better than most I have tried. But the PCB program has a lot to be
> desired. I could probably do it if all I needed was through hole, but I
> need some custom parts. I could use KCAD I gu
kai-martin knaak writes:
> Armin Faltl wrote:
>
>> you suggest it's good for something - what for?
>
> Mechanics. These deviant holes may be used to solder the pcb
> to a brass rod.
>
> Anyway, I don't know what use some rocket scientist may find
> for overlapping holes. PCB can do it, some fabs
blueeag...@gmail.com writes:
> How do I replace a footprint? I realized that the footprint I had was not
> correct so I edited the *.fp file and changed it in the schematic using a
> different name, but the pcb program still has the old footprint even after I
> updated the layout.
Footprints in
kai-martin knaak writes:
> Stephan Boettcher wrote:
>
>> Rocket Scientist need to qualify everything that is even marginally
>> unusual, over full temperature range, and mechanical loads, in
>> vacuum. That will cost a thick branch of some big tree (10kg
>> paper
kai-martin knaak writes:
> From my notes:
>
> • pcb feature request: Please put all the gerbers in a dedicated subdir
> of the working directory by default. The name of the subdir should be
> configurable.
Any default will seldom be what I'd need, since either the directory
name or the filenam
DJ Delorie writes:
> "Bert Timmerman" writes:
>> I don't think it's a Good Thing (TM) that a User Manual is derived
>> from source code files, for this would require a person with gEDA-dev
>> priviliges to push changes into the git repository.
>
> I originally envisioned four manuals for PCB:
>
"Johnny Rosenberg" writes:
> Yet another newbie question then:
>
> I tried to enter a value of a resistor
> (/usr/share/gEDA/sym/analog/resistor-2.sym, my operating system is
> Ubuntu 10.10) but the position of the value needs to be adjusted a
> bit. How can I do that?
>
> It should look like t
"Johnny Rosenberg" writes:
> At http://www.geda.seul.org/wiki/geda:gsch2pcb_tutorial the following
> is written:
>
> ”When all the edits are done, it's very important when editing symbols
> to do a Edit→Symbol Translate to zero before saving. Do that and then
> save the symbol with File→Save Pag
Merry Christmas!
== PCB wishlist ==
The recent (and some not so recent) discussions made me think about how
development of PCB could proceed to solve some of the feature request,
in a future-proof way. This is what came up in my mind.
=== Make all layers explicit ===
Everything shall be layer
k...@aspodata.se (Karl Hammar) writes:
> Stephan:
>> Merry Christmas!
> Thanks, Merry Christmas to youself!
>
> ...
>> === Make elements small layouts ===
>>
>> An element shall be defined as a small layout, same syntax, same
>> semantics. ...
>
> That would be great.
>
>> === Introduce the conce
Peter Clifton writes:
> All ideas.. I'm not coding anything on this in the foreseeable future ;)
... but, somebody must code the graphics to support new features, e.g.,
dehilighting all objects that are not part of the currently edited
sublayout instances. :-)
--
Stephan
___
Levente Kovacs writes:
> On Sat, 25 Dec 2010 18:14:27 +0100
> Stephan Boettcher wrote:
>
>> 132 150 132 250
>
> I'd add a current netname to copper objects
>
> 132 150 132 250
>
> Or something like this.
This is fundamentally different from how PCB t
"Johnny Rosenberg" writes:
> Hm… I start to regret that I asked the question in the first place…
Please don't.
--
Stephan
___
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geda-user@moria.seul.org
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Levente Kovacs writes:
> The thing made post my previous message, is that it is very annoying when
> unconnected line stays on PCB, and there is no chance to connect anything to
> it. Even to the net it was formerly connected.
Well, that is a question of the HIDs, i.e., processes, in this case t
Stefan Salewski writes:
> I think one reason for start writing it was my desire to assign
> attributes/classes to subnets, to transfer this information to PCB to
> support manually- and auto-routing with already specified parameters for
> traces.
Why do you need a gschem replacement for that?
John Doty writes:
> One "crazy" configuration was to reduce the number of bits/photon to
> one, and thereby achieve two orders of magnitude better time
> resolution than most people thought necessary while staying within
> data transmission restrictions. I'm told that this has been the most
> com
Stefan Salewski writes:
> OK, shame on me for missing that option. But I do not think that this
> really proves that a gschem rewrite is obsolete.
I may believe that writing a second gschem editor is worse use of your
time than improving the existing one, but it is not up to me to judge
how you
Eduardo Costa writes:
> In my opinion, while the idea of the wikibook is fine, it's gonna need
> of constant surveillance which in turn, means a pain in the ass for
> whoever is at charge.
I think this is FUD
> Ideally, all the needed documentation should come together with the
> software, and
Vanessa Ezekowitz writes:
> On Sun, 26 Dec 2010 23:55:04 -0500
> al davis wrote:
>
>> On Saturday 25 December 2010, Vanessa Ezekowitz wrote:
>> > * If the part in question can usually be described by a
>> > single value, for the purposes of the signal flow in the
>> > schematic that is, then giv
John Doty writes:
> A better netlister for simulation is difficult as long as the gnetlist
> front end has hard-coded semantics, especially for hierarchy and
> slotting.
Last year (June 2009) LWN published a very nice series by Neil Brown
about successful design pattern in the Linux kernel. A
John Doty writes:
> On Dec 29, 2010, at 6:23 AM, Stephan Boettcher wrote:
>
>> I can imagine that it's not a lot, since this is really a classical
>> case for said design pattern.
>
> The real difficulty here is the complexity of the Guile<->C
> interface
Oliver King-Smith writes:
> Thank you for the info. Both the Ctrl-M idea from Levente and you suggestion
> for pin labels worked well for me.
A lot of features in PCB are not easily discoverable. Discoverability
is a major quality factor with UI software.
Info->Key Bindings
is a valuable
kai-martin knaak writes:
> Johnny Rosenberg wrote:
>
>> __
>> | |
>> | & |o–––
>> |__|
>>
>
> Ah, those box shaped symbols.
> Well, I don't like them. So none of them in my lib...
Those were invented by bureaucrats at a time when pen plotters had
difficulti
"Johnny Rosenberg" writes:
> Den 2010-12-31 02:58:36 skrev Stephan Boettcher
> :
>
>> kai-martin knaak writes:
>>
>>> Johnny Rosenberg wrote:
>>>
>>>> __
>>>> | |
>>>> | & |o–––
kai-martin knaak writes:
> Bob Paddock wrote:
>
>>> This is a DRC issue. The rules should allow any net to connect
>>> to no-net copper. No need to restructure the way pcb handles
>>> connectivity.
>>
>> If different nets connect to the same no-net copper there is a short
>> between nets.
>
> Of
"Johnny Rosenberg" writes:
> Well, I guess that I need to make my own symbols then,
Yes.
Will that be generic, light logic symbols, or 74xx series
symbols?
> and that it's no point sharing them since I am the only one who use
> them.
No. That's the wrong conclusion.
--
Stephan
_
"Johnny Rosenberg" writes:
>> No. That's the wrong conclusion.
>>
>
> Well, we'll see what will happen. I am still not 100% sure how to
> create symbols in the first place, so I guess things will move very
> slowly to begin with…
Maybe your time is better invested by using a small FPGA for wha
Philipp Klaus Krause writes:
> Am 31.12.2010 16:31, schrieb Stephan Boettcher:
>>
>> Maybe your time is better invested by using a small FPGA for whatever
>> you want to build, and learn Verilog to express the logic.
>>
>> Depends how much fun can have from
"Johnny Rosenberg" writes:
> Den 2010-12-31 16:31:42 skrev Stephan Boettcher
> :
>
>> "Johnny Rosenberg" writes:
>>
>>>> No. That's the wrong conclusion.
>>>>
>>>
>>> Well, we'll see what will happen.
John Griessen writes:
> I wish we were attaching netnames to pcb trace segments as we create
> them and using that to do auto enforce
Please don't!
> Guess I need to try out that Auto enforce DRC feature -- I've never
> purposely used it yet
Same here. If you do not use it, why do you care a
John Griessen writes:
> On 01/02/2011 04:14 PM, Stephan Boettcher wrote:
>> If you do not use it, why do you care about associating
>> netnames to traces?
>
> That's not about auto DRC enforce drawing, it's about searching
> for parts related to schemati
Dan White writes:
> gnetlist: Option "sort_port_value" sorts spice-IO devs by value=.
> SF: 3150019
> This allows using the refdes' to indicate pinlabel and then using
> value= to yield a meaningful ordering to a subckt's ports. My symbol
> generator script uses the refdes for pinlabel, order f
PCB 20100929 Debian Sid
When selecting elements (whatever) by left-draging a rectangle over the
canvas, pads on the deactivated far side are selected invisibly as well.
A subsequent ChangeClearSize(selectedpads,...) also changes the
invisibly selected pads on the backside.
My boardhouse told
"Johnny Rosenberg" writes:
> I created this symbol, it's the 74-series version of the 4066 (4
> bilateral switches), called 744066 (as in 74LV4066, for example):
>
>
>
>
> The documentation of the symbol can be found at
> http://focus.ti.com/lit/ds/symlink/sn74lv4066a.pdf
> I am not sure I go
DJ Delorie writes:
> Make the far side hidden before selecting.
That's the point, I did! The pads select anyway.
>
> Also, see MinMaskGap() to fix solder mask openings :-)
Well, I couldn't. I can only use actions that I know about. :-(
--
Stephan
Peter TB Brett writes:
>> The slot attribute does not get promoted. Why can't I promote an
>> attribute after placement from the (ee) Element attribute edit window?
>>
>
> I just tried this. I placed a symbol, hit , right-clicked on the
> inherited attribute that I wanted to promote, and sele
Stefan Salewski writes:
> On Tue, 2011-01-04 at 21:14 +0100, Johnny Rosenberg wrote:
>
>> comment=Use 74_pwr.sym for supply
>
> I wrote it some months ago...
>
> A single 74_pwr.sym can not work for 14 and 16 pin parts, so I really
> recommend to do not use a 74_pwr.sym at all, but one for 14, an
Matthew Wilkins writes:
>
> There _is_ a meaning to the order if a netlister expects only one
> attribute, but the symbol has several of the same name. In that case,
> the netlister could find either the first attribute of that name or
> the last, depending on how the netlister was written.
Th
John Doty writes:
> I'd prefer a spice-prototype attribute, which would allow us to avoid many of
> the difficulties without a confusing proliferation of attributes. For the
> symbol nmos-3.sym, a suitable prototype might be:
>
> M? #D #G #S #S $model-name L= W= AS= AD= PS= PD= M=
>
> We can ye
John Doty writes:
> On Jan 5, 2011, at 9:56 AM, Stephan Boettcher wrote:
>
>>
>> Is this too verbose?
>>
>> M? #{pinlabel=D} #{pinlabel=G} #{pinlabel=S} #{pinlabel=S} ${model-name}
>> L={length} W={width} AS= AD= PS= PD= M=
>
> Yes, I think it is.
DJ Delorie writes:
> DJ Delorie writes:
>> I had that problem with silk. I've not seen it for pads.
>
> Fixed in git head, not including any subtleties with elements with pads
> on both sides. I did the obvious thing for those, anyone who *has* one
> of those (edge connectors?) can complain if
DJ Delorie writes:
> Stephan Boettcher writes:
>> Whatever the obvious thing is, the only correct thing is that
>> invisible (deactivated) objects must not get selected.
>
> If an element is on the front side, but has pads on both sides, and the
> back side is hid
DJ Delorie writes:
> The "operation" is "select". PCB doens't know *why* you're selecting,
> it's just selecting everything in a region. If you select the *element*
> should it select the *whole* element, or just part of the element?
It is possible to make parts of an element invisible
(silk/p
Krzysztof Kościuszkiewicz writes:
> I would say the existing attribute/backend/semantics interaction
> matrix is complex enough
> to require full analysis of the implications of yet another attribute
> being added...
The matrix is so complex because it is not orthogonal. The solution is:
more a
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