Stephan Boettcher <[email protected]> writes: > Peter Clifton <[email protected]> writes: > >> On Sat, 2010-03-27 at 08:57 +0100, Stephan Boettcher wrote: >>> gene glick <[email protected]> writes: >>> >>> >> This is the board: >>> >> >>> >> http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb >>> >> >>> >> Any idea if it is a good idea to just ignore these violations? >>> >> >>> > >>> > Blindly ignoring violations is probably not a good idea. Better to >>> > understand them first. >>> >>> Well, I visually scanned the perimeter of the violating planes and did >>> not find any problems, OTOH, Peter did see them, he said, so I need to >>> look more carefully. >> >> I didn't verify whether they were in fact, too close, just that I could >> make the violations go away by adjusting their clearances. It could be >> that PCB is miss-calculating the gaps. > > Ok. I will do that then, since there is no reason why they need to be > so close (10 mils) in most cases, just to get my layout DRC clean before > I submit them (on Monday?).
Yupp, when I make all plane to plane clearances at least 15 mil instead of 10 mil, the DRC is happy. 10 mil between planes is not good enough with 8 mil design rules. There is actually a case left with 10 mil clearance where DRC does not complain. I tried to convert my layout into a minimal example. Open the layout, enlarge a poly on the power layer to reduce the clearance to 10 mil. I chose an edge where no vias nor lines are present. DRC marks both polys. Then I tryed to remove stuff from the board, but I got segfaults from DRC. When I remove all routing from the front layer, most vias and pads become violations because they are too close but not connected any more. DRC is not pretty. After I removed all parts and vias too, DRC segfaults. Actually, I could not reproduce the segfault, but I got: *** glibc detected *** pcb: corrupted double-linked list: 0x08dc1fb8 *** Then I gave up. My boards are now both DRC clean. On Monday we expect a delivery of parts, so I can do some fitchecks on a 1:1 printoutm and then I'll have them made. Thanks for all the code, especially the DRC checker. Thanks for the reviews. -- Stephan _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
