On Jun 2, 2011, at 4:26 AM, DJ Delorie wrote:
>
> Yup, I know about that, I was thinking of something that worked with
> the hidden nets we all complain about, automatically pulling in those
> from whatever symbols were on the page and exposing them.
In 1.7.0, the following back end *almost* wo
On Jun 2, 2011, at 4:54 AM, Colin D Bennett wrote:
> On Wed, 1 Jun 2011 11:41:13 +0900
> John Doty wrote:
>
>>
>> On Jun 1, 2011, at 1:30 AM, Colin D Bennett wrote:
>>
>>> Power and ground connections are a critical part of the circuit
>>> design but would not be visible when looking at the
On 06/01/2011 02:54 PM, Colin D Bennett wrote:
But how (and where) would such global rules be defined?
In the chip biz you write design rules that create connectivity based on
overlap,
or boolean intersection of areas being greater than a minimum number of units.
Those rules use features of
On Wed, 1 Jun 2011 11:41:13 +0900
John Doty wrote:
>
> On Jun 1, 2011, at 1:30 AM, Colin D Bennett wrote:
>
> > Power and ground connections are a critical part of the circuit
> > design but would not be visible when looking at the schematic!
>
> It depends on the job. If there are rigorou
Yup, I know about that, I was thinking of something that worked with
the hidden nets we all complain about, automatically pulling in those
from whatever symbols were on the page and exposing them.
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On Jun 2, 2011, at 1:03 AM, DJ Delorie wrote:
>
> At one point, I suggested a "table object" for schematics, that let
> you describe the mapping from hidden power pins to nets. So, for
> example, one row might be "U4,U5 / Vdd / +5v".
http://www.gedasymbols.org/user/john_doty/tools/pins2gsch.ht
At one point, I suggested a "table object" for schematics, that let
you describe the mapping from hidden power pins to nets. So, for
example, one row might be "U4,U5 / Vdd / +5v".
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On Wed, Jun 01, 2011 at 11:41:13AM +0900, John Doty wrote:
>
> On Jun 1, 2011, at 1:30 AM, Colin D Bennett wrote:
>
> > Power and ground connections are a critical part of the circuit
> > design but would not be visible when looking at the schematic!
>
> It depends on the job. If there are r
On Jun 1, 2011, at 1:30 AM, Colin D Bennett wrote:
> Power and ground connections are a critical part of the circuit
> design but would not be visible when looking at the schematic!
It depends on the job. If there are rigorous global rules governing these
connections, putting them explicitl
> To my knowledge this is not the case right now. Of course the pin numbers
> should not be shown on the schematics: they would use up too much schematics
> real estate and are not interesting anyway (even relatively simple and cheap
> FPGA devices like XC3S700A has 88 power pins in the 256 pins BG
On Mon, 2011-05-30 at 22:59 +0200, Richard Rasker wrote:
> Um, OK ... but somehow, my older xgsch2pcb (or perhaps just the older
> PCB build) doesn't recognize the layout file edited with the newer PCB
> version any more. As a result, I haven't succeeded in updating any
> changes in my schematic i
On Mon, 2011-05-30 at 23:34 +0200, Richard Rasker wrote:
> It compiled OK after installing a bunch of dependencies, but I can't
> recall at all whether dbus was enabled or not. By the looks of it, I
> didn't use git, so I guess dbus is switched off. Is there a way to check
> if it is enabled?
xgs
> Do I understand correctly that heavy symbols basically have certain nets
> with predefined names (e.g. VCC, GND) implicitly included, whereas light
> symbols offer the pins to connect those nets oneself?
The difference between light and heavy is specificity. A light
resistor, for example, is j
On Tue, 31 May 2011 05:09:25 +0200
Kai-Martin Knaak wrote:
> Richard Rasker wrote:
>
> > OK, I'll start by reading up on the light vs. heavy symbol
> > discussions. Do I understand correctly that heavy symbols basically
> > have certain nets with predefined names (e.g. VCC, GND) implicitly
> > i
On Tue, May 31, 2011 at 05:09:25AM +0200, Kai-Martin Knaak wrote:
> Richard Rasker wrote:
>
> > OK, I'll start by reading up on the light vs. heavy symbol discussions.
> > Do I understand correctly that heavy symbols basically have certain nets
> > with predefined names (e.g. VCC, GND) implicitly
Richard Rasker wrote:
> OK, I'll start by reading up on the light vs. heavy symbol discussions.
> Do I understand correctly that heavy symbols basically have certain nets
> with predefined names (e.g. VCC, GND) implicitly included, whereas light
> symbols offer the pins to connect those nets onese
>> The trace optimizer only touches autorouted tracks by default - if you
>> want it to work on manually routed traces you need to clear the
>> "Connects -> Optimize routed tracks -> [/] Only autorouted nets"
>> checkbox.
>
> Thanks for the suggestion, but it messed up the layout something
> wicke
Op vrijdag 27-05-2011 om 19:56 uur [tijdzone +0100], schreef Peter
Clifton:
> On Thu, 2011-05-26 at 10:03 +0200, Richard Rasker wrote:
>
> > - Work flow of newer gschem/PCB version: until recently, I worked with
> > an older PCB version (20080202), but I finally got round to compiling
> > and ins
On Tue, May 31, 2011 at 7:21 AM, Richard Rasker wrote:
> Op donderdag 26-05-2011 om 22:56 uur [tijdzone +1000], schreef Stephen
> Ecob:
>> > Then two more usage questions:
>> > - Zero length lines in PCB: I found that when drawing lines in PCB,
>> > sometimes dots (zero length lines) get created i
>> > - Zero length lines in PCB: I found that when drawing lines in PCB,
>>
>> I think you're tripping over the metric-rouding bug, where what you're
>> seeing is lines that are 0.01 mil long. We're working on that with
>> the metrification of PCB.
>
> Is there already some sort of script to elimi
Op donderdag 26-05-2011 om 22:56 uur [tijdzone +1000], schreef Stephen
Ecob:
> > Then two more usage questions:
> > - Zero length lines in PCB: I found that when drawing lines in PCB,
> > sometimes dots (zero length lines) get created inadvertently on corners
> > and bends. This isn't much of a pro
Op donderdag 26-05-2011 om 11:07 uur [tijdzone -0400], schreef DJ
Delorie:
> > I'd really like to contribute something back -- but as I'm not really a
> > proficient coder
>
> Contributions come in other forms, Certainly, library work and
> documentation are sorely in need of contributors and even
On Thu, 2011-05-26 at 10:03 +0200, Richard Rasker wrote:
> - Work flow of newer gschem/PCB version: until recently, I worked with
> an older PCB version (20080202), but I finally got round to compiling
> and installing the latest version -- and it's quite an improvement (no
> more disappearing cr
> I'd really like to contribute something back -- but as I'm not really a
> proficient coder
Contributions come in other forms, Certainly, library work and
documentation are sorely in need of contributors and even owners. If
you read the light/heavy thread, you'll see I just put out a call for
f
> Then two more usage questions:
> - Zero length lines in PCB: I found that when drawing lines in PCB,
> sometimes dots (zero length lines) get created inadvertently on corners
> and bends. This isn't much of a problem, until I start dragging lines
> and end points in rubber band mode: those dots t
Hello all,
First of all, I would like to express a huge "thank you" to all the
people who built and contributed to gEDA. I recently finished a largish
project with hundreds of devices and thousands of nets, and I got the
work done without a hitch. I find that gschem, PCB and other gEDA
building bl
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