Unfortunately, the highlighting just tells you WHICH nets are shorted,
not where they are shorted.
I tried deleting the objects in question which highlight orange. Now it
just highlights some more objects orange indicating 3.3V and ground are
shorted somewhere.
Is there any way to
I am getting these messages:
Warning! Net "3V3plus" is shorted to net "GND"
Warning! Net "GND" is shorted to net "3V3plus"
The 3.3V bus is used all over the board. How can I locate specifically
which part is shorted? It must be something I placed recently, but I do
not have an und
Bump. Not a major problem but would be nice to see fixed. Anyone know
what could cause this?
On 11 June 2011 22:49, Thomas Oldbury <[1]toldb...@gmail.com> wrote:
Segmentation fault occurred when I attempted to rotate an entire
board
(in the buffer)
This might explain my problem with PCB+GL maybe it's just a general
problem with PCB? I have noticed that PCB can eat up about 3 GB after a
few hours of routing.
On 3 June 2011 14:41, Kai-Martin Knaak <[1]kn...@iqo.uni-hannover.de>
wrote:
Andrew Poelstra wrote:
> Use gdb
Double sided boards are great, but not so great when the product is
supposed to cost only $3/each, after an MSP430, mains power supply,
heatsink, triac etc.
On 31 May 2011 22:09, Levente Kovacs <[1]leventel...@gmail.com> wrote:
On Tue, 31 May 2011 21:59:04 +0100
Thomas O
Oh. Thanks anyway. Any hack-ish way to add this in? (Because I'd like
each jumper to have a refdes and BOM entry if possible.)
On 31 May 2011 21:44, DJ Delorie <[1]d...@delorie.com> wrote:
> Does PCB have any support for adding jumper components, where the
> pins would essentially
Python!
On 31 May 2011 11:26, Jim Lynch <[1]j...@k4gvo.com> wrote:
On 05/27/2011 11:54 AM, DJ Delorie wrote:
This is more anecdotal than anything else...
I'm a Perl fan myself.
(shudder)
Javascript!
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Presently I use a second layer (such as a "jumper" layer) to draw on
jumpers for single layer FR4 PCBs, however this is cumbersome; and it
doesn't support zero ohm SMT resistors. Does PCB have any support for
adding jumper components, where the pins would essentially be shorted
(the
Another plus for Python. Such a nice language to code in IMHO.
On 26 May 2011 21:22, Geoff Swan <[1]shinobi.j...@gmail.com> wrote:
+1 python :)
On Fri, May 27, 2011 at 4:52 AM, Andrew Poelstra <[1][2]as...@sfu.ca>
wrote:
On Thu, May 26, 2011 at 10:56:40AM -0400, DJ De
I find it immensely useful, even on a 2-layer board, but when routing a
4-layer board it made it so much easier. I used to have to check all
the layers, even the ones with planes, to see if I had hit another
layer. Thanks Peter.
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Is there a Python api for gEDA?
Because that would be really nice...
On 18 May 2011 20:56, Stefan Salewski <[1]m...@ssalewski.de> wrote:
On Wed, 2011-05-18 at 19:26 +0200, Kai-Martin Knaak wrote:
> Russell Shaw wrote:
>
> > I think Scheme could be made much more attractive in
Can I enter my own project Super OSD?
[1]http://code.google.com/p/super-osd
On 18 May 2011 03:25, Kai-Martin Knaak <[2]k...@lilalaser.de> wrote:
Stefan Salewski wrote:
> While gEDA/PCB has some serious
> users and a large list of projects done with gEDA, KiCAD users seems
I didn't have it from the last git, but I haven't compiled the PCB+gl
branch without gl yet.
On 14 May 2011 15:43, Levente Kovacs <[1]leventel...@gmail.com> wrote:
On Sat, 14 May 2011 10:59:57 +0100
Thomas Oldbury <[2]toldb...@gmail.com> wrote:
> Af
I have not yet figured out what the "=" key does in PCB, but whenever
it gets pressed, the program freezes for a few minutes. Unfortunately,
on my laptop keyboard it is very close to the delete key, so this leads
to a lot of frustration. How do I turn it off?
_
After using PCB+gl for more than an hour or so on a basic 4-layer
board, it is using nearly 3.5 GB of memory, slowing the system to a
crawl and forcing it to page a lot of data. Is anyone else experiencing
this issue?
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On my ThinkPad X201, I am encountering a minor issue with PCB+GL... Not
a show stopper, but a bit annoying. I notice that when I move the
cursor, occasionally a random triangle extending from the middle of the
board to the outer edge will be highlighted. I'm using Ubuntu 10.10 and
th
It works. Thanks! :)
On 11 May 2011 21:51, Thomas Oldbury <[1]toldb...@gmail.com> wrote:
Ah, problem solved... needed to cd into the directory.
On 11 May 2011 21:31, Russell Dill <[2]russ.d...@asu.edu> wrote:
Did the clone succeed? Did you cd into the cloned r
Ah, problem solved... needed to cd into the directory.
On 11 May 2011 21:31, Russell Dill <[1]russ.d...@asu.edu> wrote:
Did the clone succeed? Did you cd into the cloned repo?
On Wed, May 11, 2011 at 12:53 PM, Thomas Oldbury
<[1][2]toldb...@gmail.com> wrote
lt;[1]pc...@cam.ac.uk> wrote:
On Wed, 2011-05-11 at 16:51 +0100, Thomas Oldbury wrote:
> I've heard a lot about this pcb+gl and I like it... and it turns out
I
>fetched my git a few days from the enabling of it, so I think I
missed
>the bus for it...
In
Sometimes, I want to add an inner polygon area to a plane in PCB. The
area might be a power supply which only has to cover a small area; e.g.
1.8V in a predominantly 3.3V area. However, if I just draw a polygon on
top of the plane, there is no cut-out formed and I get shorts. To do
w
Nope... rat lines are solid. I checked thisversion out around 2nd May.
On 11 May 2011 17:27, Kai-Martin Knaak <[1]kn...@iqo.uni-hannover.de>
wrote:
Thomas Oldbury wrote:
> I've heard a lot about this pcb+gl and I like it... and it turns out
I
> fetched
I've heard a lot about this pcb+gl and I like it... and it turns out I
fetched my git a few days from the enabling of it, so I think I missed
the bus for it...
So, how do I enable it for the latest git? Is there a compile-time
flag?
Thanks,
Tom
___
I start off with schematics. People underestimate the need for a clear
schematic. On the schematics, I tend to place components approximately
where they will appear on the PCB. This gives me an idea of how traces
are to be routed. I divide my schematics into virtual blocks - not
actu
Here is one way to break it that works 100% of the time:
1. Highlight only one layer and the top side components. The layer must
have a plane or large polygon area for the bug to be easily visible.
2. Move that layer and the components.
3. Hit Undo or "U", notice polygon has holes wh
Sometimes when moving polygons, PCB gets confused and leaves the holes
of old objects.
Is there a "refresh polygons" option, which would recalculate all the
polygons?
At present, I have to move every polygon in my design a tiny bit, then
move it back, to get it to recalculate them
I have a problem:
-- Uninstalling ubuntu pcb:
thomas@thinkpadone:~$ sudo apt-get remove pcb
[sudo] password for thomas:
Reading package lists... Done
Building dependency tree
Reading state information... Done
The following packages were automatically installed and are no lon
Any idea how to fix it?
I initially installed pcb from ubuntu repos. That was the 2007 edition
but it was too old for me. So I installed from git the latest unstable
1.99z. So that might be causing the issue - how do I fix it?
On 8 May 2011 13:12, DJ Delorie <[1]d...@delorie.com> wr
Here's what I get:
newlib: "%s"
../share/pcb/newlib
%s%s%s%spcblib-newlib
Top level directory for the newlib style library
/usr/share/pcb/newlib:/usr/share/pcb/pcblib-newlib
library-newlib
That makes me think it's in /usr/share/pcb, but it isn't.
Then I did this:
thoma
I have a little issue with pcb v1.99z, in that it has two libraries:
one that I see, and one that it uses. That is, I have added components,
and they do not show up. I delete footprints, and they do not go away.
One appears to reside in /usr/share/pcb and one in
/usr/local/share/pcb.
Thanks! I got it working.
On 2 May 2011 14:48, Peter Clifton <[1]pc...@cam.ac.uk> wrote:
On Mon, 2011-05-02 at 13:18 +0100, Thomas Oldbury wrote:
> I get this message trying to build pcb from git:
>configure: error: You have requested gcode, nelma, or png
Oh and I forgot to mention, I'm using Ubuntu 10.04.
On 2 May 2011 13:18, Thomas Oldbury <[1]toldb...@gmail.com> wrote:
I get this message trying to build pcb from git:
configure: error: You have requested gcode, nelma, or png HIDs
but
-lgd could n
I get this message trying to build pcb from git:
configure: error: You have requested gcode, nelma, or png HIDs but
-lgd could not be found
however, I have installed libgd2-noxpm. I have tried to install
libgd2-dev but there was no installation candidate.
Any help appreciated!
Last time I built PCB, I screwed up and made several footprint
directories and different tools seemed to use different ones.
Now I want to make certain that it will use the current directory I am
using: /usr/share/pcb, and not /usr/local/share/pcb. How can I make it
do this?
__
[sorry, pressed Send too soon]
SOx are the normal ones - 150 mil wide for most low pin count and 200
mil wide for others (>18 pins?)
SOxM is 200mil wide. It fits 8 pin 208mil DataFlash chips.
I've not used SOxW yet.
On 29 April 2011 20:08, Thomas Oldbury <[1]toldb..
SO8, SO16
On 29 April 2011 20:01, Rob Butts <[1]r.but...@gmail.com> wrote:
Can someone tell me what is the corresponding footprint when a
datasheet lists a footprint as SOIC-8, SOIC-14 and SOIC-16? In
PCB I
see SOxx with differing widths and SOJxx_xxx with a slew
Hmm... I used to get that error on Linux, but it never bothered me (I
used PCB fine.) Just leave the message log open in the background and
it won't bother you.
On 13 April 2011 13:19, Vaclav Peroutka <[1]vacla...@seznam.cz> wrote:
Hello all,
I don't want to disturb you too
I got mail too. I deleted it.
On 13 April 2011 12:51, rickman <[1]gnuarm.g...@arius.com> wrote:
I use a separate email address for this list and that address
received a spam email. It doesn't look like that email came through
this list, but rather the list was somehow harves
Out of curiosity, how do other PCB layout products (Altium, Orcad,
etc.) implement this? Follow by example?
On 7 April 2011 18:21, Stephan Boettcher
<[1]boettc...@physik.uni-kiel.de> wrote:
John Griessen <[2]j...@ecosensory.com> writes:
> On 04/07/2011 04:52 AM, Stephan Boettch
Normal paper is about 90 g/m^2 (or gsm.)
I'd take a guess that it's slightly more expensive, perhaps 130 g/m^2?
On 6 April 2011 22:49, yamazakir2 <[1]yamazak...@gmail.com> wrote:
I want to print up some owners manuals for some things I'm selling
but
I don't know what type
If you go into the attributes of a symbol, and tick "show inherited",
then you will see the nets the power/ground pins are associated to. You
can either change these pin assigns by adding new nets, or change your
net names. At least, that's how I've always done it.
On 2 April 2011 2
I found that ctrl-k worked, and "k" alone did not when all vias were
selected.
On 28 March 2011 23:46, DJ Delorie <[1]d...@delorie.com> wrote:
> Second question then - how do I tell how much clearance I have? The
> soldermask doesn't seem to show holes for vias.
Then you have
Second question then - how do I tell how much clearance I have? The
soldermask doesn't seem to show holes for vias.
On 28 March 2011 23:39, DJ Delorie <[1]d...@delorie.com> wrote:
Show the soldermask layer in pcb, then use the 'k' key to increase
the
soldermask clearance f
My board house seems to cover my vias with soldermask (tenting them),
which isn't what I want, because some are placed for testing purposes.
Is there any way to remove some soldermask around the via to reduce the
chance of tenting them? Thanks.
I'd suggest making it an opt-out for people like me who like it as it
is, but maybe I'll get used to it.
On 21 March 2011 22:56, Peter Clifton <[1]pc...@cam.ac.uk> wrote:
Could someone give this a test and come up with any counter-reasons
why
this attached patch is NOT a g
Ah, my error. It still didn't work (--prefix=/usr), but per Kai-Martin
Knaak's suggestion, I used /usr/local and put them there and they show
up, so I'm happy. :)
On 21 March 2011 22:26, DJ Delorie <[1]d...@delorie.com> wrote:
> My footprints still aren't showing up. :( I built it
I get this from strings /usr/bin/pcb | grep /pcb/
../share/pcb/newlib
/usr/share/pcb/newlib:/usr/share/pcb/pcblib-newlib
/usr/share/pcb/[1]gpcb-menu.re
My footprints still aren't showing up. :( I built it with
./configure.sh --prefix=/usr/share/pcb, then make, then sudo make
in
Probably my problem. Nope. Any idea where it is getting the footprints
from?
On 21 March 2011 17:28, DJ Delorie <[1]d...@delorie.com> wrote:
Did you build your 1.99z with --prefix=/usr ?
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I normally put all footprints under /usr/share/pcb/pcblib-newlib/tom,
this used to create an entry under pcblib-newlib called "tom". However,
as of 1.99z it seems to not be working. It looks like I'll have to
downgrade which is a shame because it fixed some bugs with the trace
length
I think we'd need to see the actual PCB to know if there's a short.
My suspicion would be that you have the fet the wrong way around or the
pads are not assigned correctly in the footprint or symbol.
On 20 March 2011 17:23, Rob Butts <[1]r.but...@gmail.com> wrote:
I am using an
OK, I used the git version, and the bug is fixed. Thanks. :)
On 15 March 2011 23:57, DJ Delorie <[1]d...@delorie.com> wrote:
> I'll try. Are there any bug fixes for that version relating to the
> net length calculator? Also, are the PCB files backwards
> compatible? I'm working w
I'll try. Are there any bug fixes for that version relating to the net
length calculator? Also, are the PCB files backwards compatible?I'm
working with several people who still use the 2009 versions.
On 15 March 2011 22:52, DJ Delorie <[1]d...@delorie.com> wrote:
> version 200911
Huh. Did not know that. Thanks. I'll have to check if my fab does
charge.
On 15 March 2011 22:51, DJ Delorie <[1]d...@delorie.com> wrote:
We already have a Hole type. Create a via, and use Ctrl-H to toggle
it into a hole.
Note that many fabs charge extra if you have unpla
About dialog shows this:
This is PCB, an interactive
printed circuit board editor
version 20091103
Compiled on Dec 18 2009 at 22:18:40
by harry eaton
On 15 March 2011 22:47, DJ Delorie <[1]d...@delorie.com> wrote:
What version of pcb are you using?
__
One thing I'd like to see is a drill hole, because at the moment I use
vias for those. It means I usually have to have a minimum plating, or
DRC will warn me, but drill holes rarely need plating.
On 15 March 2011 22:32, Martin Kupec <[1]martin.ku...@kupson.cz> wrote:
On Tue, Mar 15
Hmm it's not working...
I'm getting: Net length: 0.00 mils
Even when hovering over the trace. I think the problem is it is
including the pads and vias and getting confused, but I wouldn't know
enough about pcb to know for certain.
Can you see images over newsgroup? I've uploaded a
I'm trying to measure the length of some traces, so I can keep them the
same (for timing purposes.) I've heard of :report(netlength) but that
always gives me 0.00mm. What am I doing wrong, or is there something
else I should be doing?
___
ge
On 15 March 2011 14:39, Kai-Martin Knaak <[1]kn...@iqo.uni-hannover.de>
wrote:
My current project happens to be a use case for lines with paste:
I need to transport lots of current on limited space. And it needs
to be very resistant to vibration (this is supposed to survive a
Reading the section on blind and buried vias had me interested.
However, shouldn't vias be assigned layers (and not the other way
around?) It would probably make the code simpler - clicking on a via
would give immediate information about layers it belongs to, whereas
having vias assi
I've used a few.
On 14 March 2011 08:37, Balogh Richard, Ing. <[1]bal...@elf.stuba.sk>
wrote:
Me too. A lot of them.
Richard Balogh
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[3]http://www.seul.org/cgi-bin/mai
had a
large impact on performance in prior Email threads.
Steve
On Mar 12, 2011, at 4:07 PM, Thomas Oldbury <[2]toldb...@gmail.com>
wrote:
> I have recently got a new laptop, a Lenovo ThinkPad X201. However,
I'm
> having a rather annoying problem with
I have recently got a new laptop, a Lenovo ThinkPad X201. However, I'm
having a rather annoying problem with pcb. When trying to zoom in or
scroll, it is incredibly slow - taking a second or more to do any
action. I'm running pcb on another laptop and it doesn't have any
problems, it
I am using an outline layer in PCB. It complains of DRC violations when
the outline is too close to vias. Is it possible to get it to skip DRC
on these?
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In the BIOS, there is usually a "restore after power loss" option,
however if that doesn't work, I'd suggest a power on reset controller
connected to the power button. Here's one example, which is available
in TO92:
[1]http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en0201
I have two questions relating to solder paste. One is more general,
second one is about gEDA/PCB.
1.) Is it common practice to add paste on top of a copper layer to
carry more current or to remove heat from small power devices (surface
mount SOT26 buck regulator in my case)? If so,
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