The problem in the SOT23-5 may be the dash in the filename.
Try changing to a name like SOT23_5.
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Kester 2331-ZX
Aggressive flux so make sure you clean thoroughly.
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Not sure the pitch you require but I have a couple
of SON's at
http://www.luciani.org/geda/pcb/pcb-footprint-list.html
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On Wed, Feb 23, 2011 at 2:38 PM, yamazakir2 wrote:
> After you get done soldering and fluxing up your board to solder a lot
> of SMT components, what do you guys use to get it looking flux-free
> and clean again? I tried MG Chemical flux remove and while it does
> remove the flux, after washing it
On Sat, Feb 12, 2011 at 7:00 PM, John Griessen wrote:
>
> PS the Zierick IDC connectors are all copper, and reflowable, so they can
> do 150 deg C
> forever. Copper doesn't have any annealing properties that change any lower
> than
> 400 deg F I am sure. Tin is also good at 400 deg F. That's
On Sat, Feb 12, 2011 at 4:26 PM, Steven Michalske wrote:
> Or 1/4 inch quick disconnects.
> What about just soldering the wires?
This is for volume production of MCPCB. Connectors are preferred.
Are 1/4 inch quick disconnects the same as faston tabs?
The vertical tabs are too tall. Not sure abou
Thanks to everyone for the suggestions.
The Phoenix style are a bit too tall.
The Omnetics are too expensive but the Omnetics site did mention the materials
that the 125degC and 200degC rated were made of so I was able to find parts
at Tyco and Molex with the high temp materials.
I had originally
I am looking for a low profile wire to board connector - either two
contacts 5A per contact or four
contacts 2.5A per contact. I need a temperature rating of at least
110degC (preferable
>120degC). UL recognized is required.
Being able to remove the wires would be nice but is not a requirement. We
On Mon, Jan 31, 2011 at 1:29 AM, yamazakir2 wrote:
> http://products.cui.com/getPDF.aspx?fileID=4458
>
I use large round holes -- http://wiblocks.luciani.org/PICO/PICO1TR-index.html
IIRC the footprint is in the gEDA section at luciani.org
(* jcl *)
On Wed, Dec 22, 2010 at 2:55 PM, kai-martin knaak wrote:
> Johnny Rosenberg wrote:
>
>> things like ”DRAWN BY”, ”TITLE”, ”REVISION” and so on. Am I supposed
>> to fill that in by using the Text tool or is there a more proper way
>> to do it?
>
> Yes, this is the proper way with the default title
On Wed, Dec 15, 2010 at 10:42 PM, George M. Gallant, Jr.
wrote:
> I am looking for the footprint for a 2 x 4 2mm surface mount header.
I have some for one of the Molex series at
http://www.luciani.org/geda/pcb/pcb-footprint-list.html
(* jcl *)
___
g
Arcs aren't allowed in footprints. You can overlay rectangular pads
along an arc if you need to.
The footprint I use for fiducials is below. The request from the
assembly house was 1mm pad with 3mm clearance. The board that
assembled my last board did not mention any problems (and the
board worked
When I run the command
gsch2pcb --use-files --elements-dir /local/lan/pcb/packages --skip-m4
ELE2_r0.sch
I get the error message
At least gnetlist 20030901 is required for m4-xxx options.
I am on Ubuntu (Mavrick Merrkat) and used apt-get to install the tools.
Using the --verbose option produces
On Mon, Sep 6, 2010 at 10:09 PM, Eric Brombaugh wrote:
> Whenever I post pix from photo mode I always get questions about what tool I
> used to do them. Surprising that none of the big pro tools out there provide
> that. Who says OSS apps always follow the lead of the proprietary SW world?
I ha
On Sat, Jul 3, 2010 at 8:31 PM, Matthew Lai wrote:
> Hello,
>
> How do I add thermal pad (heatsink, NOT thermal relief pad!) in PCB?
> Rectangles/polygons don't clear solder mask.
Make a footprint with a large pad.
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On Thu, Jul 1, 2010 at 1:04 AM, DJ Delorie wrote:
> In October I'm going to be giving a presentation at a conference
What is the name of the conference?
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On Mon, May 24, 2010 at 3:57 PM, wrote:
> Hi all,
> i'm new in making pcb's and was wondering what footprint should i use
> for an sma connector?
> Thanks.
I have a couple at --
http://www.luciani.org/geda/pcb/footprints-gif/Connector-gif.html
(* jcl *)
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Closed Tools + Open Files !=
When this happens to me it is caused by not starting
on the end point. Sometimes, especially with 45 deg traces, the end point
can be a little tough to select. Also if you have changed to a
coarser grid it can be more difficult to hit the end point.
(* jcl *)
--
Closed Tools + Open Files != Open
On Fri, May 7, 2010 at 2:45 PM, Dave McGuire wrote:
> On May 7, 2010, at 12:49 PM, Windell H. Oskay wrote:
>>>
>> I wonder how third-part component search services (like findchips.com and
>> octopart) presently search the distributors. Does anyone know? There must
>> be some sort of API that th
On Tue, May 4, 2010 at 8:33 AM, George M. Gallant
wrote:
> I recently designed a small board that contained multiple instances
> of a devices that utilized copper on the bottom layer for heat
> dissipation (not ground). I ended up using closed loop trace around
> these large pads as a keep
On Mon, May 3, 2010 at 12:49 PM, Tamas Szabo wrote:
> John Luciani wrote:
>>
>> On Mon, May 3, 2010 at 12:12 PM, Tamas Szabo wrote:
>>>
>>> My best idea is, that I do it by pads which have a zero width and a
>>> specified clearance. Unfortuna
On Mon, May 3, 2010 at 12:12 PM, Tamas Szabo wrote:
>
> My best idea is, that I do it by pads which have a zero width and a
> specified clearance. Unfortunately, those will have a rounded corner, so
> rectangular corner seems impossible (I can reduce the radius, if I make it
> from more pieces, bu
My SQFP-50P-1480L1-1480L2-80N looks like it could work (see
http://www.luciani.org/geda/pcb/pcb-footprint-list.html).
Double-check the dimensions against your component and
process specs.
(* jcl *)
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Closed Tools + Open Files != Open Hardware
You can't create open hardware with closed EDA too
2010/4/13 SZABO Tamas :
> Hi,
>
> I would like to create a footprint where the pad is not in the center, and it
> is not symmetric for all sides.
>
> Is it possible somehow?
You can overlay multiple pads. Give each pad the same pin number.
(* jcl *)
On Sat, Apr 10, 2010 at 9:48 PM, DJ Delorie wrote:
>
> Yes, I got microsd working. Next time, though, I'm putting a P-MOSFET
> on the power line so I can software power cycle it.
> http://www.delorie.com/tmp/microsd.c
Excellent. Thanks!!! I will give this a try tomorrow.
I made the same omissio
On Sat, Apr 10, 2010 at 6:58 PM, DJ Delorie wrote:
>
>> I can think of a few uses for your USB GPIO pod!-Patrick
>
> I use it mostly for testing out new components. I have added a
> micro-sd module for it, and most recently it's wired up to a new
> ethernet chip from micrel.
Do you have uSD code
I used gEDA/PCB to do a remix of ladyada's drawdio remix. The zip
file contains the schematic (with embedded symbols) and the
PCB file. No gerbers but just do an export from the PCB
menu. The documentation file contains hard copies of the
schematic, board layout and bom. Each line item in the bom
i
I have 1000 or so footprints at
http://www.luciani.org/geda/pcb/pcb-footprint-list.html
The gEDA scripts and libraries that I use are also on the site.
Stefan's 15min-90min estimate for footprint creation seems about
right. With a script
you can generate families of footprints and amortize that ti
Popup ads and ads intermixed with gEDA content would
be distracting but I don't believe that is what is
being suggested.
A sidebar of text ads does not seem bad.
Occasionally useful and easy to ignore.
(* jcl *)
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You can't create open hardware with closed EDA tools.
twitter: http://twitter.c
I was thinking of a post-processing script.
For each footprint you would look up to see if there was a corresponding stencil
footprint (maybe a .sfp file). If there was that would be used. If not
then a rule would be applied to create the pattern. You could have
specific rules for groups of compon
I would also go with fast and quality for the reasons that Dave stated.
I would use PCB Express or Advanced Circuits. Highest quality
boards in 2-5 days (depending on service).
If you have more than one design panelize and
cut them yourself. If you have friends that want PCBs
group all your design
I have been using the Bausch & Lomb Magna Visor Magnifying Visor
81-42-00
It is $40 from Amazon and comes with three lenses. Works very well.
I keep one in the garage (woodshop) and one on my bench.
I also use the Luxo 17113 (magnifier + light).
(* jcl *)
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On Tue, Mar 2, 2010 at 1:25 AM, Donald Tillman <[1]...@till.com> wrote:
On Feb 27, 2010, at 3:57 PM, John Luciani wrote:
I use two different footprints. Both footprints have the pins
inline.
One footprint spaces the leads 1.39mm the other 2.60mm.
The 2.60mm
On Sat, Feb 27, 2010 at 6:27 PM, Donald Tillman <[1]...@till.com>
wrote:
Hey folks,
What's considered Best Practices for TO-92 packages?
I use two different footprints. Both footprints have the pins inline.
One footprint spaces the leads 1.39mm the other 2.60mm.
The 2.60m
equivalents. Obviously I can't just rip off XCircuit
symbols
with a converter, but I'll see if I can see about producing
similarly
styled graphics in gEDA using paths. (I might trace some bits).
It is about time we had some pretty symbols ;).
John Lucia
Without a Windows port you will have a beginners interface (and
documentation) but
no beginners ;) I have talked to a lot of people at the Arduino Users
Group and
at dorkbot and the majority are Windows, a fair number on MAC and a few
on Linux.
Eagle has done excellent marketin
Fiducials and Keepouts --
The last mfg I dealt with recommended that the fiducial be
a copper circle with a diameter between 0.5mm and 3.5mm and
that the solder mask diameter be three times larger than the
copper. I made a single 1mm pad footprint with
the 3mm clearance. IIRC the
Check the gerbers and drill files using gerbv.
I use a script that zips and renames all the files for the fab house.
I take the zip file that is created, unzip it and check those files
with gerbv.
For a system of boards that plug into each I might panelize them
so that they all al
On Wed, Feb 17, 2010 at 2:52 PM, Jason <[1]g...@lakedaemon.net> wrote:
Bob Paddock wrote:
Anyone know of a proto-house that will do 0.031" thick boards?
Advanced Circuits [2]http://www.4pcb.com will do them, you just have
to move away from the prototype stovepipe (no solderm
On Sun, Feb 14, 2010 at 3:23 PM, David Griffith
<[1]dgri...@cs.csubak.edu> wrote:
On Sun, 14 Feb 2010, John Luciani wrote:
Does anyone have a ready-made footprint for the Xicon 42IF series of
transformers?
That looks similar to the package for the Toko Inductors I u
That looks similar to the package for the Toko Inductors I used on a
Theremin.
Check the inductor section at
[1]http://www.luciani.org/geda/pcb/pcb-footprint-list.html
(* jcl *)
On Sun, Feb 14, 2010 at 1:43 PM, David Griffith
<[2]dgri...@cs.csubak.edu> wrote:
Does anyone
On Sat, Feb 6, 2010 at 2:10 PM, gene glick <[1]carzr...@optonline.net>
wrote:
Dave McGuire wrote:
First off, thanks for the input from all.
So you write in a text editor, add in your own codes?
I write a lot of macros. If you decide to use EMACS I would highly
recommend
On Sat, Feb 6, 2010 at 6:26 AM, gene glick <[1]carzr...@optonline.net>
wrote:
Do you all use Latex for editing docs, or maybe open office or
other? I'm getting fed up with the open office bugs and starting to
think that Latex is a better alternative. Busy compiling Lyx as we
On Sat, Jan 30, 2010 at 8:10 PM, Phil Frost <[1]ind...@bitglue.com>
wrote:
Is there some way to instruct PCB to put a copper pad for
through-hole
pins only on the bottom of the board? I'm etching two sided boards,
and
I don't solder to the top side since it makes rew
Why wouldn't you use the transistor or the FET? An MMBT3904 or an
N-channel
FET is more suitable for this application than a 1G125. I would go
with the MMBT3904
since you have a low voltage system. I used these to drive pager
motors in a haptic
compass.
I am not sure about
You will have to make rotated symbol. When you rotate a component that
has both
end points on grid at least one end point will be off grid unless the
rotation is by
an integer multiple of 90 degrees.
(* jcl *)
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twit
For 20 identical copies I would just do it manually. It
would be about five minutes of work. I place a 50mil space
between copies. This enables me to make
a single cut (between rows/cols) with a hacksaw blade.
I place copper at least 25mils from the edge (typically 50mils).
If I
2009/12/16 Goran Meki� <[1]m...@ns-linux.org>
� � Is there a way to recognize what footprint I need for an
element other
then printing them all and comparing it to real element? Let's say
it's 2200uF polar cap. I know it's RCY*, but how to figure out
what's
*? Th
On Tue, Nov 24, 2009 at 9:34 AM, Karl Hammar <[1]k...@aspodata.se>
wrote:
Can anyone recommend some good books on analog circuit design for
audio, precision/low noise op.amp., emc, active filters and similar
?
National Semiconductor use to publish the "Audio/Radio Handboo
On Tue, Nov 24, 2009 at 3:13 AM, Anthony Shanks
<[1]yamazak...@gmail.com> wrote:
Sorry but can you give me a direct link? I can't find it on the
site.
[2]http://www.luciani.org/geda/pcb/pcb-footprint-list.html
(* jcl *)
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I should have the 2.1mm jack and the SC70-5 at [1]luciani.org
(* jcl *)
--
You can't create open hardware with closed EDA tools.
twitter: [2]http://twitter.com/jluciani
blog:[3]http://www.luciani.org
References
1. http://luciani.org/
2. http://twitter.com/jluciani
You could also try some of the links at [1]http://www.schemers.org
(* jcl *)
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twitter: [2]http://twitter.com/jluciani
blog:[3]http://www.luciani.org
References
1. http://www.schemers.org/
2. http://twitter.com/jl
On Fri, Nov 20, 2009 at 6:46 AM, Dan McMahill <[1]...@mcmahill.net>
wrote:
Michael Sokolov wrote:
> Bill Gatliff <[2]b...@billgatliff.com> wrote:
>
>> Now I'm beginning to see the problems with slotting and symbols the
way
>> we're doing them now: they unnecessarily tie th
On Mon, Nov 16, 2009 at 5:16 PM, Ben Jackson <[1]...@ben.com> wrote:
On Mon, Nov 16, 2009 at 01:47:48PM -0800, Anthony Shanks wrote:
> I see, I actually like the black frame, I was just interested if any
> company sold them for cheaper. I'll just use the digikey part.
I'm sure t
I put all of the footprint files (or symlinks) that I use for
production boards in
a single directory. I also use descriptive footprint names. To find
a footprint I use dired mode in EMACS. Very easy to find to
footprints.
For semiconductors and some specialized components I add
On Sun, Oct 25, 2009 at 4:15 PM, Gene Heskett
<[1]gene.hesk...@verizon.net> wrote:
On Sunday 25 October 2009, John Luciani wrote:
>I am not sure if the Roland uses NGC or some other format.
>The commands looked a lot plotter control commands to
>me.
Me ei
There is a python script, from the MIT Media Lab, that converts
Gerber files into a format used by a Roland milling machine.
The python script is at
[1]http://web.media.mit.edu/~neilg/fab/dist/cam.py
I am not sure if the Roland uses NGC or some other format.
The commands looked a
On Thu, Oct 15, 2009 at 2:54 PM, Stephen Williams wrote:
>
> I was thinking about multi-part symbols, actually. It would be
> kool to draw a symbol for all the business pins and another symbol
> for the power pins. Then I could have a sheet just for power/gnd.
This is what I would do. I would als
Open up the symbols in a text editor and see if there are
net name attributes attached to the connector pins.
If there are then just remove them.
(* jcl *)
--
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twitter: http://twitter.com/jluciani
blog:http://www.luciani.org
__
Photos from the 2009 MIT Great Glass Pumpkin Patch are
[1]http://www.luciani.org.
Also a couple of photos from the MIT museum.
(* jcl *)
--
You can't create open hardware with closed EDA tools.
twitter: [2]http://twitter.com/jluciani
www: [3]http://www.luciani.org
Referenc
[1]http://blog.makezine.com/archive/2009/10/how_to_-_get_professionall
y_printed.html
[2]http://www.popsci.com/diy/article/2009-09/getting-your-circuit-boar
ds-professionally-printed
(* jcl *)
References
1.
http://blog.makezine.com/archive/2009/10/how_to_-_get_professionally_p
On Wed, Aug 26, 2009 at 8:23 PM, gene glick
<[1]carzr...@optonline.net> wrote:
how much does plating reduce the hole size? It just occurred to me
that
I have to allow for some reduction in finished hole size due to
the
plating and whatever other stuff goes on.
On Tue, Aug 18, 2009 at 6:39 PM, DJ Delorie <[1...@delorie.com> wrote:
as-shown uses the board's ShowSolderSide flag (the tab key changes
this) to decide which side to print. I don't know of a way to
force
that flag from the command line, but I suppose you could
perl-
I use the commands
pcb -x png --only-visible --ben-mode --dpi 600
pcb -x png --only-visible --ben-mode --ben-flip-x --dpi 600
to generate top and bottom pictures for PCB layouts. I would
like to get EPS files instead of PNGs. Are there EPS printing
options for this?
The co
2009/8/3 Goran Meki� <[1]m...@ns-linux.org>
� � Does anyone has B9A pin base (12AX7 tube, for example) for
pcb? I've
searched everything that came to my mind, but found nothing. How to
put tube on a PCB (software, not the real board), anyway? Thanx!
I wrote a script th
I do this all the time (even as we speak ;)
You need to find out how the manufacturer wants you to specify the
board perimeter. With PCB Express I place a one mil line on the top
layer.
(* jcl *)
--
You can't create open hardware with closed EDA tools.
[1]http://www.luciani
On Thu, Jul 30, 2009 at 6:35 AM, gene glick
<[1]carzr...@optonline.net> wrote:
John Luciani wrote:
>Since S6.S401 is repeated for all refdeses can you just put a box
>around the sub-circuit and label it S6.S401? You could then
replace the three
>
On Wed, Jul 29, 2009 at 10:21 PM, gene glick
<[1]carzr...@optonline.net> wrote:
Any comments on this sort of refdes position?
[2]http://geocities.com/motorcity/9424/geda/refdes_sample.png
I would find it difficult to use. Rather than reading a refdes you
have
to perform
There is a video of Stuart's gEDA presentation at
[1]http://tinyurl.com/bbt2rc
This was from Ignite Boston, Feb 2009.
(* jcl *)
--
You can't create open hardware with closed EDA tools.
[2]http://www.luciani.org
References
1. http://tinyurl.com/bbt2rc
2. http://www.luci
Are you sure that was a tornado?
Looking at those pictures it appears to be a message from aliens
addressed to William Hemmel ;)
(* jcl *)
--
You can't create open hardware with closed EDA tools.
[1]http://www.luciani.org
References
1. http://www.luciani.org/
__
On Tue, Jul 14, 2009 at 1:17 PM, Dan McMahill <[1]...@mcmahill.net>
wrote:
John Luciani wrote:
>On Tue, Jul 14, 2009 at 2:07 AM, Dan McMahill
<[1][2]...@mcmahill.net>
>wrote:
>
>Mark Rages wrote:
>> What is the lik
On Tue, Jul 14, 2009 at 11:10 AM, DJ Delorie <[1...@delorie.com>
wrote:
> Can PCB plot gerber files from the command line?
It can't read a gerber file and plot it, if that's what you mean.
It
always loads a .pcb and does whatever with it.
Sorry for the poor choice of
On Tue, Jul 14, 2009 at 2:07 AM, Dan McMahill <[1]...@mcmahill.net>
wrote:
Mark Rages wrote:
> What is the likelihood of moving --photo-mode from pcb to gerbv
where
> it belongs?
don't know about *moving* it. I'm certainly not opposed to
*adding* it
to gerbv tho
On Fri, Jul 10, 2009 at 9:19 PM, Michael B Allen <[1]iop...@gmail.com>
wrote:
Where can I find wire like that used for smallish ceramic disc
capacitors and other similar components?
I don't care if it's insulated but insulated wire is almost always
copper which is not as
On Wed, Jul 8, 2009 at 2:36 PM, John Doty <[1]...@noqsi.com> wrote:
On Jul 8, 2009, at 12:25 PM, John Luciani wrote:
>Putting vendor information into the schematic is not a good idea.
>
True, but...
Using your project symbols as capsules for that data i
On Wed, Jul 8, 2009 at 2:08 PM, Bill Gatliff <[1]b...@billgatliff.com>
wrote:
John Luciani wrote:
>aggregates the attributes manufacturer and
manufacturer_part_number,
>
Are those two attributes a common convention? I've been using
I would keep the footprint pin numbering consistent with the schematic
symbol
and datasheet pin numbering. If that means additional symbols and
footprints
then I would create them.
If there are differences between mfgs of the same part number then I
would attach a mfg suffix t
This sounds good to me.
If some of this code is used by the BOM utility then aggregating other
attributes by refdes could be useful. I have my own BOM script that
aggregates the attributes manufacturer and manufacturer_part_number,
in a hash, by refdes.
(* jcl *)
--
You can
I would use the square box with pins too.
(* jcl *)
--
You can't create open hardware with closed EDA tools.
[1]http://www.luciani.org
References
1. http://www.luciani.org/
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http://
On Thu, Jul 2, 2009 at 1:55 PM, Eric Brombaugh
<[1]ebrombau...@cox.net> wrote:
Anthony Blake wrote:
> By the way, the LCD project was very cool. Will the board be
available
> at some stage?
That's my intent. I've got it pretty much ready to go now, but
BatchPCB's DRC
On Sun, Jun 28, 2009 at 9:46 PM, Dan McMahill <[1]...@mcmahill.net>
wrote:
For transistors and IC's, I have no problems with the "enumerate
them
all" approach I've taken.
This is what I been doing too. All semiconductors are enumerated.
Since
all of the graphics are
On Sat, Jun 27, 2009 at 7:26 AM, S. Aguinaga <[1]sa...@yahoo.com>
wrote:
I need to create a footprint for a cylindrical SMT resistor. Do
you
fellows have some pointers for me to generate the semi-circular
cut
out?
You won't be able to get a circular cut-o
On Thu, Jun 25, 2009 at 8:24 PM, DJ Delorie <[1...@delorie.com> wrote:
Picoliters? All we need now is an inkjet printer that can print
solder paste instead of ink.
At Vicor we had a robot with a syringe that dispensed solder
paste dots.
(* jcl *)
--
You can't create
On Thu, Jun 25, 2009 at 12:24 PM, DJ Delorie wrote:
> Me, I have a perl script that post-processes that layer to adjust the
> sizes for the paste I want.
I was thinking of doing a Perl script that would substitute stencil
footprints (.sfp) if they were found. Otherwise a generic adjustment
would
The Fab Lab in Boston uses a Roland Modela MDX-20. There is
a python script that translates the gerber files that Eagle
creates into routing commands
(http://web.media.mit.edu/~neilg/fab/dist/cam.py).
I brought a couple of Gerber files (created with gEDA/PCB)
to try routing a board using the milli
Are routing traces with "new lines clears polygons" enabled?
My guess (without seeing the board) is that you have a trace
or piece of a trace underneath a pin or a pad. If there
is a polygon near it may produce a short.
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Did you change the slot attribute for each of the comparators?
(* jcl *)
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For hand soldering which footprint variation are people using?
My existing passive footprints are very generous in length making for
very easy assembly by hand. I would like to get some smaller footprints
that are not too difficult for hand assembly. The IPC M footprints
do not look too difficult.
I am wondering if the RESC1608L pad length is correct. The difference
between the RESC1608L and CAPC1608L is apx 30%. The difference between
RESC2012L and CAPC2012L is about 10%. I have not looked at heights or
calculated the values using the IPC-7351 equations. The RESC1608L
pads look very narrow
On Wed, Jun 10, 2009 at 11:24 AM, Frank Miles wrote:
> Since DJ mentioned impedance level concerns associated with different kinds
> of flux: please note that the flux pen shown in John Luciani's generally
> excellent recommendations leads to seriously low electrical conductivity.
> [At least for h
On Wed, Jun 10, 2009 at 9:19 AM, DJ Delorie wrote:
>
>> Well said. Tiny tips and tiny solder are the wrong approach.
>
> Of course, size is relative. 0.020" solder and 0.020" tip come in
> handy when soldering 0201 or 0402 parts, or trying to fix a single pin
> on 0.5mm pitch.
And when trying to
The supplies and tools I use for SMT assembly are
listed at http://tinyurl.com/5foeou
(* jcl *)
--
You can't create open hardware with closed EDA tools.
http://www.luciani.org
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geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org
hostview to view and print postscript files.
Also I have a postscript cartridge in my printer.
(* jcl *)
On Fri, Jun 5, 2009 at 4:33 PM, John Luciani
<[1][2]jluci...@gmail.com>
wrote:
On Fri, Jun 5, 2009 at 4:27 PM, Rob Butts
<[1][2][3]r.but...@gmai
On Fri, Jun 5, 2009 at 4:27 PM, Rob Butts <[1]r.but...@gmail.com>
wrote:
I'm exporting a postscript file and then converting that to a pdf
with
the ps2pdf command. I then come up in windows and print the file
to
my Samsung laser printer. I have to do this be
On Mon, Jun 1, 2009 at 8:35 AM, Tamas Szabo <[1]sza2k...@freemail.hu>
wrote:
Hi,
Can I make a pin without plating and put the footprint only to the
component side? If yes, how can I do it?
It sounds like you want a copper ring with an unplated hole. IIRC
pins create co
On Fri, May 29, 2009 at 10:35 AM, Stefan Salewski
<[1]m...@ssalewski.de> wrote:
On Fri, 2009-05-29 at 09:41 -0400, John Luciani wrote:
> It would be difficult to get that exact layout with real components
> but you should be able to get very close.
Yes. My shield
It would be difficult to get that exact layout with real components
but you should be able to get very close. I would be surprised
if you see a difference between connecting a pad with two or three
10mil traces and a solid plane. I would worry more about the
problems caused with han
On Mon, May 25, 2009 at 5:05 PM, Josef Wolf <[1...@raven.inka.de>
wrote:
On Mon, May 25, 2009 at 02:52:31PM -0400, John Luciani wrote:
> For the PCB layout I would make a breadboard footprint (along the
lines of
> the patterns of *[2]http://tinyurl.com/5bxzgh
For the PCB layout I would make a breadboard footprint (along the
lines of the
patterns of [1]http://tinyurl.com/5bxzgh ).
(* jcl *)
--
You can't create open hardware with closed EDA tools.
[2]http://www.luciani.org
References
1. http://tinyurl.com/5bxzgh
2. http://www
On Thu, May 21, 2009 at 7:10 PM, Kai-Martin Knaak
<[1]...@familieknaak.de> wrote:
On Thu, 21 May 2009 19:02:04 +, Michael Sokolov wrote:
> [2]http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/OSDCU-AA.bom
> [3]http://ifctfvax.Harhan.ORG/OpenSDSL/OSDCU/shortbom.txt
Thanks.
I'
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