On Tue, Sep 13, 2011 at 8:59 AM, Markus Hitter wrote:
>
> Am 12.09.2011 um 16:43 schrieb DJ Delorie:
>
>> 1. The easier it is to contribute, the more likely you are to be
>> vandalized. Wikipedia has seen plenty of this problem. You need
>> some method of authorizing trusted contributors and
On 11/09/2011 9:13 AM, "Markus Hitter" <[1]m...@jump-ing.de> wrote:
> But how close is gEDA here? To be honest, I think gEDA couldn't be
farther away. It can't even agree on an equivalent GUI design for both
major tools, gschem and pcb. Instead of doing something about that,
lots of
> So if I have an electromagnetic and I hold it next to the spinning
> metal disc as I increase the intensity of the magnetic field the metal
> disc should be harder to spin?
Yes.
> Define conductive? The eddy current breaks says non-ferromagnetic which
> means to me not having any magne
I've not looked into this in great detail myself, but I believe this
physics suggests this could be as simple as a spinning metal
(conductive) disk with a permanent magnet at an adjustable distance to
the spinning disk. It sounds like you understand how it works, but are
perhaps looking for the cat
On Fri, Sep 9, 2011 at 11:16 AM, Rob Butts wrote:
> I have asked this question on this forum before but I never got a
> definitive answer so forgive me for asking it again.
>
>
> Does anyone know the theory behind the design of an electromagnetic
> bicycle. I thought it was bringing in mag
+1 python :)
On Fri, May 27, 2011 at 4:52 AM, Andrew Poelstra <[1]as...@sfu.ca>
wrote:
On Thu, May 26, 2011 at 10:56:40AM -0400, DJ Delorie wrote:
>
> Opportunity to pick a more modern language, too. Something more
> os-agnostic, we've had issues with scheme on Windows befor
This post kind of blew out a bit - TLDR version - I have a database
idea that may be helpful in the pin swapping under discussion. The
database would provide a device representation that captures
*everything*. The database would help inform the pin swapping decision
process rather th
01005 (0402 metric) : 0.016" × 0.008" (0.4 mm × 0.2 mm)
0201 (0603 metric) : 0.024" × 0.012" (0.6 mm × 0.3 mm)
0402 (1005 metric) : 0.04" × 0.02" (1.0 mm × 0.5 mm)
0603 (1608 metric) : 0.063" × 0.031" (1.6 mm × 0.8 mm)
0805 (2013 metric) : 0.08" × 0.05" (2.0
I don't claim to have any great level of experience in writing APIs at
all - but I have already started some parts db stuff I would like to
continue - put me down against some parts db work.
cheers,
Geoff
On Wed, May 25, 2011 at 4:38 PM, DJ Delorie <[1]d...@delorie.com> wrote:
I really don't want any *major* changes to the core workflow and UI
TBH.
The changes that would make this a more complete tool (for me anyway)
are:
PCB:
- better control over polygons. Ie better awareness/ability to tie to
nets, built in crosshatching (intstead of solid), and a
I am sure there has been discussion around this in the past - but I am
keen to know if there is any chance of PCBs understanding of what a
footprint can contain being expanded in the near future?
Primarily just two things I would really like... text and polygons...
Is this somethin
We're going over old ground now...
[1]http://www.delorie.com/pcb/component-dbs.html
"First, in gschem/gattrib, the the GUI has a way of querying the
database for potential values of attributes - such as choosing
variants, picking parts from official part lists, sticking
cheers, I'll look more closely at me setup
On Thu, May 19, 2011 at 12:16 PM, DJ Delorie <[1]d...@delorie.com> wrote:
> I have been attempting to build polystitch.c against
pcb+gl_experimental
> without much luck. Also had some issue against pcb git head... Has
anyone
> el
I have been attempting to build polystitch.c against
pcb+gl_experimental without much luck. Also had some issue against pcb
git head... Has anyone else had any luck with polystitch.c building
against recent versions?
cheers,
Geoff
> > Examples
> > are the next to unusable default library of geda
>
> As has been discussed many times, this cannot be fixed, since there
is no
> narrow, common use case for gEDA. Even the big $$ tools can't get
this
> right, so how can we? A narrowly targeted, inflexible to
am.ac.uk>
wrote:
On Wed, 2011-05-11 at 07:16 -0700, Colin D Bennett wrote:
> On Wed, 11 May 2011 13:12:55 +0100
> Peter Clifton <[2]pc...@cam.ac.uk> wrote:
>
> > On Wed, 2011-05-11 at 21:41 +1000, Geoff Swan wrote:
> > > Hi folks, I'v
Hi folks, I've just started using separate layers so for my polygons so
that I can hide them when necessary. This works fine until I group them
with the appropriate layer. Ie - top and ground in a layer grouping -
with ground being the layer I am putting polygons on. When I go to hide
pcjc2/pcb+gl_experimental confirmed
(ubuntu 10.04 AMD64)
On Sat, Apr 23, 2011 at 6:05 PM, Link <[1]l...@penguindevelopment.org>
wrote:
On 23/04/11 05:42, Andrew Poelstra wrote:
> With the current git HEAD, pcb segfaults as soon as
> you click 'png' in the export list. Can any
> I would advise a note of caution.
What some people do not like is the visible :1 in schematics -- can
we
simple suppress that output for symbols with only one pin and digit
1
after the :
That would be a not too dangerous patch, because it concerns only
graph
(having not seen this post) I created something similar yesterday in
python.
It only does SMD dual column footprints with an outline - and at the
moment
only takes mm.
I'll push it to github or something like that if folks are interested.
I assumed at
the time that thi
I had a couple of issues with the patch process - I didn't bother
checking which version I should have had (i'm using 1.7.0 20110116) but
went and manually patched it myself.
BTW - the first hunk worked fine - it was only the second one that
failed.
Otherwise it seems great, c
I very much like the idea of this patch :)
I'll have a go at testing it.
On Tue, Mar 22, 2011 at 10:29 AM, Thomas Oldbury
<[1]toldb...@gmail.com> wrote:
I'd suggest making it an opt-out for people like me who like it as
it
is, but maybe I'll get used to it.
O
this sounds
like something impossible - feel free to give me a heads up :)
cheers,
Geoff Swan
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Last time I saw this error it was because when I saved the file, all
text fields were quoted.
Ie - instead of> version\t01
it read> "version"\t01
or something along those lines.
I fixed with vim...
:1,$s/\"//g
Geoff
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I am
ripping off their notation)
I am relatively new to gEDA - so I thought I would find out if this is
theoretically possible (or been done before) before I start trying to
write my
own script...
cheers,
Geoff Swan
Yes
On Mon, Mar 14, 2011 at 12:14 PM, Kai-Martin Knaak
<[1]k...@lilalaser.de> wrote:
Hi.
I am curious: Is anyone on the list using the footprints and/or
symbols in my department of [2]gedasymbols.org?
---<)kaimartin(>---
--
Kai-Martin Knaak
Email: [3]k.
I have done something like this by using multiple symbols for a single
device rather than slotting. From memory all that was required was to
ensure the pinseq are correct and the symbols are given the same
refdes.
I'm sure someone will correct me if I have missed something :P
On
> Remember to always store your iron tips with a ball of solder on them,
> this helps prevent the tip from corroding in storage.
>
> Don't wipe the tip before putting it back in the holder, your wipes on
> the moist sponge should be when you take the tip out of the holder.
>
> Again the molten sol
I like the multiple names solution. I hadn't run into this issue until
I came across gEDA symbols with hardcoded nets. Not a big issue, I
tend to modify symbols now on a per project basis - so the need to
have two net names for a single wire is much reduced.
__
DRM to prevent the user from
> changing his code when he could otherwise. The intent is to prevent
> GPLed code from being locked down, trusted computing style.
>
> On Wed, Oct 6, 2010 at 4:20 PM, Geoff Swan wrote:
>> So just to clarify - if you distribute an embedded device
So just to clarify - if you distribute an embedded device that runs a
GPLv3 binary; to comply with the GPLv3 you must not only provide the
source, but also a hardware-programmer/uploader?
I suppose in most cases this isn't necessarily a huge issue - where
firmware upgrade capability is built into t
For quick breadboarding of an accelerometer I've deadbug soldered one
successfully. Just superglued it upside down and soldered directly to
the pads with very thin wire..
On Mon, Sep 13, 2010 at 12:04 PM, DJ Delorie wrote:
>
>> does anyone have experience with this package?
>
> Just did one tod
I came across this
([1]http://www.tentlabs.com/InfoSupport/page35/files/Supply_decoupling.
pdf) some time ago. I would be interested to hear peoples thoughts as
there are clearly many differing views on correct grounding and supply
decoupling. The article certainly made a lot of sens
Bahahhahah! No. :P Not referring to you at all. My response
was targeted at timecop. Apologies if it my aim was off...
*I* am??
-Dave
On 6/15/10 11:38 PM, [1]shinobi.j...@gmail.com wrote:
Wow. You're really looking to start arguments
Sent via BlackBerry® from
Perhaps that's where the pain is, but customizing symbols takes little
time, so endure the brief pain and get on with it. You can't avoid it.
Even if you have a heavy symbol from somebody else's library, you have
to check it carefully, and that's almost as much work as customizing.
M
Hi, I am very interested to find out what you choose to use for this
sort of analysis. I have played a bit with qucs and agree that's a good
place to start. Please post back your findings!
Geoff
On Fri, Apr 30, 2010 at 6:08 AM, al davis <[1]ad...@freeelectron.net>
wrote:
Most tools require some preliminary investment in terms of setting up
libraries to the satisfaction of the user, plus general
familiarisation. I think you will find you only need to modify your
symbol once to include the appropriate SPICE directives. If you save
this symbol you can t
>> hardware. The capability comes from the programmer. This argument
>> seems similar to suggesting that somehow the canvas that Leonardo da
>> Vinci painted the Mona Lisa on contained the capability rather than
da
>> Vinci.
>
> The canvas could have supported a D
>>> Remember, the bare hardware without any software at all has the greatest
>>> potential. Every line of code added to the software system takes away from
>>> that potential. This is necessary, of course. You have the hardware for
>>> specific purposes, and the software serves these. But one sh
>One thing, I made it by copying the symbol for a triac. I did not pay
>careful attention to pin numbering. Am I going to regret that if I
>ever decide to do a layout / make a PCB?
I guess that depends if you got the numbering wrong :P
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> Never used "pcb View - Align Grid".
> What may be the intended function? My guess: If you realign grid, all
> other components will become off grid.
>
> What I did: Align the new component to the grid, by grabbing its center
> or a single pin. For aligning a single pin it may be necessary/helpful
I am having some trouble with pcb View - Align Grid. I am trying to
use it to align the snap grid to a component pin. However it is not
having any effect. I have tried various permutations of adjusting grid
size and units - turning snap to pin on and off and anything else that
I thought may potenti
+1 *hassle*
(i really like toporouter :)
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> I've seen commercial tools that have some predefined grids like rectangular,
> polar, smith but so far none have taken it to the next level of letting you
> add custom ones or the custom readout.
Just in case you missed it - qucs has a number of plotting outputs
including a Smith chart. I don't
>Seriously - simulating for things like this is not going to be the best
>way to design circuits.. physical variation between parts, and
>discrepancies between the model and reality, plus limited choices of
>real-world resistor values will mean it is pretty pointless trying to
>get any more accurat
Ignoring the response(s) from timecop, I don't believe the suggestion
to try sot-23 was intended to be either elitist or unhelpful. *if* the
option to use a different footprint is available then in many cases
there is a great deal of advantage to using the sot-23 layout. If the
work is being done b
>> What's considered Best Practices for TO-92 packages?
>>
>
> Redesign with SOT-23. Easier to solder, faster than stuffing TO-92.
+1
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> don't even consider ordering boards without loading up the photoplot files
> into something like gerbv and doing some sanity checks. This advice applies
> to a design done with any layout tool and not just pcb. A minimal list would
> be:
>
> - From 20,000 feet, does each layer look right or are
I have daydreamed about the possibility of linking gEDA with qucs and
simavr/gdb for example. To be able to create a circuit layout and
perform harmonic ballance simulation combined with microcontroller
code simulation... Oh, and while I daydream, an integrated tool for
doing FEM analysis the pcb d
> Please run gschlas -e .sch and post the result to the list.
>
> Thanks,
cat untitled.sch~
v 20090328 2
C 4 4 0 0 0 title-B.sym
C 47800 46400 1 0 0 resistor-1.sym
{
T 48100 46800 5 10 0 0 0 0 1
device=RESISTOR
T 48000 46700 5 10 1 1 0 0 1
refdes=R1
T 47600 46200 5 10 1 0 0 0 1
footprint=
On Thu, Feb 18, 2010 at 8:59 AM, Steven Michalske wrote:
> here is what i got
>
> V3 R1-1
> V5 R1-2
>
> with
>
> gsch2pcb --version
> gsch2pcb 1.6
Ditto.
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