On Wed, Oct 08, 2008 at 07:56:27AM +0200, Bert Timmerman wrote:
>
> I notice that both rat lines on the pads with circles (in C600 and C601)
> have the "via" flag set.
>
> I wonder, what could have triggered this ?
It's supposed to happen when you're over a rectangle in the target net.
I added t
On Wed, 2008-10-08 at 07:56 +0200, Bert Timmerman wrote:
> Hi Stefan,
>
> FWIW,
>
> I notice that both rat lines on the pads with circles (in C600 and C601)
> have the "via" flag set.
>
> I wonder, what could have triggered this ?
>
> Is it that the layer named "component" is not defined to be
Hi Stefan,
FWIW,
I notice that both rat lines on the pads with circles (in C600 and C601)
have the "via" flag set.
I wonder, what could have triggered this ?
Is it that the layer named "component" is not defined to be on the
component side (04) of the board, but is defined as an inner layer
(02
Stefan Salewski wrote:
> Am Dienstag, den 07.10.2008, 18:12 -0400 schrieb Rob Butts:
>> I did read the thread. I would like to modify the symbol so that the
>>part in pcb does not have the G, D or S. I'd like it to just have the
>>flat side of the transistor.
>
> Sorry, I can not really
Am Dienstag, den 07.10.2008, 18:12 -0400 schrieb Rob Butts:
> I did read the thread. I would like to modify the symbol so that the
>part in pcb does not have the G, D or S. I'd like it to just have the
>flat side of the transistor.
Sorry, I can not really understand your problem.
You men
Am Dienstag, den 07.10.2008, 23:58 +0200 schrieb Stefan Salewski:
>
> Done -- same bug.
>
And it's the same with Thru hole footprints -- tested with CONN600 of
b2.pcb.
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I did read the thread. I would like to modify the symbol so that the
part in pcb does not have the G, D or S. I'd like it to just have the
flat side of the transistor.
On Tue, Oct 7, 2008 at 5:07 PM, Stefan Salewski <[EMAIL PROTECTED]>
wrote:
Am Dienstag, den 07.10.2008, 16:
Am Dienstag, den 07.10.2008, 18:34 +0200 schrieb Stefan Salewski:
> I will myself make a test with a
> layout created from scratch.
>
Done -- same bug.
I used a other, simple schematic used gsch2pcb to generate initial
board, opened board with pcb, imported netlist, dispersed elements, draw
a
All of my boards are in version control. so they all are really
tied together well.
i just check out a revision of that repository that has everything
where it was back then and it just works.
it might be cool to put geda and gschem in the mix at that level too,
so that the tools used
Am Dienstag, den 07.10.2008, 16:08 -0400 schrieb Rob Butts:
> Does antone know where I would find the symbol file for the pnp-3.sym
>symbol in the basic devices library?
This IS a symbol file (for gschem).
Are you locking for the corresponding Footprint (pcb element)?
I think there is no speci
Does antone know where I would find the symbol file for the pnp-3.sym
symbol in the basic devices library?
On Tue, Oct 7, 2008 at 12:47 PM, Stefan Salewski
<[EMAIL PROTECTED]> wrote:
Am Montag, den 06.10.2008, 16:57 -0400 schrieb Rob Butts:
> I'm using the pnp-3.sym symbol f
I've found a "quick & dirty" workaround. I attach to such "pure" nets the
testpoints with refdes set to RMV? (? is then replaced with a number).
It assures proper generation of the netlist.
Then I filter the network with the command:
$cat generated.net | sed -e s/RMV[0-9]*-1// > filtered.net
It r
On Oct 6, 2008, at 1:18 AM, Wojciech Zabolotny wrote:
>> Do you really need multiple netnames for the same net?
>>
>> I did it this way, see
>>
>> http://www.ssalewski.de/Controller.pdf
>>
>> My Connector has pin names like MOSI.
>>
>> I use a io.sym symbol with attribute net=uC_MOSI:1 and conne
Op dinsdag 07-10-2008 om 13:22 uur [tijdzone -0400], schreef DJ Delorie:
> > Hold the mouse pointer over a component and press the F ("Find") key.
>
> I just tried that, and it doesn't work for me.
Indeed, you're right -- this only works with nets (traces), no with
components. My apologies.
Rich
Hi Stefan,
FWIW, I do not understand these circles myself either, but I do notice
that if you connect them on the "GND" layer they seem to connect, and
that these circles do not connect on "solder" or "component" layers.
Maybe these circles "know" that an intermediate layer and via is
required ?
> Hold the mouse pointer over a component and press the F ("Find") key.
I just tried that, and it doesn't work for me.
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Am Dienstag, den 07.10.2008, 11:19 +0400 schrieb Ineiev:
> Won't it miss DRC errors? I'd prefer false alarms.
>
Smart rounding should work.
Multiplying entered Clearance my something like 0.999 or subtraction of
one internal unit (0.01 mil) should really make no problem, but prevent
entering of
> I'd be interested to see this test-case too. I'm sure I've hit similar
> problems.
I've reproduced Stefan's problem, with his board, with the latest pcb.
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Op maandag 06-10-2008 om 15:52 uur [tijdzone -0400], schreef Rob Butts:
> Can you select a component in pcb and highlight all components
> connected to it?
Hold the mouse pointer over a component and press the F ("Find") key.
Press Shift+F to undo the highlight.
Best regards,
Richard Rasker
On Tue, 2008-10-07 at 18:34 +0200, Stefan Salewski wrote:
> Am Montag, den 06.10.2008, 10:55 -0700 schrieb Ben Jackson:
> >
> > Is it possible you optimized the ratlist while they were over a polygon
> > and then moved them? The ratlist never reevaluates due to dragging a part.
> > For normal rat
Can you select a component in pcb and highlight all components
connected to it?
Thanks
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Am Montag, den 06.10.2008, 10:55 -0700 schrieb Ben Jackson:
>
> Is it possible you optimized the ratlist while they were over a polygon
> and then moved them? The ratlist never reevaluates due to dragging a part.
> For normal rats this just means less optimal lines running around, but if
> you ha
Hi, Stefan;
On Sun, Oct 5, 2008 at 11:21 PM, Stefan Salewski <[EMAIL PROTECTED]> wrote:
> I have 0.5 mm grid size, 0.25 mm line width and 0.25 mm "Minimum copper
> spacing" in Preferences/Design Rule Checking.
>
> It was clear for me that this can cause problems -- indeed it does.
> Sometimes it i
Am Montag, den 06.10.2008, 16:57 -0400 schrieb Rob Butts:
> I'm using the pnp-3.sym symbol from the Basic devices library in
>gschem. The symbol is drawn in pcb with a "G" "D" and "S at each pin
npn transistors really should not have "G" "D" and "S", this is for
MOSFET.
It can be necessary
I'm using the pnp-3.sym symbol from the Basic devices library in
gschem. The symbol is drawn in pcb with a "G" "D" and "S at each pin
eventhough the footprint I'm using doesn't have those abbreviations.
I listed the footprint file is below:
Element["" "" "" "TO92_EBC" 173228 66929
> "Steven" == Steven Michalske <[EMAIL PROTECTED]> writes:
> i put mine into source control, so that i can go back in time and work
> on old files easily enough
> when schematics reference a symbol you used years ago and you have
> updated it, you may need the older one for the schematic.
On Mon, Oct 06, 2008 at 07:05:47PM +0200, Stefan Salewski wrote:
> I have seen these circles indicating a connection to a plane in DJ's
> tutorial for the first time. Now I get these myself. I do not understand
> it really, and I do not want it, because there in no plane.
Is it possible you optimi
Could you measure everything in mils and see what aspect of it is off?
It looks like 0.30mm rounds down to 11.81 mils, but 0.15mm rounds up
to 5.91 mils, we'd need to think about how we consider rounding at
each stage in order for it to always come out right.
Am Montag, den 06.10.2008, 19:05 +0200 schrieb Stefan Salewski:
>howto get plain rats lines instead of circles
I think it is a bug.
On left and right side of FPGA/Planes all works as expected, on top and
below not. Maybe an error in y coordinate (vertically).
I have deleted all planes -- now I
> "Stefan" == Stefan Salewski <[EMAIL PROTECTED]> writes:
> I have 0.5 mm grid size, 0.25 mm line width and 0.25 mm "Minimum
> copper spacing" in Preferences/Design Rule Checking.
> It was clear for me that this can cause problems -- indeed it does.
> Sometimes it is not possible to draw copp
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