Fairly trivial patch that introduces no functional changes.
* config/mips/mips.h (MIPS_STACK_ALIGN): Implement using
ROUND_UP macro.
* config/mips/mips.c (mips_setup_incoming_varargs): Use
ROUND_DOWN to calculate off.
(mips_gimplify_va_arg_expr): Use ROUND_UP to calculate rsize
On Tue, Oct 13, 2015 at 12:10 PM, Eric Botcazou wrote:
>> Two functional changes I'd like to point out:
>>
>> /* ALIGN FRAMES on double word boundaries */
>> -#define SPARC_STACK_ALIGN(LOC) \
>> - (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
>> +#define SPARC_STACK_ALIGN(LOC) ROUND_UP
; Is that fine?
OK, but to avoid ABI mismatches, please double check that enum values
passed between library and compiled code are always the same in all
gcc releases.
Uros.
> Regards,
> Venkat.
>
>> -Original Message-
>> From: Kumar, Venkataramanan
>> Sent: F
No functional changes.
2015-10-13 Uros Bizjak
* config/i386/i386.c (classify_argument): Use CEIL where applicable.
(ix86_function_arg_advance): Ditto.
(ix86_function_arg): Ditto.
(ix86_gimplify_va_arg): Ditto.
(ix86_class_max_nregs): Ditto.
(inline_memory_move_cost
Attached patch fixes PR 67967, where we emit REG_CFA_EXPRESSION,
attached to aligned SSE store. This is unnecessary, and confuses SEH
targets.
2015-10-14 Uros Bizjak
PR target/67967
* config/i386/i386.c (ix86_emit_save_reg_using_mov): Do not add
REG_CFA_EXPRESSION to aligned SSE
On Wed, Oct 14, 2015 at 11:38 PM, Matthew Fortune
wrote:
> Uros Bizjak writes:
>> Fairly trivial patch that introduces no functional changes.
>>
>> * config/mips/mips.h (MIPS_STACK_ALIGN): Implement using
>> ROUND_UP macro.
>> * config/mips/mips.c (
On Wed, Oct 14, 2015 at 5:17 PM, H.J. Lu wrote:
> On Wed, Oct 14, 2015 at 8:15 AM, H.J. Lu wrote:
>> On Wed, Oct 14, 2015 at 8:08 AM, Yulia Koval wrote:
>>> Hi,
>>>
>>> This patch fixes the issue:
>>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67963
>>>
>>> gcc/config/i386/i386.c (ix86_optio
On Wed, Oct 14, 2015 at 5:08 PM, Yulia Koval wrote:
> Hi,
>
> This patch fixes the issue:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67963
>
> gcc/config/i386/i386.c (ix86_option_override_internal) Disable
> 80387 mask if lakemont target is set.
>
> diff --git a/gcc/config/i386/i386.c b/
On Thu, Oct 15, 2015 at 1:45 PM, Uros Bizjak wrote:
> On Wed, Oct 14, 2015 at 5:08 PM, Yulia Koval wrote:
>> Hi,
>>
>> This patch fixes the issue:
>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67963
>>
>> gcc/config/i386/i386.c (ix86_option_override
On Thu, Oct 15, 2015 at 6:59 PM, H.J. Lu wrote:
> On Thu, Oct 15, 2015 at 9:57 AM, Uros Bizjak wrote:
>> On Thu, Oct 15, 2015 at 1:45 PM, Uros Bizjak wrote:
>>> On Wed, Oct 14, 2015 at 5:08 PM, Yulia Koval wrote:
>>>> Hi,
>>>>
>>>> This pa
On Thu, Oct 15, 2015 at 9:21 PM, H.J. Lu wrote:
> On Thu, Oct 15, 2015 at 12:16 PM, Uros Bizjak wrote:
>> On Thu, Oct 15, 2015 at 6:59 PM, H.J. Lu wrote:
>>> On Thu, Oct 15, 2015 at 9:57 AM, Uros Bizjak wrote:
>>>> On Thu, Oct 15, 2015 at 1:45 PM, Uros Bizjak wro
On Thu, Oct 15, 2015 at 9:30 PM, Uros Bizjak wrote:
>>>> Do we support -O2 -march=lakemont with
>>>>
>>>> __attribute__((target("arch=silvermont")))
>>>
>>> Hm, no.
>>>
>>
>> Do we issue an error or silently ig
On Fri, Oct 16, 2015 at 8:43 AM, Uros Bizjak wrote:
> On Thu, Oct 15, 2015 at 9:30 PM, Uros Bizjak wrote:
>
>>>>> Do we support -O2 -march=lakemont with
>>>>>
>>>>> __attribute__((target("arch=silvermont")))
>>>>
>>&g
On Fri, Oct 16, 2015 at 7:42 PM, H.J. Lu wrote:
> Since GET_MODE_ALIGNMENT is defined by psABI and the biggest alignment
> is 4 byte for IA MCU psABI, we should use GET_MODE_BITSIZE to get
> vector natural alignment to check misaligned vector move.
>
> OK for trunk?
>
> Thanks.
>
> H.J.
> ---
>
On Sat, Oct 17, 2015 at 12:38 AM, H.J. Lu wrote:
> When processing __attribute__ ((target("arch=XXX"))), we should clear
> the ISA bits in x_ix86_isa_flags first to avoid leaking ISA from
> command line.
>
> Tested on x86-64. OK for trunk?
OK.
Thanks,
Uros.
> Thanks.
>
> H.J.
> ---
> gcc/
>
>
On Mon, Oct 19, 2015 at 1:12 PM, H.J. Lu wrote:
> On Mon, Oct 19, 2015 at 4:05 AM, Uros Bizjak wrote:
>> On Fri, Oct 16, 2015 at 7:42 PM, H.J. Lu wrote:
>>> Since GET_MODE_ALIGNMENT is defined by psABI and the biggest alignment
>>> is 4 byte for IA MCU psABI, we sho
On Sat, Oct 17, 2015 at 4:30 AM, H.J. Lu wrote:
> -miamcu specifies how parameters are passed to functions and how value
> is returned from a function. Inside function, we can use instructions
> supported by -march=XXX. -miamcu -march=haswell can generate x87, SSE
> and AVX instructions as long
... plus some cleanups due to unused macro argument.
No functional changes.
2015-10-20 Uros Bizjak
* config/alpha/alpha.h (HARD_REGNO_NREGS): Use CEIL macro.
(ALPHA_ARG_SIZE): Ditto. Remove unused NAMED argument.
* config/alpha/alpha.c (alpha_function_arg_advance): Update
just need to enable correct code paths when
incoming stack boundary is less than 16 bytes. This is exactly what
the attached patch does.
2015-10-21 Uros Bizjak
PR target/68018
* config/i386/i386.c (ix86_compute_frame_layout): Realign the stack
for 64-bit MS_ABI targets also when
2015-10-22 Uros Bizjak
* gcc.target/i386/pr67985-3.c (dg-options): Add -mfpmath=sse.
Tested on x86_64-linux-gnu {,-m32} and committed to mainline SVN.
Uros.
Index: gcc.target/i386/pr67985-3.c
===
--- gcc.target/i386/pr67985
Hello!
Inverted condition is generated with =@ccae.
2015-10-25 Uros Bizjak
PR target/68084
* config/i386/i386.c (ix86_md_asm_adjust) [case 'a']: Use NE code
for =@ccae.
testsuite/ChangeLog:
2015-10-25 Uros Bizjak
PR target/68084
* gcc.target/i386/pr68084.c
On Tue, Oct 27, 2015 at 12:37 PM, H.J. Lu wrote:
> On Tue, Oct 27, 2015 at 4:20 AM, Bernd Schmidt wrote:
>> On 10/19/2015 09:55 PM, H.J. Lu wrote:
>>>
>>> * calls.c (prepare_call_address): Don't handle -fno-plt here.
>>
>>
>> Is any other target using -fno-plt? If not, and if that's real
On Thu, Oct 29, 2015 at 2:16 PM, Kumar, Venkataramanan
wrote:
> Hi Uros,
>
> As per your comments in
> https://gcc.gnu.org/ml/gcc-patches/2015-09/msg02326.html please find the
> patch that also adds changes to libgcc.
>
> It was bootstrapped and regressed tested on x86_64.
>
> Ok for trunk?
>
>
Hello!
Attached patch improves pr67609-2.c testcase with the SSE2 runtime
test framework.
2015-11-01 Uros Bizjak
* gcc.target/i386/pr67609-2.c: Include sse2-check.h.
(sse2_test): Rename from main. Do not return 0.
Tested on x86_64-linux-gnu {,-m32} and committed to mainline SVN
Hello!
> I have committed a patch to libgo to update it to the Go 1.5 release.
>
> As usual for libgo updates, the actual patch is too large to attach to
> this e-mail message. I've attached the changes to the gccgo-specific
> files.
>
> Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu.
... and add ifunc effective target requirement where necessary.
2015-11-03 Uros Bizjak
* gcc.dg/mvc1.c: Move to ...
* gcc.target/i386/mvc1.c: ... here. Require ifunc.
* gcc.dg/mvc2.c: Move to ...
* gcc.target/i386/mvc2.c: ... here.
* gcc.dg/mvc3.c: Move to
On Tue, Nov 3, 2015 at 3:16 PM, Yulia Koval wrote:
> Hi,
>
> This patch fixes a typo: PROCESSOT -> PROCESSOR. Ok for trunk?
Trivial patch, OK with a suitable ChangeLog.
Uros.
for unaligned
input, so the bug is benign, but nevertheless, we should use the
correct value.
2015-11-03 Uros Bizjak
* lex.c (search_line_sse42): Correctly advance the pointer to an
aligned address.
Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed t
On Fri, Nov 6, 2015 at 3:07 PM, Yulia Koval wrote:
> Hi,
>
> I updated and reposted the patch. Regtested/bootstraped on
> x86_64/Linux and i686/Linux. Ok for trunk?
This version still emits insns from ix86_function_arg, so NAK.
Uros.
On Sat, Nov 7, 2015 at 3:34 AM, Segher Boessenkool
wrote:
> Adding x86 maintainer, ping?
>
> On Fri, Oct 16, 2015 at 05:53:41AM -0700, Segher Boessenkool wrote:
>> For x86, STC still gives better results for optimise-for-size than
>> "simple" does. So use STC at -Os as well.
>>
>> Is this okay fo
On Sun, Nov 8, 2015 at 9:58 PM, Segher Boessenkool
wrote:
> On Fri, Nov 06, 2015 at 04:00:08PM -0600, Segher Boessenkool wrote:
>> This patch stops combine from generating widening muls of anything else
>> but registers (immediates, memory, ...). This probably is a reasonable
>> tradeoff for all
We don't have to use cilk.h convenience header.
2015-11-09 Uros Bizjak
* g++.dg/cilk-plus/CK/pr66326.cc: Do not include cilk.h.
(main): Use _Cilk_spawn instead of cilk_spawn.
Tested on x86_64-linux-gnu and committed to mainline SVN.
Uros.
Index: g++.dg/cilk-plus/CK/pr663
On Mon, Nov 9, 2015 at 5:28 PM, Richard Sandiford
wrote:
> After the previous patches it's no longer necessary for
> TARGET_BUILTIN_VECTORIZED_FUNCTION to return functions that
> map to the vector optab of the original operation. We'll use
> a vector form of the internal function instead.
>
>
> g
2015-11-09 Uros Bizjak
* config/i386/i386.md (*strmovqi_1): Fix insn enable condition.
Tested on x86_64-linux-gnu {,-m32} and committed to mainline SVN.
Uros.
Index: config/i386/i386.md
===
--- config/i386/i386.md (revision
On Tue, Nov 10, 2015 at 12:54 PM, Yulia Koval wrote:
> Hi,
>
> This patch fixes the issue, when target(arch="haswell") function was
> chosen instead of target(arch="skylake") on skylake. Ok for trunk?
>
> gcc/
> * config/i386/i386.c: Handle "skylake" and
> "skylake-avx512".
>
> gcc/tests
Hello!
Recent AS patches introduced the above compilation failure. We have to
treat movabs operands in a special way - without %rip and inside
square bracket for -masm=intel.
Also, the patch removes dead code while at it.
2015-11-10 Uros Bizjak
* config/i386/i386.c (ix86_print_operand
On Tue, Nov 10, 2015 at 7:00 PM, Richard Henderson wrote:
> On 11/10/2015 06:54 PM, Uros Bizjak wrote:
>>
>> - return "movabs{}\t{%1, %0|%0, %1}";
>> + return "movabs{}\t{%1, %P0|[%P0], %1}";
>
>
> The thing that's missing from
On Tue, Nov 10, 2015 at 7:14 PM, Uros Bizjak wrote:
> On Tue, Nov 10, 2015 at 7:00 PM, Richard Henderson wrote:
>> On 11/10/2015 06:54 PM, Uros Bizjak wrote:
>>>
>>> - return "movabs{}\t{%1, %0|%0, %1}";
>>> + return "movabs{}\t{%1,
2015-11-11 Uros Bizjak
* config/alpha/alpha-protos.h (print_operand): Remove.
(print_operand_address): Remove.
* config/alpha/alpha.h (PRINT_OPERAND): Remove.
(PRINT_OPERAND_ADDRESS): Remove.
(PRINT_OPERAND_PUNCT_VALID_P): Remove.
* config/alpha/alpha.c
Hello!
Attached patch uses ssememalign attribute to reject insn combinations
where memory operands would be misaligned.
2015-11-12 Uros Bizjak
* config/i386/i386.c (ix86_legitimate_combined_insn): Reject
combined insn if the alignment of vector mode memory operand
is less than
2015-11-12 Uros Bizjak
* config/alpha/alpha.h (FUNCTION_VALUE, LIBCALL_VALUE,
FUNCTION_VALUE_REGNO_P): Remove.
* config/alpha/alpha-protos.h (function_value): Remove.
* config/alpha/alpha.c (function_value): Rename to...
(alpha_function_value_1): ... this. Make static
Hello!
> this patch rotates the loop generated in the prologue to do stack checking
> when -fstack-check is specified, thereby saving one branch instruction. It
> was initially implemented as a WHILE loop to match the generic implementation
> but can be turned into a DO-WHILE loop because the amo
Hello!
We have to check natural alignment of the operand in
misaligned_operand predicate. This predicate is used to check SSE
memory operands for alignment, when movaps instead of movups can be
used. This change makes predicate independent of BIGGEST_ALIGNMENT
setting.
2015-11-13 Uros Bizjak
Hello!
> 2015-11-09 Segher Boessenkool
>
> * gcc/simplify-rtx.c (simplify_truncation): Simplify TRUNCATE
> of AND of [LA]SHIFTRT.
Revision r230164 (the above patch) regressed:
FAIL: gcc.target/alpha/pr42269-1.c scan-assembler-not addl
on alpha-linux-gnu.
The difference starts in combine, wh
On Fri, Nov 13, 2015 at 11:10 AM, Kyrill Tkachov wrote:
> Hi all,
>
> On 10/11/15 19:53, Segher Boessenkool wrote:
>>
>> On Mon, Nov 09, 2015 at 03:51:32AM -0600, Segher Boessenkool wrote:
>From the original patch submission, it looks that this patch would
also benefit x86_32.
>>>
>
Hello!
> 2015-11-13 Richard Biener
>
> PR tree-optimization/68306
> * tree-vect-data-refs.c (verify_data_ref_alignment): Move
> loop related checks ...
> (vect_verify_datarefs_alignment): ... here.
> (vect_slp_analyze_and_verify_node_alignment): Compute and
> verify alignment of the single DR t
On Fri, Nov 13, 2015 at 3:36 PM, Segher Boessenkool
wrote:
> Hi!
>
> On Fri, Nov 13, 2015 at 11:02:55AM +0100, Uros Bizjak wrote:
>> on alpha-linux-gnu.
>>
>> The difference starts in combine, where before the patch, we were able
>> to combine insns:
&g
On Fri, Nov 13, 2015 at 2:15 PM, Uros Bizjak wrote:
>> 2015-11-13 Richard Biener
>>
>> PR tree-optimization/68306
>> * tree-vect-data-refs.c (verify_data_ref_alignment): Move
>> loop related checks ...
>> (vect_
On Fri, Nov 13, 2015 at 9:47 PM, Bernd Schmidt wrote:
> This adds a new -mmitigate-rop option to the i386 port. The idea is to
> mitigate against certain forms of attack called "return oriented
> programming" that some of our security folks are concerned about. The basic
> idea is that the stack g
This test uses NaN, so it requires ieee options for certain targets.
2015-11-17 Uros Bizjak
* gcc.dg/torture/pr68264.c: Use dg-add-options ieee.
Tested on alphaev68-linux-gnu and committed to mainline SVN.
Uros.
Index: gcc.dg/torture/pr68264.c
Hello!
Attached patch fixes PR 68263. IAMCU ABI doesn't guarantee any
alignment, so we have to emit unaligned moves for SSE or AVX unaligned
operands.
2015-11-17 Uros Bizjak
PR target/68263
* config/i386/i386.h (BIGGEST_ALIGNMENT): Always define
to 32 for IAMCU.
* config
> I fixed this with the below patch. Tested on x86_64 linux, x86_64 darwin and
> my port. If you want to
> list aarch64/arn and mips, please do.
>
> * g++.dg/init/vbase1.C: Only run on x86_64-*-* as this testcase
> isn't portable.
I have added i?86-*-* to the list.
On Sun, Nov 22, 2015 at 11:38 AM, Richard Henderson wrote:
> The full round of testing from v1 turned up a couple of problems.
>
> One of which I believe I've worked around in the i386 backend, but I believe
> to be a latent problem within combine.
>
> With the following patch, disable the add3_*_
Hello!
> 2015-11-25 Victoria Stepanyan
>
> * common/config/i386/i386-common.c
> (OPTION_MASK_ISA_CLZERO_SET): New.
> (ix86_handle_option): Handle clzero.
>* config.gcc (i[34567]86-*-*): Add clzerointrin.h,
> (x86_64-*-*): Likewise.
> * config/i386/
Hello!
> gcc/
>
> 2015-11-26 Vladimir Makarov
>
> PR target/68416
> * config/i386/i386.h (enum reg_class): Add
> bounds registers to ALL_REGS.
>
> gcc/testsuite/
>
> 2015-11-26 Ilya Enkovich
>
> PR target/68416
> * gcc.target/i386/mpx/pr68416.c: New test.
OK for mainline and gcc-5 after gcc
On Thu, Nov 26, 2015 at 12:46 PM, Ilya Enkovich wrote:
> 2015-11-26 13:15 GMT+03:00 Uros Bizjak :
>>> 2015-11-26 Vladimir Makarov
>>>
>>> PR target/68416
>>> * config/i386/i386.h (enum reg_class): Add
>>> bounds registers to ALL_REGS.
>>
On Mon, Nov 30, 2015 at 10:38 PM, Bernd Schmidt wrote:
> On 11/27/2015 10:02 AM, Bernd Schmidt wrote:
>>
>> This is a patch for PRs 68471 and 68472, which show problems with the
>> ROP mitigation:
>> * reg-stack doesn't call df_insn_update when it makes changes, and
>> if df checking is enab
Hello!
> 2015-11-29 Andreas Tobler
>
> * config/i386/i386.h: Define two new macros:
> SUBTARGET_SHADOW_OFFSET_64 and SUBTARGET_SHADOW_OFFSET_32.
> * config/i386/i386.c (ix86_asan_shadow_offset): Use these macros.
> * config/i386/darwin.h: Override the SUBTARGET_SHADOW_OFFSET_64
> macro.
> * con
On Thu, Dec 3, 2015 at 9:52 PM, Jakub Jelinek wrote:
> Hi!
>
> As discussed in the PR, for some permutation we can get better code
> if we try to expand it as if it was a permutation in a mode with the
> same vector size, but wider vector element. The first attempt to do this
> always had mixed r
No functional changes.
2015-12-08 Uros Bizjak
* config/i386/i386.c (ix86_emit_swsqrtsf): Cleanup
infinity filterning code.
Bootstrapped and regression tested on x86_64-linux-gnu, committed to
mainline SVN.
Uros.
Index: config/i386/i386.c
On Tue, Dec 8, 2015 at 11:40 AM, Kirill Yukhin wrote:
> Hello,
> On 08 Dec 09:47, Andreas Schwab wrote:
>> FAIL: gfortran.dg/pr68627.f -O (test for excess errors)
>> Excess errors:
>> gfortran: error: unrecognized command line option '-mavx512f'
> Thanks for pointing.
>
> I've checked in this a
Hello!
> this patch fixes the asm statements in the gcc.target/i386/sse4_1-round* test
> cases.
>
> They do lots of things that are just absolutely forbidden, like clobber
> registers
> that are not mentioned in the clobber list, and create a hidden data flow.
>
> The test cases work just by cha
On Tue, Dec 8, 2015 at 7:10 PM, Uros Bizjak wrote:
> Hello!
>
>> this patch fixes the asm statements in the gcc.target/i386/sse4_1-round*
>> test cases.
>>
>> They do lots of things that are just absolutely forbidden, like clobber
>> registers
>> that
what the patch does, in addition to
emitting an informative warning.
2015-12-08 Uros Bizjak
PR target/68701
* config/i386/i386.c (ix86_option_override_internal): Enable
-maccumulate-outgoing-args when %ebp is fixed due to stack
realignment requirements.
testsuite/ChangeLog:
2015
On Tue, Dec 8, 2015 at 9:13 PM, Bernd Edlinger
wrote:
> Hi,
>
> Am 08.12.2015 um 19:23 schrieb Uros Bizjak:
>> On Tue, Dec 8, 2015 at 7:10 PM, Uros Bizjak wrote:
>>> Hello!
>>>
>>>> this patch fixes the asm statements in the gcc.target/i386/sse4_1-ro
This patch adds the test for the fixed PR.
2015-12-09 Uros Bizjak
PR c++/68348
PR c++/68464
* g++.dg/pr68348.C: New test.
Tested on x86_64-linux-gnu.
OK for mainline?
Uros.
Index: g++.dg/pr68348.C
===
--- g++.dg
On Wed, Dec 9, 2015 at 8:18 AM, Uros Bizjak wrote:
> Saying that, I see we don't need to define ASM_SUFFIX anymore. I'll
> prepare the patch that removes these #defines.
2015-12-09 Uros Bizjak
* gcc.target/i386/sse4_1-roundps-1.c: Remove ASM_SUFFIX define.
* gcc.ta
> Finally the mechanical changes necessary due to the API change in the walker.
You forgot to change the graphite part, as in the attached patch.
2015-12-10 Uros Bizjak
PR tree-optimization/68619
* graphite-scop-detection.c (gather_bbs::before_dom_children):
Change return type
On Thu, Feb 13, 2020 at 9:39 AM Uros Bizjak wrote:
> > Changelog
> > gcc/
> >* config/i386/avx512vbmi2intrin.h
> >(_mm512_[,mask_,maskz_]shrdi_epi16,
> >_mm512_[,mask_,maskz_]shrdi_epi32,
> >_m512_[,mask_,maskz_]shrdi_epi
Default testsuite flags do not enable V8QI (MMX) vector mode for
32bit x86 targets. Require vect_multiple_sizes effective target in
scan-tree-dump to avoid "LOOP EPILOGUE VECTORIZED" failure.
Tested on x86_64-linux-gnu {,-m32}.
2020-02-19 Uroš Bizjak
* gcc.dg/vect/vect-epilogues.c (scan-tree
testsuite: Add -msse2 to fix ia32 tests.
Tested on x86_64-linux-gnu {,-m32}.
2020-02-19 Uroš Bizjak
* gcc.dg/gimplefe-41.c: Add -msse2 additional options for x86 targets.
* gcc.dg/ipa/ipa-sra-19.c: Ditto.
Uros.
diff --git a/gcc/testsuite/gcc.dg/gimplefe-41.c
b/gcc/testsuite/gcc.dg/g
shufps moves two of the four packed single-precision floating-point values
from *destination* operand (first operand) into the low quadword of the
destination operand. Match source operand to the destination.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline.
This testcase is susceptible to memory location details and start to fail
with default to -fno-common. Use -fcommon to set expected testing conditions.
Tested on x86_64-linux-gnu {,-m32}.
2020-02-21 Uroš Bizjak
* gcc.target/i386/pr69052.c: Require target ia32.
(dg-options): Add -fcom
*movstrict_1 insn pattern allows only general registers,
so we have to reject modes not suitable for general regs in
corresponding movstrict expander.
2020-03-02 Uroš Bizjak
PR target/93997
* config/i386/i386.md (movstrict): Allow only
registers with VALID_INT_MODE_P modes.
testsu
asan_test.cc tries to allocate 0xf000 bytes for 32bit targets in
a disabled DISABLED_DemoOOM test. Since the testcase is compiled with
-Werror, the compilation fails with:
error: argument 1 value '4026531840' exceeds maximum object size 2147483647
Compile with -Wno-alloc-size-larger-than to
On Tue, Mar 10, 2020 at 7:39 AM Jakub Jelinek wrote:
>
> Hi!
>
> In r10-1938-g460bf043c8266dd080308f4783137aee0d0f862c *testdi_1 has been
> changed, so that if the mask has upper 32-bits 0 and then at least one bit
> set, it requires CCZmode rather than CCNOmode, because in that case it uses
> tes
The function needs more than 8 SSE registers, avoid
false positives triggered by SSE spills for 32bit targets.
2020-03-10 Uroš Bizjak
* g++.dg/pr80481.C (dg-final): Scan for SSE reg-reg moves only.
Tested on x86_64-linux-gnu {,-m32}.
Uros.
diff --git a/gcc/testsuite/g++.dg/pr80481.C b/gc
On Wed, Sep 25, 2019 at 5:48 PM Richard Sandiford
wrote:
>
> Ping
>
> Richard Sandiford writes:
> > One of the effects of the function_abi series is to make -fipa-ra
> > work for partially call-clobbered registers. E.g. if a call preserves
> > only the low 32 bits of a register R, we handled the
On Mon, Sep 30, 2019 at 9:01 AM Jakub Jelinek wrote:
>
> Hi!
>
> The recent SUBREG simplification changes aren't as forgiving in the past and
> ICE on invalid constants, in this case CONST_VECTOR:V8SI with 8x CONST_INT
> 0x8000 element, which is invalid, because for SImode it needs to be sign
On Tue, Oct 1, 2019 at 10:59 AM Alexandre Oliva wrote:
>
> flag_omit_frame_pointer is set in machine-independent code depending
> on the optimization level. It is then overridden in x86
> target-specific code depending on a macro defined by
> --enable-frame-pointer.
>
> Uses of attribute optimize
On Wed, Sep 25, 2019 at 5:48 PM Richard Sandiford
wrote:
> > The comment suggests that this code is only needed for Win64 and that
> > not testing for Win64 is just a simplification. But in practice it was
> > needed for correctness on GNU/Linux and other targets too, since without
> > it the RA
>>> This caused:
>>>
>>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91994
>
> Thanks for reducing & tracking down the underlying cause.
>
>> This change doesn't work with -mzeroupper. When -mzeroupper is used,
>> upper bits of vector registers are clobbered upon callee return if any
>> MM/ZMM re
On Sun, Oct 6, 2019 at 4:32 PM Richard Sandiford
wrote:
>
> Uros Bizjak writes:
> >>>> This caused:
> >>>>
> >>>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91994
> >>
> >> Thanks for reducing & tracking down the unde
Put some functions to a better place.
2019-10-07 Uroš Bizjak
* config/i386/i386-expand.c (ix86_expand_floorceildf_32,
ix86_expand_rounddf_32): Reorder functions.
* config/i386/i386-protos.h: Update..
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mai
> Some x86 tests of stack realignment, that disaligned the stack with
> pushes and pops, failed when the compiler was configured to tune for a
> target that preferred to accumulate outgoing arguments: the stack
> space is reserved before the asm push, the call sequence overwrites
> the saved regist
preserves some
256-bit SSE registers.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
On Tue, Oct 1, 2019 at 12:14 PM Uros Bizjak wrote:
>
> On Wed, Sep 25, 2019 at 5:48 PM Richard Sandiford
> wrote:
>
> > > The comment sugge
We have to handle (skip) DEBUG_INSN in alpha_handle_trap_shadows.
2019-10-10 Uroš Bizjak
PR target/92022
* config/alpha/alpha.c (alpha_handle_trap_shadows): Skip DEBUG_INSN.
testsuite/ChangeLog:
2019-10-10 Uroš Bizjak
PR target/92022
* g++.dg/pr92022.C: New test.
Bootstr
On Wed, Oct 16, 2019 at 5:06 PM H.J. Lu wrote:
>
> i386.h has
>
> #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
>
> It is impossible to have CLEAR_RATIO > 6. This patch adds clear_ratio
> to processor_costs, sets it to the minimum of 6 and move_ratio in all
> cost mod
> gcc/ChangeLog:
> * config/i386/driver-i386.c (host_detect_local_cpu): Handle
> icelake-client and icelake-server.
> * testsuite/gcc.target/i386/builtin_target.c (check_intel_cpu_model):
> Verify icelakes are detected correctly.
>
> libgcc/ChangeLog:
> *
On Sat, Oct 19, 2019 at 7:54 AM Jakub Jelinek wrote:
>
> Hi!
>
> As mentioned in the PR, x == 0 can be equivalently tested as x < 1U
> and the latter form has the advantage that it sets the carry flag and if it
> is consumed by an instruction that can directly use the carry flag, it is a
> win.
>
On Sun, Oct 20, 2019 at 1:24 PM Jakub Jelinek wrote:
>
> Hi!
>
> As mentioned in the PR, the x86 backend has various define_insn_and_split
> patterns that are meant to match usually during combine, are then
> unconditionally split during split1 pass and as they have &&
> can_create_pseudo_p ()
>
On Thu, Nov 14, 2019 at 9:36 AM Martin Liška wrote:
>
> On 11/13/19 5:14 PM, Uros Bizjak wrote:
> > On Wed, Nov 13, 2019 at 4:25 PM Martin Liška wrote:
> >>
> >> Hi.
> >>
> >> The patch adds a missing feature for PTA_ICELAKE_CLIENT and
&
On Tue, Nov 19, 2019 at 10:04 AM Jakub Jelinek wrote:
>
> Hi!
>
> xchg instruction is smaller, in some cases much smaller than 3 moves,
> (e.g. in the testcase 2 bytes vs. 8 bytes), and is not a performance
> disaster, but from Agner Fog tables and
> https://stackoverflow.com/questions/45766444/wh
On Wed, Nov 20, 2019 at 12:53 AM Jakub Jelinek wrote:
>
> Hi!
>
> The arch= handling in target attribute right now clears almost all isa_flags
> and all isa_flags2, so that later call to ix86_option_override_internal
> can set just the isa options for the specific arch and nothing else.
> Unfortun
On Fri, Nov 22, 2019 at 1:58 PM Bernd Schmidt wrote:
>
> A patch I posted recently fixes combine to take costs of JUMP_INSNs into
> account. That causes the pr30315 test to fail with -m32, since the cost
> of an add that sets the flags is estimated too high.
>
> The following seems to fix it. Boo
On Fri, Nov 22, 2019 at 5:39 PM Bernd Schmidt wrote:
>
> On 11/22/19 3:04 PM, Uros Bizjak wrote:
> > On Fri, Nov 22, 2019 at 1:58 PM Bernd Schmidt
> > wrote:
> >>
> >> A patch I posted recently fixes combine to take costs of JUMP_INSNs into
> >>
On Sat, Nov 23, 2019 at 2:09 AM Jakub Jelinek wrote:
>
> Hi!
>
> The following testcase ICEs, because ix86_md_asm_adjust emits an invalid
> insn that isn't matched. setcc_qi output is nonimmediate_operand and so is
> fine, but the problem is if we decide to do a ZERO_EXTEND, because
> zero_extend
On Sun, Dec 1, 2019 at 6:55 PM Jakub Jelinek wrote:
>
> On Sun, Dec 01, 2019 at 03:43:37PM +0100, Jan Hubicka wrote:
> > > PR target/92549
> > > * config/i386/i386.md (peephole2 for *swap): New peephole2.
> > >
> > > * gcc.target/i386/pr92549.c: New test.
> >
> > It is very hard to ge
On Mon, Dec 2, 2019 at 10:06 AM Jakub Jelinek wrote:
>
> On Mon, Dec 02, 2019 at 08:28:27AM +0100, Uros Bizjak wrote:
> > > I'll have a look tomorrow.
> >
> > general_reg_operand should be used in the pattern.
>
> That indeed works, ok for trunk if it pa
2018-08-01 Uros Bizjak
* gcc.dg/tree-ssa/pr84512.c: Xfail on alpha*-*-*.
Tested on alphaev68-linux-gnu, committed to mainline SVN.
Uros.
Index: gcc.dg/tree-ssa/pr84512.c
===
--- gcc.dg/tree-ssa/pr84512.c (revision 263193
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