On Sun, Oct 20, 2019 at 1:24 PM Jakub Jelinek <ja...@redhat.com> wrote:
>
> Hi!
>
> As mentioned in the PR, the x86 backend has various define_insn_and_split
> patterns that are meant to match usually during combine, are then
> unconditionally split during split1 pass and as they have &&
> can_create_pseudo_p ()
> in their define_insn condition, if they get matched after split1, nothing
> would split them anymore and they wouldn't match after reload.
>
> The split1 pass already sets a property that can be used.
>
> I've first tried to remove some constraints and associated attributes, but
> it seems from further discussions in the PR I don't know much about the
> reasons why they were added and if they are still needed or not, so this
> version of the patch just replaces the can_create_pseudo_p () conditions
> with a new predicate that stops matching already after the split1 pass.
As explained by Segher in the PR, there is no 100% guarantee that
combine won't produce a pattern with a wrong hard register as a e.g.
count reg of a shift insn. RA will die on this kind of pattern with
reload failure, so these constraints are used together with
ix86_legitimate_combined_insn target hook to reject invalid
combinations involving hard registers.
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
Assuming that used property is the correct way to go, OK.
Thanks,
Uros.
> 2019-10-20 Jakub Jelinek <ja...@redhat.com>
>
> * config/i386/i386-protos.h (ix86_pre_reload_split): Declare.
> * config/i386/i386.c (ix86_pre_reload_split): New function.
> * config/i386/i386.md (*fix_trunc<mode>_i387_1, *add<mode>3_eq,
> *add<mode>3_ne, *add<mode>3_eq_0, *add<mode>3_ne_0, *add<mode>3_eq,
> *add<mode>3_ne, *add<mode>3_eq_1, *add<mode>3_eq_0, *add<mode>3_ne_0,
> *anddi3_doubleword, *andndi3_doubleword, *<code>di3_doubleword,
> *one_cmpldi2_doubleword, *ashl<dwi>3_doubleword_mask,
> *ashl<dwi>3_doubleword_mask_1, *ashl<mode>3_mask, *ashl<mode>3_mask_1,
> *<shift_insn><mode>3_mask, *<shift_insn><mode>3_mask_1,
> *<shift_insn><dwi>3_doubleword_mask,
> *<shift_insn><dwi>3_doubleword_mask_1, *<rotate_insn><mode>3_mask,
> *<rotate_insn><mode>3_mask_1, *<btsc><mode>_mask,
> *<btsc><mode>_mask_1,
> *btr<mode>_mask, *btr<mode>_mask_1, *jcc_bt<mode>, *jcc_bt<mode>_1,
> *jcc_bt<mode>_mask, *popcounthi2_1, frndintxf2_<rounding>,
> *fist<mode>2_<rounding>_1, *<code><mode>3_1, *<code>di3_doubleword):
> Use ix86_pre_reload_split instead of can_create_pseudo_p in condition.
> * config/i386/sse.md (*sse4_1_<code>v8qiv8hi2<mask_name>_2,
> *avx2_<code>v8qiv8si2<mask_name>_2,
> *sse4_1_<code>v4qiv4si2<mask_name>_2,
> *sse4_1_<code>v4hiv4si2<mask_name>_2,
> *avx512f_<code>v8qiv8di2<mask_name>_2,
> *avx2_<code>v4qiv4di2<mask_name>_2,
> *avx2_<code>v4hiv4di2<mask_name>_2,
> *sse4_1_<code>v2hiv2di2<mask_name>_2,
> *sse4_1_<code>v2siv2di2<mask_name>_2, sse4_2_pcmpestr,
> sse4_2_pcmpistr): Likewise.
>
> --- gcc/config/i386/i386-protos.h.jj 2019-10-19 14:45:47.693185643 +0200
> +++ gcc/config/i386/i386-protos.h 2019-10-19 19:08:12.371359926 +0200
> @@ -55,6 +55,7 @@ extern rtx standard_80387_constant_rtx (
> extern int standard_sse_constant_p (rtx, machine_mode);
> extern const char *standard_sse_constant_opcode (rtx_insn *, rtx *);
> extern bool ix86_standard_x87sse_constant_load_p (const rtx_insn *, rtx);
> +extern bool ix86_pre_reload_split (void);
> extern bool symbolic_reference_mentioned_p (rtx);
> extern bool extended_reg_mentioned_p (rtx);
> extern bool x86_extended_QIreg_mentioned_p (rtx_insn *);
> --- gcc/config/i386/i386.c.jj 2019-10-19 14:45:47.729185094 +0200
> +++ gcc/config/i386/i386.c 2019-10-19 19:08:12.376359849 +0200
> @@ -4894,6 +4894,18 @@ ix86_standard_x87sse_constant_load_p (co
> return true;
> }
>
> +/* Predicate for pre-reload splitters with associated instructions,
> + which can match any time before the split1 pass (usually combine),
> + then are unconditionally split in that pass and should not be
> + matched again afterwards. */
> +
> +bool
> +ix86_pre_reload_split (void)
> +{
> + return (can_create_pseudo_p ()
> + && !(cfun->curr_properties & PROP_rtl_split_insns));
> +}
> +
> /* Returns true if OP contains a symbol reference */
>
> bool
> --- gcc/config/i386/i386.md.jj 2019-10-19 14:46:15.489760948 +0200
> +++ gcc/config/i386/i386.md 2019-10-19 19:08:12.381359773 +0200
> @@ -4920,7 +4920,7 @@ (define_insn_and_split "*fix_trunc<mode>
> && !TARGET_FISTTP
> && !(SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
> && (TARGET_64BIT || <MODE>mode != DImode))
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(const_int 0)]
> @@ -6857,7 +6857,7 @@ (define_insn_and_split "*add<mode>3_eq"
> (match_operand:SWI 2 "<general_operand>")))
> (clobber (reg:CC FLAGS_REG))]
> "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CC FLAGS_REG)
> @@ -6881,7 +6881,7 @@ (define_insn_and_split "*add<mode>3_ne"
> && (<MODE>mode != DImode
> || INTVAL (operands[2]) != HOST_WIDE_INT_C (-0x80000000))
> && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CC FLAGS_REG)
> @@ -6904,7 +6904,7 @@ (define_insn_and_split "*add<mode>3_eq_0
> (match_operand:SWI 1 "<general_operand>")))
> (clobber (reg:CC FLAGS_REG))]
> "ix86_unary_operator_ok (PLUS, <MODE>mode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CC FLAGS_REG)
> @@ -6925,7 +6925,7 @@ (define_insn_and_split "*add<mode>3_ne_0
> (match_operand:SWI 1 "<general_operand>")))
> (clobber (reg:CC FLAGS_REG))]
> "ix86_unary_operator_ok (PLUS, <MODE>mode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CC FLAGS_REG)
> @@ -6951,7 +6951,7 @@ (define_insn_and_split "*sub<mode>3_eq"
> (match_operand:SWI 2 "<general_operand>")))
> (clobber (reg:CC FLAGS_REG))]
> "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CC FLAGS_REG)
> @@ -6976,7 +6976,7 @@ (define_insn_and_split "*sub<mode>3_ne"
> && (<MODE>mode != DImode
> || INTVAL (operands[2]) != HOST_WIDE_INT_C (-0x80000000))
> && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CC FLAGS_REG)
> @@ -7005,7 +7005,7 @@ (define_insn_and_split "*sub<mode>3_eq_1
> && (<MODE>mode != DImode
> || INTVAL (operands[2]) != HOST_WIDE_INT_C (-0x80000000))
> && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CC FLAGS_REG)
> @@ -7028,7 +7028,7 @@ (define_insn_and_split "*sub<mode>3_eq_0
> (eq:SWI (match_operand 2 "int_nonimmediate_operand") (const_int
> 0))))
> (clobber (reg:CC FLAGS_REG))]
> "ix86_unary_operator_ok (MINUS, <MODE>mode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CC FLAGS_REG)
> @@ -7049,7 +7049,7 @@ (define_insn_and_split "*sub<mode>3_ne_0
> (ne:SWI (match_operand 2 "int_nonimmediate_operand") (const_int
> 0))))
> (clobber (reg:CC FLAGS_REG))]
> "ix86_unary_operator_ok (MINUS, <MODE>mode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CC FLAGS_REG)
> @@ -8621,7 +8621,7 @@ (define_insn_and_split "*anddi3_doublewo
> (clobber (reg:CC FLAGS_REG))]
> "!TARGET_64BIT && TARGET_STV && TARGET_SSE2
> && ix86_binary_operator_ok (AND, DImode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(const_int 0)]
> @@ -9076,7 +9076,7 @@ (define_insn "*andndi3_doubleword"
> (match_operand:DI 2 "nonimmediate_operand")))
> (clobber (reg:CC FLAGS_REG))]
> "!TARGET_64BIT && TARGET_STV && TARGET_SSE2
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#")
>
> (define_split
> @@ -9176,7 +9176,7 @@ (define_insn_and_split "*<code>di3_doubl
> (clobber (reg:CC FLAGS_REG))]
> "!TARGET_64BIT && TARGET_STV && TARGET_SSE2
> && ix86_binary_operator_ok (<CODE>, DImode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(const_int 0)]
> @@ -9898,7 +9898,7 @@ (define_insn_and_split "*one_cmpldi2_dou
> (not:DI (match_operand:DI 1 "nonimmediate_operand")))]
> "!TARGET_64BIT && TARGET_STV && TARGET_SSE2
> && ix86_unary_operator_ok (NOT, DImode, operands)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -10032,7 +10032,7 @@ (define_insn_and_split "*ashl<dwi>3_doub
> (match_operand:SI 3 "const_int_operand")) 0)))
> (clobber (reg:CC FLAGS_REG))]
> "(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT)) == 0
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -10073,7 +10073,7 @@ (define_insn_and_split "*ashl<dwi>3_doub
> (match_operand:QI 3 "const_int_operand"))))
> (clobber (reg:CC FLAGS_REG))]
> "(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT)) == 0
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -10228,7 +10228,7 @@ (define_insn_and_split "*ashl<mode>3_mas
> "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -10250,7 +10250,7 @@ (define_insn_and_split "*ashl<mode>3_mas
> "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -10748,7 +10748,7 @@ (define_insn_and_split "*<shift_insn><mo
> "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -10770,7 +10770,7 @@ (define_insn_and_split "*<shift_insn><mo
> "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -10791,7 +10791,7 @@ (define_insn_and_split "*<shift_insn><dw
> (match_operand:SI 3 "const_int_operand")) 0)))
> (clobber (reg:CC FLAGS_REG))]
> "(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT)) == 0
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -10832,7 +10832,7 @@ (define_insn_and_split "*<shift_insn><dw
> (match_operand:QI 3 "const_int_operand"))))
> (clobber (reg:CC FLAGS_REG))]
> "(INTVAL (operands[3]) & (<MODE_SIZE> * BITS_PER_UNIT)) == 0
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -11298,7 +11298,7 @@ (define_insn_and_split "*<rotate_insn><m
> "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -11319,7 +11319,7 @@ (define_insn_and_split "*<rotate_insn><m
> "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -11622,7 +11622,7 @@ (define_insn_and_split "*<btsc><mode>_ma
> "TARGET_USE_BT
> && (INTVAL (operands[2]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -11647,7 +11647,7 @@ (define_insn_and_split "*<btsc><mode>_ma
> "TARGET_USE_BT
> && (INTVAL (operands[2]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -11687,7 +11687,7 @@ (define_insn_and_split "*btr<mode>_mask"
> "TARGET_USE_BT
> && (INTVAL (operands[2]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -11712,7 +11712,7 @@ (define_insn_and_split "*btr<mode>_mask_
> "TARGET_USE_BT
> && (INTVAL (operands[2]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(parallel
> @@ -11897,7 +11897,7 @@ (define_insn_and_split "*jcc_bt<mode>"
> && INTVAL (operands[2])
> >= (optimize_function_for_size_p (cfun) ? 8 : 32))
> : !memory_operand (operands[1], <MODE>mode))
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CCC FLAGS_REG)
> @@ -11929,7 +11929,7 @@ (define_insn_and_split "*jcc_bt<mode>_1"
> (pc)))
> (clobber (reg:CC FLAGS_REG))]
> "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CCC FLAGS_REG)
> @@ -11965,7 +11965,7 @@ (define_insn_and_split "*jcc_bt<mode>_ma
> "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
> && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (reg:CCC FLAGS_REG)
> @@ -14058,7 +14058,7 @@ (define_insn_and_split "*popcounthi2_1"
> (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand"))))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_POPCNT
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(const_int 0)]
> @@ -16479,7 +16479,7 @@ (define_insn_and_split "frndintxf2_<roun
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_USE_FANCY_MATH_387
> && (flag_fp_int_builtin_inexact || !flag_trapping_math)
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(const_int 0)]
> @@ -16582,7 +16582,7 @@ (define_insn_and_split "*fist<mode>2_<ro
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_USE_FANCY_MATH_387
> && flag_unsafe_math_optimizations
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(const_int 0)]
> @@ -17973,7 +17973,7 @@ (define_insn_and_split "*<code><mode>3_1
> (match_operand:MAXMIN_IMODE 2 "nonimmediate_operand")))
> (clobber (reg:CC FLAGS_REG))]
> "(TARGET_64BIT || <MODE>mode != DImode) && TARGET_STV
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -18002,7 +18002,7 @@ (define_insn_and_split "*<code>di3_doubl
> (match_operand:DI 2 "nonimmediate_operand")))
> (clobber (reg:CC FLAGS_REG))]
> "!TARGET_64BIT && TARGET_STV && TARGET_AVX512VL
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> --- gcc/config/i386/sse.md.jj 2019-10-19 14:45:47.634186545 +0200
> +++ gcc/config/i386/sse.md 2019-10-19 19:08:12.383359743 +0200
> @@ -17363,7 +17363,7 @@ (define_insn_and_split "*sse4_1_<code>v8
> (const_int 4) (const_int 5)
> (const_int 6) (const_int 7)]))))]
> "TARGET_SSE4_1 && <mask_avx512bw_condition> && <mask_avx512vl_condition>
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -17420,7 +17420,7 @@ (define_insn_and_split "*avx2_<code>v8qi
> (const_int 4) (const_int 5)
> (const_int 6) (const_int 7)]))))]
> "TARGET_AVX2 && <mask_avx512vl_condition>
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -17469,7 +17469,7 @@ (define_insn_and_split "*sse4_1_<code>v4
> (parallel [(const_int 0) (const_int 1)
> (const_int 2) (const_int 3)]))))]
> "TARGET_SSE4_1 && <mask_avx512vl_condition>
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -17535,7 +17535,7 @@ (define_insn_and_split "*sse4_1_<code>v4
> (parallel [(const_int 0) (const_int 1)
> (const_int 2) (const_int 3)]))))]
> "TARGET_SSE4_1 && <mask_avx512vl_condition>
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -17579,7 +17579,7 @@ (define_insn_and_split "*avx512f_<code>v
> (const_int 2) (const_int 3)
> (const_int 4) (const_int 5)
> (const_int 6) (const_int 7)]))))]
> - "TARGET_AVX512F && can_create_pseudo_p ()"
> + "TARGET_AVX512F && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -17626,7 +17626,7 @@ (define_insn_and_split "*avx2_<code>v4qi
> (parallel [(const_int 0) (const_int 1)
> (const_int 2) (const_int 3)]))))]
> "TARGET_AVX2 && <mask_avx512vl_condition>
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -17693,7 +17693,7 @@ (define_insn_and_split "*avx2_<code>v4hi
> (parallel [(const_int 0) (const_int 1)
> (const_int 2) (const_int 3)]))))]
> "TARGET_AVX2 && <mask_avx512vl_condition>
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -17740,7 +17740,7 @@ (define_insn_and_split "*sse4_1_<code>v2
> (const_int 1)) 0)
> (parallel [(const_int 0) (const_int 1)]))))]
> "TARGET_SSE4_1 && <mask_avx512vl_condition>
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -17804,7 +17804,7 @@ (define_insn_and_split "*sse4_1_<code>v2
> (const_int 0)) 0)
> (parallel [(const_int 0) (const_int 1)]))))]
> "TARGET_SSE4_1 && <mask_avx512vl_condition>
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(set (match_dup 0)
> @@ -18087,7 +18087,7 @@ (define_insn_and_split "sse4_2_pcmpestr"
> (match_dup 6)]
> UNSPEC_PCMPESTR))]
> "TARGET_SSE4_2
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(const_int 0)]
> @@ -18223,7 +18223,7 @@ (define_insn_and_split "sse4_2_pcmpistr"
> (match_dup 4)]
> UNSPEC_PCMPISTR))]
> "TARGET_SSE4_2
> - && can_create_pseudo_p ()"
> + && ix86_pre_reload_split ()"
> "#"
> "&& 1"
> [(const_int 0)]
>
> Jakub
>
