On Fri, Sep 29, 2023 at 02:09:12PM -0400, Michael Meissner wrote:
> * config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete.
> (copysign3_fcpsg): Use copysign RTL instead of UNSPEC.
(typo, it is _fcpsgn)
Nice to see unnecessary unspecs going away :-)
Segher
Hi Jakub,
On Fri, Jun 29, 2018 at 12:52:59AM +0200, Jakub Jelinek wrote:
> The newly added rs6000-modes.h is now included from rs6000.h, so it is
> needed when building plugins that include tm.h, but it wasn't listed in the
> Makefile fragments and therefore included among PLUGIN_HEADERS.
>
> Fix
Hi!
On Fri, Jun 29, 2018 at 07:38:39AM -0700, Carl Love wrote:
> +;; Unpack high elements of float vector to vector of doubles
> +(define_expand "altivec_unpackh_v4sf"
> + [(set (match_operand:V2DF 0 "register_operand" "=v")
> +(match_operand:V4SF 1 "register_operand" "v"))]
> + "TARGET_
tting to trunk. This should also go to 8.
Segher
2018-06-26 Segher Boessenkool
PR target/86285
* config/rs6000/rs6000.c (rs6000_init_builtins): Do not set
ieee128_float_type_node to long_double_type_node unless
TARGET_LONG_DOUBLE_128 is set.
---
gcc/c
On Tue, Jul 03, 2018 at 10:53:20AM +0200, Martin Liška wrote:
> On 06/29/2018 09:04 PM, Jeff Law wrote:
> > I think this is fine for the trunk.
> >
> > jeff
>
> Thank you Jeff.
>
> I found some issues when doing build of all targets (contrib/config-list.mk).
> I'll update patch and test that aff
On Tue, Jul 03, 2018 at 12:15:48PM +0200, Martin Liška wrote:
> > toplev.c already has (in init_alignments):
> >
> > if (align_jumps_max_skip > align_jumps)
> > align_jumps_max_skip = align_jumps - 1;
>
> I'm rewriting this logic in the patch set. Issue is that
> checking for value of alig
The target has been removed, so we shouldn't try to build it.
Segher
2018-07-03 Segher Boessenkool
* contrib/config-list.mk: Remove powerpc-linux_paired.
---
contrib/config-list.mk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/config-list
On Tue, Jul 03, 2018 at 02:51:27PM +0200, Martin Liška wrote:
> On 07/03/2018 12:58 PM, Segher Boessenkool wrote:
> > On Tue, Jul 03, 2018 at 12:15:48PM +0200, Martin Liška wrote:
> >>> toplev.c already has (in init_alignments):
> >>>
> >>
Hi Carl,
On Tue, Jul 03, 2018 at 02:36:22PM -0700, Carl Love wrote:
> Please let me know if the patch looks OK for GCC mainline. The patch
> also needs to be backported to GCC 8.
Looks great, thanks! Okay for trunk, and also for 8.
Segher
> 2018-07-03 Carl Love
>
> * config/rs6000/
On Fri, Jul 06, 2018 at 01:51:37AM -0400, Michael Meissner wrote:
> case "$target:$with_long_double_format" in
> - xpowerpc64*-*-linux*:*)
So this case could never happen. The changelog should mention it fixes
that bug (and having it as a separate patch is much preferred!)
Other than this thi
On Fri, Jul 06, 2018 at 09:38:02AM -0400, Michael Meissner wrote:
> On Fri, Jul 06, 2018 at 06:38:55AM -0500, Segher Boessenkool wrote:
> > On Fri, Jul 06, 2018 at 01:51:37AM -0400, Michael Meissner wrote:
> > > case "$target:$with_long_double_format" in
>
On Fri, Jul 06, 2018 at 09:46:36AM -0400, Michael Meissner wrote:
> On Fri, Jul 06, 2018 at 10:16:34AM -0300, Tulio Magno Quites Machado Filho
> wrote:
> > I suggest to test with the following program:
> >
> > #include
> >
> > int
> > main ()
> > {
> > return !isinfl(__builtin_infl());
> > }
On Mon, Jul 09, 2018 at 04:50:03PM -0700, Carl Love wrote:
> The following patch is a back port for a commit to mainline prior to
> GCC 8 release. Note, the code fixed by this patch was later modified
> in commit 256798 as part of adding vec_xst_len support. The sldi
> instruction gets replaced b
Hi!
On Mon, Jul 09, 2018 at 02:08:37PM -0500, Will Schmidt wrote:
> * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin):
> Add support for gimple-folding of vec_pack() and vec_unpack()
> intrinsics.
> +case ALTIVEC_BUILTIN_VUPKHPX:
> +case ALTIVEC_BUILTIN_VUPKLPX:
> +
Hi Will,
On Mon, Jul 09, 2018 at 02:08:49PM -0500, Will Schmidt wrote:
> * gcc.target/powerpc/fold-vec-unpack-char.c: New.
> * gcc.target/powerpc/fold-vec-unpack-float.c: New.
> * gcc.target/powerpc/fold-vec-unpack-int.c: New.
> * gcc.target/powerpc/fold-vec-unpack-pixel.c
On Mon, Jul 09, 2018 at 02:08:55PM -0500, Will Schmidt wrote:
>Add support for early gimple folding of vec_perm. Testcases are already
> in-tree as
> gcc.target/powerpc/fold-vec-perm-*.c
>
> OK for trunk?
Looks fine to me. Okay if no one else complains :-)
Segher
> * gcc/config/
Hi!
On Tue, Jul 10, 2018 at 12:10:51PM -0500, Will Schmidt wrote:
> Add support for Gimple folding for unaligned vector loads and stores.
This is fine if the experts agree. Thanks! And thanks to the reviewers,
too.
One detail:
> * config/rs6000/rs6000.c (rs6000_builtin_valid_without_lhs
Hi!
On Wed, Jul 11, 2018 at 12:26:24PM -0500, Bill Schmidt wrote:
> It was recently brought to our attention that the existing emmintrin.h
> header, which was believed to be feature-complete for SSE2 support, is
> actually missing four logical-op interfaces:
>
> _mm_and_si128
> _mm_andnot_si128
On Tue, Jul 10, 2018 at 06:13:50PM -0500, Kelvin Nilsen wrote:
> This patch alphabetizes the list of AltiVec built-in function prototypes that
> consume about 15 pages of the gcc.pdf file. As part of the alphabetization
> effort, certain functions that should not be documented in this section of
On Fri, Jul 13, 2018 at 10:51:24AM -0400, David Edelsohn wrote:
> On AIX it would be calling divtc3, but AIX defaults to 64 bit long
> double. Either all of these tests need
>
> /* { dg-require-effective-target longdouble128 } */
>
> or
>
> /* { dg-additional-options "-mlong-double-128" { targe
On Fri, Jul 13, 2018 at 04:15:26PM -0700, Carl Love wrote:
> Segher, David:
>
> I reworked the patch per the first option that David gave. The tests
> divkc3-2.c, divkc3-3.c, mulkc3-2.c and mulkc3-3.c pass on Power 9 Linux
> as they did before. The tests are unsupported on Power8 Linux as they
>
before power7 because that is not
supported).
Committing to trunk.
Segher
Segher Boessenkool (6):
rs6000: Use more correct names for some trunc/extend libcalls
rs6000: Use correct names for some trunc/extend libcalls
rs6000: Improve truncifsf2
rs6000: Fix testsuite bug in
The test program for ppc_float128_hw_available would always return
false, since there is a syntax error in that test program.
2018-07-16 Segher Boessenkool
gcc/testsuite/
* lib/target-supports.exp (check_ppc_float128_hw_available): Fix
syntax error.
---
gcc/testsuite/lib
The libcalls for trunc and extend of a decimal float to a binary float,
and vice versa, do not have "2" in the name, although all other such
conversions do.
2018-07-16 Segher Boessenkool
* config/rs6000/rs6000.c (init_float128_ibm): Use the correct names
for c
The current implementation leaves an unnecessary register move. It is
easier to just expand things in the expander already. This patch does
that.
2018-07-16 Segher Boessenkool
* config/rs6000/rs6000.md (truncsf2): Expand truncates of
double-double modes to SFmode directly
This introduces four new selectors for use with Power testcases:
longdouble64, ppc_float128, ppc_float128_insns, powerpc_vsx.
2018-07-16 Segher Boessenkool
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_longdouble64,
check_effective_target_ppc_float128
They had source and destination swapped in the name.
2018-07-16 Segher Boessenkool
* config/rs6000/rs6000.c (init_float128_ibm): Use more correct names
for the conversions between TDmode and IFmode.
(init_float128_ieee): Use more correct names for the conversions
This tests the generated code for all conversions between floating point
point types, binary and decimal.
2018-07-16 Segher Boessenkool
gcc/testsuite/
* gcc.target/powerpc/convert-fp-128.c: New testcase.
* gcc.target/powerpc/convert-fp-64.c: New testcase.
---
gcc/testsuite
On Tue, Jul 17, 2018 at 01:34:18PM -0400, David Edelsohn wrote:
> And another test that needs to be restricted because it assumes 128
> bit long double.
Thanks :-)
Segher
On Tue, Jul 17, 2018 at 03:44:43PM -0500, Kelvin Nilsen wrote:
> The many PowerPC built-in functions (intrinsics) that are enabled by
> including each have different configuration requirements. To
> simplify the description of the requirements, this patch sorts these
> functions into different
Hi Carl,
On Tue, Jul 17, 2018 at 04:39:58PM -0700, Carl Love wrote:
> I was requested to backport the patch for the AIX test case failures to
> GCC 8. The trunk patch applied cleanly to GCC 8. I updated the
> changelog patch, built and retested the patch on:
>
> powerpc64le-unknown-linux-gn
Hi Mike,
On Fri, Jul 13, 2018 at 04:56:13PM -0400, Michael Meissner wrote:
> This means rather than keeping the toc fusion around (that nobody used), I
> would prefer to delete the current code, and replace it with better code as I
> implement it.
> +++ gcc/config/rs6000/constraints.md (working
Hi Carl,
On Fri, Jul 20, 2018 at 12:42:33PM -0700, Carl Love wrote:
> The following patch fixes errors on AIX for the "vector double" tests
> in altivec-1-runnable.c file. The type "vector double" requires the
> use of the GCC command line option -mvsx. The vector double tests
> in altivec-1-runn
pieces.
This patch adds a splitter to make combine handle this case.
Tested on powerpc64-linux {-m32,-m64} and on powerpc64le-linux; committing.
Segher
2018-07-23 Segher Boessenkool
* config/rs6000/rs6000.md (splitters for rldimi and rlwimi with the
zero_extend argument
This changes vsx_init_v4si to be an expander. That way, no special
cases are needed anymore for special arguments: the normal RTL passes
can deal with it.
Tested as usual; committing.
Segher
2018-07-23 Segher Boessenkool
* config/rs6000/rs6000-p8swap.c (rtx_is_swappable_p
lting insns to be a
move instruction. But that is actually a very good thing to have, as
should have been obvious).
Tested for many months; tested on about 30 targets.
I'll commit this later this week if there are no objections.
Segher
2018-07-24 Segher Boessenkool
PR rtl-op
On Mon, Jul 23, 2018 at 10:26:35PM -0600, Sandra Loosemore wrote:
> diff --git a/libgcc/config.host b/libgcc/config.host
> index 18cabaf..b2ee0c9 100644
> --- a/libgcc/config.host
> +++ b/libgcc/config.host
> @@ -94,6 +94,9 @@ am33_2.0-*-linux*)
> arc*-*-*)
> cpu_type=arc
> ;;
> +csky*
On Tue, Jul 24, 2018 at 12:19:30PM -0600, Sandra Loosemore wrote:
> On 07/24/2018 12:10 PM, Segher Boessenkool wrote:
> >On Mon, Jul 23, 2018 at 10:26:35PM -0600, Sandra Loosemore wrote:
> >>diff --git a/libgcc/config.host b/libgcc/config.host
> >>index 18cabaf..b2ee
On Wed, Jul 25, 2018 at 10:28:30AM +0200, Richard Biener wrote:
> On Tue, Jul 24, 2018 at 7:18 PM Segher Boessenkool
> wrote:
> >
> > This patch allows combine to combine two insns into two. This helps
> > in many cases, by reducing instruction path length, and a
On Wed, Jul 25, 2018 at 09:47:31AM -0400, David Malcolm wrote:
> > +/* Return whether X is just a single set, with the source
> > + a general_operand. */
> > +static bool
> > +is_just_move (rtx x)
> > +{
> > + if (INSN_P (x))
> > +x = PATTERN (x);
> > +
> > + return (GET_CODE (x) == SET &&
value written to the DImode is not the same as that
written to the lowest-numbered QImode!
This patch fixes it. Committing. Will backport later, too.
Segher
2018-07-26 Segher Boessenkool
PR rtl-optimization/85805
* combine.c (reg_nonzero_bits_for_combine): Only use the last
On Thu, Jul 26, 2018 at 01:16:42PM +0200, Richard Biener wrote:
> On Thu, Jul 26, 2018 at 12:12 PM Segher Boessenkool
> wrote:
> >
> > The current code in reg_nonzero_bits_for_combine allows using the
> > reg_stat info when last_set_mode is a different integer mode. This
On Thu, Jul 26, 2018 at 08:40:01AM -0500, Kelvin Nilsen wrote:
> To improve internal consistency and to improve consistency with published ABI
> documents, this patch replaces the __uint128_t type with __uint128 and
> replaces __int128_t with __int128.
> Is this ok for trunk?
Looks good, thanks
On Thu, Jul 26, 2018 at 02:53:09PM -0500, Pat Haugen wrote:
> Probably an obvious patch but...
>
> The testcase fails because it looks like recent glibc headers (2.27 at least)
> no longer contain a declaration for __strdup, which results in warning
> messages being generated and failure for exc
In arm_block_set_aligned_vect 8-bit constants are generated as zero-
extended const_ints, not sign-extended as required. Fix that.
Tamar tested the patch (see PR); no problems were found. Is this okay
for trunk?
Segher
2018-07-30 Segher Boessenkool
PR target/86640
Committing.
Segher
2018-07-30 Segher Boessenkool
gcc/testsuite/
PR rtl-optimization/85160
* gcc.target/powerpc/combine-2-2.c: New testcase.
---
gcc/testsuite/gcc.target/powerpc/combine-2-2.c | 17 +
1 file changed, 17 insertions(+)
create mode 100644 gcc
On Tue, Jul 24, 2018 at 05:18:41PM +, Segher Boessenkool wrote:
> This patch allows combine to combine two insns into two. This helps
> in many cases, by reducing instruction path length, and also allowing
> further combinations to happen. PR85160 is a typical example of code
>
On Mon, Jul 30, 2018 at 03:55:30PM +0100, Kyrill Tkachov wrote:
> Hi Segher,
>
> On 30/07/18 14:14, Segher Boessenkool wrote:
> >In arm_block_set_aligned_vect 8-bit constants are generated as zero-
> >extended const_ints, not sign-extended as required. Fix that.
> >
On Fri, Jul 27, 2018 at 10:07:20AM -0500, Kelvin Nilsen wrote:
> On 7/26/18 9:54 AM, Segher Boessenkool wrote:
> > On Thu, Jul 26, 2018 at 08:40:01AM -0500, Kelvin Nilsen wrote:
> >> To improve internal consistency and to improve consistency with published
> >> ABI doc
On Tue, Jul 31, 2018 at 09:02:56AM +0100, Kyrill Tkachov wrote:
> Hi Segher,
>
> On 30/07/18 18:37, Segher Boessenkool wrote:
> >On Mon, Jul 30, 2018 at 03:55:30PM +0100, Kyrill Tkachov wrote:
> >>Hi Segher,
> >>
> >>On 30/07/18 14:14, Segher Boessenkool
Hi Kyrill,
As before, untested. Is this okay for trunk, or will you handle it
yourself (or will someone else do it?)
Segher
2018-07-31 Segher Boessenkool
gcc/testsuite/
PR target/86640
* gcc.target/arm/pr86640.c: New testcase.
---
gcc/testsuite/gcc.target/arm/pr86640.c
Hi Christophe,
On Tue, Jul 31, 2018 at 02:34:06PM +0200, Christophe Lyon wrote:
> Since this was committed, I've noticed regressions
> on aarch64:
> FAIL: gcc.dg/zero_bits_compound-1.c scan-assembler-not \\(and:
This went from
and w0, w0, 255
lsl w1, w0, 8
orr
On Tue, Jul 31, 2018 at 05:39:37AM -0700, H.J. Lu wrote:
> For
>
> ---
> #define N 16
> float f[N];
> double d[N];
> int n[N];
>
> __attribute__((noinline)) void
> f3 (void)
> {
> int i;
> for (i = 0; i < N; i++)
> d[i] = f[i];
> }
> ---
>
> r263067 improved -O3 -mavx2 -mtune=generic -m6
On Tue, Jul 31, 2018 at 05:01:02PM -0500, Bill Schmidt wrote:
> > On Jul 27, 2018, at 4:37 AM, Richard Earnshaw
> > wrote:
> > This patch reworks the existing rs6000_speculation_barrier pattern to
> > work with the new __builtin_sepculation_safe_value() intrinsic. The
> > change is trivial as it
On Wed, Aug 01, 2018 at 10:27:31AM +0200, Christophe Lyon wrote:
> On Tue, 31 Jul 2018 at 15:57, Segher Boessenkool
> wrote:
> > On Tue, Jul 31, 2018 at 02:34:06PM +0200, Christophe Lyon wrote:
> > > Since this was committed, I've noticed regressions
> >
Hi Mike,
On Wed, May 10, 2023 at 11:38:55AM -0400, Michael Meissner wrote:
> This patch rewrites the gen_ld_cmpi_p10 function in genfusion.pl to be
> clearer.
That is not at all what I asked for, even if I would agree the code is
nicer to read now (I don't).
What I asked for, what is needed, is
On Wed, May 10, 2023 at 11:40:00AM -0400, Michael Meissner wrote:
> This patch applies stricter predicates and constraints for LD and LWA
> instructions with power10 fusion. These instructions are DS-form
> instructions,
> which means that the bottom 2 bits of the address must be 0.
The low two
Hi!
On Mon, Jun 05, 2023 at 12:11:42PM +0530, P Jeevitha wrote:
> PR106907 has few warnings spotted from cppcheck. In that addressing duplicate
> expression issue here. Here the same expression is used twice in logical
> AND(&&) operation which result in same result so removing that.
>
> 2023-06-
ot;s or "qw" for lists of constants.
2023-06-06 Segher Boessenkool
* config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): New, rewritten and
split out from...
(gen_ld_cmpi_p10): ... this.
---
gcc/config/rs6000/genfusion.pl | 185 +++
2023-06-06 Segher Boessenkool
* config/rs6000/genfusion.pl: Delete some dead code.
---
gcc/config/rs6000/genfusion.pl | 3 ---
1 file changed, 3 deletions(-)
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 2851bb7..82e8f86 100755
--- a/gcc/config
Hi!
On Wed, Jun 07, 2023 at 04:21:11PM +0800, Jiufu Guo wrote:
> This patch tries to optimize "(X - N * M) / N" to "X / N - M".
> For C code, "/" towards zero (trunc_div), and "X - N * M" maybe
> wrap/overflow/underflow. So, it is valid that "X - N * M" does
> not cross zero and does not wrap/over
Hi!
On Sat, Feb 25, 2023 at 03:20:33PM +0530, Ajit Agarwal wrote:
> Here is the patch that uses xxlor instead of fmr where possible.
> Performance results shows that fmr is better in power9 and
> power10 architectures whereas xxlor is better in power7 and
> power 8 architectures. fmr is the only
Hi!
On Tue, Jun 13, 2023 at 10:15:49AM +0800, Jiufu Guo wrote:
> David Edelsohn writes:
> >
> > This definitely seems to be a better solution.
> >
> > The TARGET_CONST_ANCHOR change should not be part of this patch. Also
> > there is no ChangeLog for the patch.
>
> Thanks a lot for your quick r
Hi!
As I said in a reply to the original patch: not okay. Sorry.
But some comments on this patch:
On Tue, Jun 13, 2023 at 08:23:35PM +0800, Jiufu Guo wrote:
> + && XINT (SET_SRC (set), 1) == UNSPEC_TIE
> + && XVECEXP (SET_SRC (set), 0, 0) == const0_rtx);
This makes it required that
Hi!
On Wed, Jun 14, 2023 at 05:18:15PM +0800, Xi Ruoyao wrote:
> The generic issue here is to fix (not "papering over") the signed
> overflow, we need to perform the addition in a target machine mode. We
> may always use Pmode (IIRC const_anchor was introduced for optimizing
> some constant addre
Hi!
On Wed, Jun 14, 2023 at 12:06:29PM +0800, Jiufu Guo wrote:
> Segher Boessenkool writes:
> I'm also thinking about other solutions:
> 1. "set (mem/c:BLK (reg/f:DI 1 1) (const_int 0 [0])"
> This is the existing pattern. It may be read as an action
> to clea
Hi!
On Wed, Jun 14, 2023 at 07:59:04AM +, Richard Biener wrote:
> On Wed, 14 Jun 2023, Jiufu Guo wrote:
> > 3. "set (mem/c:DI (reg/f:DI 1 1) unspec:DI (const_int 0 [0])
> > UNSPEC_TIE".
> >This avoids using BLK on unspec, but using DI.
>
> That gives the MEM a size which means we can inte
Hi!
On Wed, Jun 14, 2023 at 05:26:52PM +0800, Jiufu Guo wrote:
> Richard Biener writes:
> >> 3. "set (mem/c:DI (reg/f:DI 1 1) unspec:DI (const_int 0 [0])
> >> UNSPEC_TIE".
> >>This avoids using BLK on unspec, but using DI.
> >
> > That gives the MEM a size which means we can interpret the (se
Hi!
On Wed, Jun 14, 2023 at 09:52:37AM +, Richard Biener wrote:
> I see. So
>
> (parallel
> (unspec stack_tie)
> (clobber (mem:BLK ...)))
Written like this, without a "set", *every* unspec has to be an
unspec_volatile, for the same reason as all inline asms without outputs
always are cons
On Wed, Jun 14, 2023 at 09:22:09AM +, Richard Biener wrote:
> How can a clobber be validly dropped?
Same as any other set: if no code executed after it can read whatever is
written. This typically means a stack frame goes away, or simply no
more code is executed *at all* after this.
> For th
Hi!
On Wed, Jun 14, 2023 at 10:04:20AM +0100, Richard Sandiford wrote:
> I'd also understood it to be either. As in, it is a may-clobber
> that can be used for must-clobber. Alternatively: the value stored
> is unpredictable, and can therefore be the same as the current value.
Yes, it is a set
On Wed, Jun 14, 2023 at 06:25:10PM +0200, Richard Biener wrote:
> > Form rs6000.md:
> > ; This is to explain that changes to the stack pointer should
> > ; not be moved over loads from or stores to stack memory.
> > (define_insn "stack_tie"
>
> That suggests it’s the hard register value that‘s pro
On Thu, Jun 15, 2023 at 03:00:40PM +0800, Jiufu Guo wrote:
> >> This is the existing pattern. It may be read as an action
> >> to clean an unknown-size memory block.
> >
> > Including a size zero memory block, yes. BLKmode was originally to do
> > things like bcopy (before modern names like m
On Wed, Jul 06, 2022 at 07:15:08PM +0100, Jonathan Wakely wrote:
> Tested powerpc64-linux, OK for trunk?
Okay, thanks!
> -! { dg-options "-mdejagnu-cpu=405 -mpower9-minmax -mfloat128-type" }
> +! { dg-options "-mdejagnu-cpu=405 -mpower9-minmax -mfloat128" }
We really shouldn't have -mpower9-minm
Hi!
On Thu, Jul 07, 2022 at 04:30:50PM +0800, HAO CHEN GUI wrote:
> This patch modifies the combine pattern after recog fails. With a helper
It modifies combine itself, not just a pattern in the machine
description.
> - change_pseudo_and_mask, it converts a single pseudo to the pseudo AND with
Hi!
On Thu, Jul 07, 2022 at 10:08:04PM +0100, Roger Sayle wrote:
> I think it's fair to describe RTL's representation of condition flags
> using MODE_CC as a little counter-intuitive.
"A little challenging", and you should see that as a good thing, as a
puzzle to crack :-)
> For example, the i38
Hi!
On Thu, Jul 07, 2022 at 08:40:38PM +0100, Roger Sayle wrote:
> Although I've not been able to reproduce your ICE (using gcc135
> on the compile farm), I completely agree with Segher's analysis
> that the Achilles heel with my approach/patch is that there's
> currently no way for the backend/re
Hi!
On Fri, Jul 08, 2022 at 08:14:58AM +0100, Roger Sayle wrote:
> This patch adds support for x86's single-byte encoded stc (set carry flag)
> and clc (clear carry flag) instructions to i386.md.
Maybe add a test for clc as well? Because:
> +(define_insn "x86_clc"
> + [(set (reg:CCC FLAGS_REG)
Hi!
On Mon, Jul 11, 2022 at 10:13:41AM +0800, HAO CHEN GUI wrote:
> I did a biset for the problem. After commit "commit 8d2d39587: combine: Do
> not combine
> moves from hard registers", the case fails. The root cause is it can't
> combine from the
> hard registers and has to use subreg which ca
Hi!
On Mon, Jul 04, 2022 at 02:27:42PM +0800, HAO CHEN GUI wrote:
> This patch fails TImode for all 128-bit logical operation expanders. So
> TImode splits to two DI registers during expand. Potential optimizations can
> be taken after expand pass. Originally, the TImode logical operations are
>
Hi!
On Wed, Jul 13, 2022 at 01:18:29PM -0500, will schmidt wrote:
> This cleans up some of the naming around the vstrir and vstril
> instruction definitions, with some cosmetic changes for consistency.
> gcc/
> * config/rs6000/altivec.md (vstrir_code_): Rename
> to vstrir_internal_.
On Wed, Jul 13, 2022 at 04:14:11PM -0500, will schmidt wrote:
> On Wed, 2022-07-13 at 14:39 -0500, Segher Boessenkool wrote:
> > I'm not a fan of "internal" either, it doesn't say anything. At
> > least
> > put it at the very end of the names please?
&
On Thu, Jul 14, 2022 at 11:20:56AM -0400, Michael Meissner wrote:
> I have applied the patch to GCC 12.
>
> | From 22736f3d0d4fb8ce4afb3230023f8accdb03a623 Mon Sep 17 00:00:00 2001
> | From: Michael Meissner
> | Date: Thu, 14 Jul 2022 11:16:08 -0400
> | Subject: [PATCH] [BACKPORT] Disable generat
On Thu, Jul 14, 2022 at 05:49:57PM -0400, Michael Meissner wrote:
> On Thu, Jul 14, 2022 at 04:12:14PM -0500, Segher Boessenkool wrote:
> > You never posted the trunk version of this, so that never was approved
> > either.
>
> I did post the trunk version on June 10th, and
On Tue, Jul 19, 2022 at 03:14:52PM -0500, will schmidt wrote:
> This cleans up some of the naming around the vstrir and vstril
> instruction definitions, with some cosmetic changes for consistency.
Okay for trunk. Thanks!
Segher
Hi!
On Wed, Jul 20, 2022 at 05:31:11PM +0800, Kewen.Lin wrote:
> As PR106345 shows, some test cases should be updated with
> -mdejagnu-tune, since their test points are sensitive to
> rs6000_tune, such as: group_ending_nop, loop align (ic),
> float conversion cost etc.
It does not make sense to r
On Thu, Jul 21, 2022 at 02:42:29AM -0400, Michael Meissner wrote:
> Testing has shown that using the load vector pair and store vector pair
> instructions for block moves has some performance issues on power10. This
> patch does not set this option by default. If it is a win in other
> machines i
On Wed, Jul 20, 2022 at 05:32:01PM +0800, Kewen.Lin wrote:
> As the failure of test case gcc.target/powerpc/pr92398.p9-.c in
> PR106345 shows, some test sources for some powerpc effective
> targets use empty translation unit wrongly. The test sources
> could go with options like "-ansi -pedantic-e
Hi!
On Fri, Jul 22, 2022 at 08:41:43AM +0800, Kewen.Lin wrote:
> Hi Segher,
>
> Thanks for the comments!
Always.
> >> This patch is to fix empty TUs with one dummy variable definition
> >> accordingly.
> >
> > You can also use
> > enum{a};
> > which is shorter, but more importantly does not
On Fri, Jul 22, 2022 at 10:22:51AM +0800, Kewen.Lin wrote:
> on 2022/7/22 02:48, Segher Boessenkool wrote:
> > On Wed, Jul 20, 2022 at 05:31:11PM +0800, Kewen.Lin wrote:
> >> As PR106345 shows, some test cases should be updated with
> >> -mdejagnu-tune, since their t
Hi!
On Tue, Jul 26, 2022 at 01:13:02PM +0100, Roger Sayle wrote:
> This patch is a major revision of the patch I originally proposed here:
> https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598040.html
>
> The primary motivation of this patch is to avoid incorrect optimization
> of MODE_CC com
Hi!
On Tue, Jul 19, 2022 at 10:30:54PM +0800, Jiufu Guo wrote:
> In patch https://gcc.gnu.org/pipermail/gcc-patches/2022-July/597712.html,
> test case was not added. After more check, a testcase is added for it.
>
> The high part of the symbol address is invalid for the constant pool.
Invalid,
Hi!
On Tue, Jul 26, 2022 at 10:04:45PM +0100, Roger Sayle wrote:
> It's very important to distinguish the invariants that exist for the RTL
> data structures as held in memory (rtx),
"In memory"? What does that mean here? RTX are just RTL expressions,
nothing more, nothing less.
> vs. the use
On Wed, Jul 27, 2022 at 08:51:58AM +0100, Roger Sayle wrote:
> > They can be, as clearly documented (and obvious from the code), but you
> can
> > not ever have that in the RTL stream, which is needed for your patch to do
> > anything.
>
> That's the misunderstanding; neither this nor the previous
Hi!
On Wed, Jul 27, 2022 at 02:42:25PM +0100, Roger Sayle wrote:
> This patch implements some additional zero-extension and sign-extension
> related optimizations in simplify-rtx.cc. The original motivation comes
> from PR rtl-optimization/71775, where in comment #2 Andrew Pinski sees:
>
> Faile
Hi!
On Mon, Jul 25, 2022 at 01:11:47PM +0800, HAO CHEN GUI wrote:
> This patch adds an expand and several insns for multiply-add with
> three 64bit operands.
> PR target/103109
> * config/rs6000/rs6000.md (maddditi4): New pattern for
> multiply-add.
Please don't break lines u
On Mon, Aug 01, 2022 at 02:19:32PM +0800, Kewen.Lin wrote:
> > new file mode 100644
> > index 000..256e05d5677
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/powerpc/pr103109.c
> > @@ -0,0 +1,16 @@
> > +/* { dg-do compile { target { lp64 } } } */
>
> Since the guard is TARGET_POWERPC
Hi!
On Mon, Jul 25, 2022 at 01:11:47PM +0800, HAO CHEN GUI wrote:
> +(define_insn "madddi4_lowpart"
> + [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
> + (subreg:DI
> + (plus:TI
> + (mult:TI (any_extend:TI
> +(match_operand:DI 1 "gpc_reg_operand" "r"))
>
Hi!
On Fri, Jul 29, 2022 at 07:57:51AM +0100, Roger Sayle wrote:
> > On Wed, Jul 27, 2022 at 02:42:25PM +0100, Roger Sayle wrote:
> > > This patch implements some additional zero-extension and
> > > sign-extension related optimizations in simplify-rtx.cc. The original
> > > motivation comes from
Hi!
On Wed, Aug 03, 2022 at 04:24:15PM +0800, HAO CHEN GUI wrote:
> This patch changes the definition of TARGET_MADDLD and includes
> TARGET_POWERPC64, since maddld is a 64 bit instruction.
Hrm. But the maddld insn is useful for SImode as well, in 32-bit mode,
it is just its name that is a bit
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