+ linaro-toolchain as I don't understand the CI issues on patchwork.
On Wed, Sep 27, 2023 at 8:40 PM Wilco Dijkstra wrote:
>
> Hi Ramana,
>
> > Hope this helps.
>
> Yes definitely!
>
> >> Passes regress/bootstrap, OK for commit?
> >
> > Target ? armhf ? --with-arch , -with-fpu , -with-float param
> On 5 Oct 2023, at 14:04, Victor Do Nascimento
> wrote:
>
> External email: Use caution opening links or attachments
>
>
> On 10/5/23 12:42, Richard Earnshaw wrote:
>>
>>
>> On 03/10/2023 16:18, Victor Do Nascimento wrote:
>>> This patch adds the `aarch64-sys-regs.def' file to GCC, teachi
On Fri, Jul 6, 2018 at 10:16 AM, Tamar Christina
wrote:
> Hi All,
>
> This fixes a -Wpedantic error with the testcase because of extra ; left after
> the
> functions.
>
> Regtested single test on aarch64-none-elf and no issues.
>
> Committed under the GCC obvious rule.
So I am curious as to why
On Fri, Jul 6, 2018 at 1:04 PM, Christophe Lyon
wrote:
> On Fri, 6 Jul 2018 at 13:56, Ramana Radhakrishnan
> wrote:
>>
>> On Fri, Jul 6, 2018 at 10:16 AM, Tamar Christina
>> wrote:
>> > Hi All,
>> >
>> > This fixes a -Wpedantic error with t
On Fri, Jul 6, 2018 at 1:13 PM, Tamar Christina wrote:
>> >>
>> >> So I am curious as to why this shows up in Christophe's test but not
>> >> in any of your test runs or indeed the testruns with our scripts.
>> >>
>
> The test was changed before sending out, the individual entries moved to
> a mac
e unpredictable behaviour.
Bootstrapped and regression tested on AArch64 , no regressions.
Ok ?
Thanks,
Ramana
* config/aarch64/atomics.md (aarch64_store_exclusive): Add early
clobber.
commit 0608cb64b97368dc1bbea87e3a9541cfb832c015
Author: Ramana Radhakrishnan
Date: Tue Jun 12 16:0
On Thu, Jul 19, 2018 at 8:31 AM, Richard Sandiford
wrote:
> Hi,
>
> Thanks for doing this.
>
> Steve Ellcey writes:
>> This is a patch to support the Aarch64 SIMD ABI [1] in GCC. I intend
>> to eventually follow this up with two more patches; one to define the
>> TARGET_SIMD_CLONE* macros and on
On Mon, Jul 23, 2018 at 12:09 PM, Umesh Kalappa
wrote:
> Hi Richard,
>
> We tested on the SP and yes the problem persist on the SP too and
> attached patch will fix the both SP and DP issues for the denormal
> resultant.
> We bootstrapped the compiler ,look ok to us with minimal testing ,
Have y
On Thu, Jul 19, 2018 at 10:11 AM, Richard Biener wrote:
>
> Status
> ==
>
> The GCC 8 branch is frozen for preparation of the GCC 8.2 release.
> All changes to the branch now require release manager approval.
>
>
> Previous Report
> ===
>
> https://gcc.gnu.org/ml/gcc/2018-07/msg001
On Tue, Jul 24, 2018 at 10:55 PM, Steve Ellcey wrote:
> On Tue, 2018-07-24 at 22:04 +0100, James Greenhalgh wrote:
>>
>>
>> I'd say this patch isn't desirable for trunk. I'd be interested in use cases
>> that need a static decision on presence of LSE that are not better expressed
>> using higher l
On Thu, Jul 26, 2018 at 6:26 PM, Joseph Myers wrote:
> On Mon, 16 Jul 2018, Alexander von Gluck IV wrote:
>
>> * We have been dragging these around since gcc 4.x.
>> * Some tweaks will likely be needed, but this gets our foot
>> in the door.
>>
>> Authors:
>> Fredrik Holmqvist
>> Jerome Duva
On Wed, Jul 19, 2023 at 5:44 PM Andrew Carlotti via Gcc-patches
wrote:
>
> Updated patch to fix the fp16 intrinsic pragmas, and pushed to master.
> OK to backport to GCC 13?
>
>
> Many intrinsics currently depend on both an architecture version and a
> feature, despite the corresponding instructio
On Tue, Nov 26, 2019 at 3:18 PM Wilco Dijkstra wrote:
>
> Hi,
>
> While code hoisting generally improves codesize, it can affect performance
> negatively. Benchmarking shows it doesn't help SPEC and negatively affects
> embedded benchmarks. Since the impact is relatively small with -O2 and mainly
On Fri, Feb 7, 2020 at 8:19 AM Jakub Jelinek wrote:
>
> Hi!
>
> As the following testcase shows, unwind.h on ARM can't be (starting with GCC
> 10) compiled with -std=c* modes, only -std=gnu* modes.
> The problem is it uses asm keyword, which isn't a keyword in those modes
> (system headers vs. non
On Sat, Dec 16, 2023 at 6:18 AM Andrew Carlotti wrote:
>
> This adds initial support for function multiversioning on aarch64 using
> the target_version and target_clones attributes. This loosely follows
> the Beta specification in the ACLE [1], although with some differences
> that still need to
e went with LDXP in this form.
Has something changed from then ?
Reviewed-by : Ramana Radhakrishnan
regards
Ramana
>
> Passes regress/bootstrap, OK for commit?
>
> gcc/ChangeLog/
> PR target/111404
> * config/aarch64/aarch64.cc (aarch64_split_compare_and_swa
Hi Wilco,
Thanks for your email.
On Tue, Sep 26, 2023 at 12:07 AM Wilco Dijkstra wrote:
>
> Hi Ramana,
>
> >> __sync_val_compare_and_swap may be used on 128-bit types and either calls
> >> the
> >> outline atomic code or uses an inline loop. On AArch64 LDXP is only
> >> atomic if
> >> the val
Reviewed-by: Ramana Radhakrishnan
A very initial review here . I think it largely looks ok based on the
description but I've spotted a few obvious nits and things that come
to mind on reviewing this. I've not done a very deep review but hope
it helps you move forward. I'm happy t
n_logic , simd, 4] mov\t%0., %1.
> + [?r , w ; multiple , * , 8] #
> + [?w , r ; multiple , * , 8] #
> + [?r , r ; multiple , * , 8] #
> + [w , Dn; neon_move , simd, 4] <<
> aarch64_output_simd_mov_immediate (ope
On Wed, Sep 27, 2023 at 1:51 AM Tamar Christina wrote:
>
> Hi All,
>
> Following the Neoverse N/V and Cortex-A optimization guides SIMD 0 immediates
> should be created with a movi of 0.
>
> At the moment we generate an `fmov .., xzr` which is slower and requires a
> GP -> FP transfer.
>
> Bootstr
As $Subject.
Pushed.
Ramana
commit 01691a6d0582a921bbcc09ab5e0cd9e7deca2cca
Author: Ramana Radhakrishnan
Date: Tue Jun 18 16:05:31 2024 +0530
[MAINTAINERS] Update my email address and move to DCO.
Signed-off-by: Ramana Radhakrishnan
* MAINTAINERS: Update
> On 6 Aug 2024, at 4:14 PM, Richard Sandiford
> wrote:
>
> External email: Use caution opening links or attachments
>
>
> Kyrylo Tkachov writes:
>>> On 5 Aug 2024, at 18:00, Richard Sandiford
>>> wrote:
>>>
>>> External email: Use caution opening links or attachments
>>>
>>>
>>> Kyryl
> On 9 Sep 2024, at 10:34 PM, Andi Kleen wrote:
>
> External email: Use caution opening links or attachments
>
>
> Andi Kleen writes:
>
> Ping^4
>
> Could someone please approve this (nearly trivial) patch?
>
> Thanks,
> -Andi
>
>> Andi Kleen writes:
>>
>> Ping^3
>>
>>> Andi Kleen wr
On 08/19/13 11:54, Matthew Gretton-Dann wrote:
All,
The attached patch removes the setting of MULTILIB_DEFAULTS for
arm*-*-linux-gnueabi* targets.
The current setting of MULTILIB_DEFAULTS includes mfloat-abi=hard,
which for arm*-*-linux-gnueabi is not true. This makes generating a
hard-float m
Ok for trunk?
Thanks,
Kyrill
2013-09-13 Kyrylo Tkachov
* config/arm/arm.md (arm_cmpsi_insn): Split rI alternative.
Set type attribute correctly. Set predicable_short_it attribute.
(cmpsi_shiftsi): Remove %? from output template.
Ok.
Ramana
AArch32:
No more issues in libstdc++ as well (same as reasons as AArch64), and
only 3 failures in the testsuite:
- The first one is invalid as the test sans the assembler for
"ldaex\tr\[0-9\]+..." and it fails because with LRA the chosen
register is r12 and thus the instruction is "ldaex ip,.
On 09/24/13 09:27, Yvan Roux wrote:
Hi,
this patch fix the scan-assembler pattern of
gcc.target/arm/atomic-comp-swap-release-acquire.c, which didn't
allowed aliases register and failed when enabling LRA where 'ip' is
used in the ldaex instruction.
Ok -
The changelog could just read : Adjust
On 10/01/13 08:42, Kugan wrote:
Hi,
I am attaching a patch that reverts Split shift di patterns (r197527) as
it introduced PR58578. I am also attaching a patch to add a testcase
based on this failiures.
No regression on qemu for arm-none-eabi and new testcase now passes.
Is this OK?
Thanks,
K
On 09/10/12 07:34, Chung-Lin Tang wrote:
On 2012/8/28 下午 04:14, Chung-Lin Tang wrote:
On 12/7/12 5:47 PM, Ramana Radhakrishnan wrote:
On 12 July 2012 07:52, Chung-Lin Tang wrote:
ARM parts, no further notes.
ARM parts are ok, modulo approval for generic parts and no
regressions with
On Tue, Sep 25, 2012 at 5:32 PM, Dinar Temirbulatov
wrote:
> Hi Ramana,
> Here is obvious fix for PR49423, I just added pool range for
Sorry for the late response - I've been on vacation.
No it's not ok. These were removed deliberately and subsequent
efforts to put these back on have been rejec
On 18 Oct 2012, at 02:50, DJ Delorie wrote:
>
> Fixed 16-bit widening multiplies by a constant by limiting constant
> matches to 16 bit constants. Applied.
>
>PR target/54950
>* config/m32c/predicates.md (m32c_const_u16_operand): New.
>* config/m32c/muldiv.md: Use it.
>
> Index:
(feature_matrix):
Likewise.
* gcc.target/arm/ftest-support.h (architecture): Add ARMv8-A.
* lib/target-supports.exp: Add ARMv8-A architecture expectation.
2012-10-17 Matthew Gretton-Dann
Ramana Radhakrishnan
* config.gcc: Add support for ARMv8 for arm
Hi,
This patch originally by Matt, adds support for the fma intrinsics in
arm_neon.h at the correct architecture levels.
Tested on arm-linux-gnueabi with no regressions.
Applied,
cheers
Ramana
2012-10-18 Matthew Gretton-Dann
Ramana Radhakrishnan
* config/arm
On 10/18/12 13:05, Ramana Radhakrishnan wrote:
Applied,
And this time with the patch.
RamanaFrom ae8086e2d1ecae8fee711942d4b530947001e8ef Mon Sep 17 00:00:00 2001
From: Ramana Radhakrishnan
Date: Wed, 17 Oct 2012 18:40:14 +0100
Subject: [PATCH 2/3] neon fma intrinsics.
---
gcc/config
Hi,
This adjusts the existing A15 scheduler description to support Neon.
Tested on arm-linux-gnueabi cross. Applied to trunk.
regards,
Ramana
2012-10-18 Matthew Gretton-Dann
Ramana Radhakrishnan
Sameera Deshpande
* config/arm/cortex-a15-neon.md: New
On Fri, Oct 19, 2012 at 7:46 AM, Zhenqiang Chen
wrote:
> Hi,
>
> In function arm_expand_compare_and_swap, oldval is converted to SImode
> when its "mode" is QImode/HImode. After "FALLTHRU" to "case SImode",
> we should use "SImode", other than "mode" (which is QImode/HImode).
> And INSN atomic_com
On Tue, Oct 16, 2012 at 10:25 AM, Chung-Lin Tang
wrote:
> On 12/9/27 6:25 AM, Janis Johnson wrote:
>> On 09/26/2012 01:58 AM, Chung-Lin Tang wrote:
>>
>> +/* { dg-do compile } */
>> +/* { dg-options "-mthumb -O1 -march=armv5te -fno-omit-frame-pointer
>> -fno-forward-propagate" } */
>> +/* { dg-r
On 10/23/12 16:38, Jeff Law wrote:
> On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
>
> The one question in the back of my mind is whether or not this uses the
> new iterator support we discussed a few months ago? I can't recall if
> that was integrated into the trunk or not.
Generic support fo
Ok for trunk?
Ok.
ramana
On 10/23/12 16:46, Vladimir Makarov wrote:
Hi, I was going to merge LRA into trunk last Sunday. It did not
happen. LRA was actively changed last 4 weeks by implementing
reviewer's proposals which resulted in a lot of new LRA regressions on
GCC testsuite in comparison with reload. Finally,
On 10/24/12 21:02, Vladimir Makarov wrote:
The following patch fix
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55055
In this case, operand was an address containing subreg. LRA before
the patch processed only operands which are subregs of regs.
The patch was successfully bootstrapp
On 10/02/13 23:49, Rong Xu wrote:
Here is the new patch. Honaz: Could you take a look?
Thanks,
-Rong
On Wed, Oct 2, 2013 at 2:31 PM, Jan Hubicka wrote:
Thanks for the suggestion. This is much cleaner than to use binary parameter.
Just want to make sure I understand it correctly about the or
> gcc/ChangeLog:
>
> 2013-10-03 Renlin Li
>
> * config/arm/arm-cores.def (cortex-a53): Use cortex tunning.
s/tunning/tuning.
Ok with that change.
Ramana
On 10/04/13 22:23, Jan Hubicka wrote:
On Fri, Oct 4, 2013 at 11:54 AM, Jan Hubicka wrote:
I looked at this problem. Bug updated
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58619
This is a bug when updating block during tree-inline. Basically, it is
legal for *n to be NULL. E.g. When gimple_blo
>> Can someone comment / approve it quickly so that we get AArch32 and AArch64
>> linux cross-builds back up ?
>
> Ok.
Applied for Dehao as r203269 . Tests on arm came back ok.
Ramana
>
> Thanks,
> Richard.
>
>>
>> regards
>> Ramana
>>
>>>
>>> Honza
>>>
Dehao
>
> Honza
>>>
not affect default build times and we have
auto-testers internally that use this feature.
I think I can apply the changes for config.gcc but I'd still like
another set of eyes on this please.
Ok ?
regards
Ramana
Matthew Gretton-Dann
Ramana Radhakrishnan
* config
On 10/24/13 00:04, Kugan wrote:
Hi,
arm testcases neon-vcond-ltgt.c and neon-vcond-unordered.c fails in
Linaro 4.8 branch. It is not reproducable with trunk but it can happen.
Both neon-vcond-ltgt.c and neon-vcond-unordered.c scans for vbsl
instruction, with other vector instructions. However, a
On 10/24/13 00:04, Kugan wrote:
Hi,
arm testcases neon-vcond-ltgt.c and neon-vcond-unordered.c fails in
Linaro 4.8 branch. It is not reproducable with trunk but it can happen.
Both neon-vcond-ltgt.c and neon-vcond-unordered.c scans for vbsl
instruction, with other vector instructions. However, a
You are better off CCing the maintainers for such reviews. Let me do
that for you. I cannot approve or reject this patch but I have a few
comments as below.
On 10/29/13 09:22, Hurugalawadi, Naveen wrote:
diff -uprN '-x*.orig' mainline-orig/gcc/config/aarch64/aarch64.md
gcc-4.8.0/gcc/confi
On 10/09/13 23:16, Christophe Lyon wrote:
Hi,
This patch is a first small sample of dejagnu-ization of my ARM Neon
intrinsics tests.
Thanks for attempting this and apologies for the slow response - I've
been busy with a few other things internally.
It's derived from my previous work at
ht
On 10/29/13 12:15, Kyrill Tkachov wrote:
Hi all,
This patch adds the new rtx costs for the Cortex-A7 core as well as a new tuning
structure to contain it.
Tested arm-none-eabi on qemu and no benchmark regressions.
Ok for trunk?
Ok.
Ramana
Cong,
Please don't do the following.
>+++ b/gcc/testsuite/gcc.dg/vect/
vect-reduc-sad.c
@@ -0,0 +1,54 @@
+/* { dg-require-effective-target sse2 { target { i?86-*-* x86_64-*-* } } } */
you are adding a test to gcc.dg/vect - It's a common directory
containing tests that need to run on multiple arc
- tested that the testcase works just fine.
Applied to trunk and will backport to the 4.8 branch in a day or so
after the auto-testers have had a chance to play with this.
regards
Ramana
2013-10-30 Ramana Radhakrishnan
PR target/58854
* config/arm/arm.c
Mans,
Can you please follow the guidelines as in
http://gcc.gnu.org/contribute.html ? Notably what's missing in your
submission here is
1. A changelog entry - well I'll create one for you . (see below)
2. A note on how this was tested and what impact this has on any
testcase that you have.
3. A c
On Thu, Oct 31, 2013 at 12:29 AM, Cong Hou wrote:
> On Tue, Oct 29, 2013 at 4:49 PM, Ramana Radhakrishnan
> wrote:
>> Cong,
>>
>> Please don't do the following.
>>
>>>+++ b/gcc/testsuite/gcc.dg/vect/
>> vect-reduc-sad.c
>> @@ -0,0 +1,54 @
On Wed, Oct 30, 2013 at 3:03 PM, Vladimir Makarov wrote:
> The following patch fixes
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58784
>
> LRA has an old check of legitimate addresses. It was written before a newer
> address decomposition code which makes more correct checks of addresses.
>
>
On Wed, Oct 30, 2013 at 3:03 PM, Vladimir Makarov wrote:
> The following patch fixes
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58784
>
> LRA has an old check of legitimate addresses. It was written before a newer
> address decomposition code which makes more correct checks of addresses.
>
>
On Fri, Jan 22, 2016 at 9:32 AM, Kyrill Tkachov
wrote:
> Hi Han,
>
> On 21/01/16 22:57, Han Shen wrote:
>>
>> Hi Kyrill, the patched gcc generates correct asm for me for the test
>> case. (I'll then build the whole system to see if other it-block
>> related bugs are gone too.)
>>
>> One short que
On Tue, Jun 30, 2015 at 2:15 AM, Jim Wilson wrote:
> This is my suggested fix for PR 65932, which is a linux kernel
> miscompile with gcc-5.1.
>
> The problem here is caused by a chain of events. The first is that
> the relatively new eipa_sra pass creates fake parameters that behave
> slightly d
On Fri, Jan 22, 2016 at 9:52 AM, Kyrill Tkachov
wrote:
> Hi all,
>
> As part of investigating the codegen effects of a fix for PR 65932 I found
> we assign
> too high a cost for the sign-extending multiply instruction SMULBB.
> This is because we add the cost of a multiply-extend but then also rec
On Fri, Jan 22, 2016 at 9:52 AM, Kyrill Tkachov
wrote:
> Hi all,
>
> PR target/65932 is a wrong-code bug affecting arm and has manifested itself
> when compiling the Linux kernel, so it's something that we really
> ought to fix. The problem stems from the fact that PROMOTE_MODE and
> TARGET_PROMOT
On Tue, Dec 15, 2015 at 10:59 AM, Wilco Dijkstra wrote:
> ping
>
>> -Original Message-
>> From: Wilco Dijkstra [mailto:wilco.dijks...@arm.com]
>> Sent: 19 November 2015 18:12
>> To: gcc-patches@gcc.gnu.org
>> Subject: [PATCH][ARM] Enable fusion of AES instructions
>>
>> Enable instruction
On Sun, Jan 17, 2016 at 9:06 AM, Prathamesh Kulkarni
wrote:
> On 31 July 2015 at 15:04, Ramana Radhakrishnan
> wrote:
>>
>>
>> On 29/07/15 11:09, Prathamesh Kulkarni wrote:
>>> Hi,
>>> This patch tries to implement division with multiplication by
&
On Mon, Jan 18, 2016 at 12:14 PM, Alan Lawrence wrote:
> This cleans up the neon_reinterpret code on ARM in a similar way to AArch64.
> Rather than a builtin backing onto an expander that emits a mov insn, we can
> just use a cast, because GCC defines casts of vector types as keeping the same
> bi
On 04/02/16 11:04, Ramana Radhakrishnan wrote:
> On Mon, Jan 18, 2016 at 12:14 PM, Alan Lawrence wrote:
>> This cleans up the neon_reinterpret code on ARM in a similar way to AArch64.
>> Rather than a builtin backing onto an expander that emits a mov insn, we can
>> just us
On Mon, Feb 15, 2016 at 11:32 AM, Kyrill Tkachov
wrote:
>
> On 04/02/16 08:58, Ramana Radhakrishnan wrote:
>>
>> On Tue, Jun 30, 2015 at 2:15 AM, Jim Wilson wrote:
>>>
>>> This is my suggested fix for PR 65932, which is a linux kernel
>>> miscomp
On Tue, Feb 16, 2016 at 11:47 AM, David Sherwood wrote:
> Hi,
>
> I have a fix for bugzilla defect 69532, which is a simple change to
> a couple of arm tests to check for effective target arm_v8_neon_hw
> instead of arm_v8_neon_ok.
>
> Tested:
> arm-none-eabi: No regressions in arm.exp testsuite.
On 19/02/16 15:24, Kyrill Tkachov wrote:
> Hi all,
>
> The atomic_loaddi expander on arm has some issues and can benefit from a
> rewrite to properly
> perform double-word atomic loads on various architecture levels.
>
> Consider the code:
> --
> #include
>
> atomic_ullon
On Fri, Feb 5, 2016 at 10:00 AM, Kyrill Tkachov
wrote:
> Hi all,
>
> I've been auditing the patterns in the arm backend that were added/modified
> for -mrestrict-it
> and I've come up with a few runtime tests that end up generating those
> patterns.
> This patch contains 4 tests for 4 patterns tha
On 01/03/16 09:54, Richard Biener wrote:
> On Tue, 1 Mar 2016, James Greenhalgh wrote:
>
>> On Tue, Mar 01, 2016 at 10:21:27AM +0100, Richard Biener wrote:
>>> On Mon, 29 Feb 2016, James Greenhalgh wrote:
>>>
On Fri, Feb 26, 2016 at 09:32:53AM +0100, Richard Biener wrote:
>
> The fo
On 03/03/16 09:35, Kyrill Tkachov wrote:
> Hi all,
>
> In this PR shrink-wrapping ends up duplicating the load-exclusive part of a
> load-exclusive/store-exclusive loop
> used to implement an atomic compare exchange operation. Look in bugzilla for
> the kind of sequences generated.
> The load-ex
On Thu, Mar 3, 2016 at 9:40 AM, Thomas Preudhomme
wrote:
> On Friday 15 January 2016 12:45:04 Ramana Radhakrishnan wrote:
>> On Wed, Dec 16, 2015 at 9:11 AM, Thomas Preud'homme
>>
>> wrote:
>> > During reorg pass, thumb1_reorg () is tasked with rewriting m
Sorry about the slow response. Been on holiday.
On 20/11/13 16:27, Renlin Li wrote:
Hi all,
This patch will make the arm back-end use vcvt for float to fixed point
conversions when applicable.
Test on arm-none-linux-gnueabi has been done on the model.
Okay for trunk?
+ (define_insn "*comb
On 04/12/13 16:05, Ian Bolton wrote:
Hi,
Currently, on ARM, you have to either call abort() or raise(SIGTRAP)
to achieve a handy crash.
This patch allows you to instead call __builtin_trap() which is much
more efficient at falling over because it becomes just a single
instruction that will trap
On Tue, Dec 10, 2013 at 9:24 AM, Zhenqiang Chen wrote:
> Ping?
>
> This is definitely a bug. The LIB1ASMFUNCS defined in t-bpabi should not be
> overridden by t-arm.
>
> OK for 4.8 and trunk
This looks correct. Ok if no regressions for both 4.8 and trunk.
regards
Ramana
>
> Thanks!
> -Zhenqian
Yvan,
On Wed, Dec 11, 2013 at 10:35 AM, Yvan Roux wrote:
> Hi Vladimir,
>
> I've some regressions on ARM after this SP elimination patch, and they
> are execution failures. Here is the list:
Pragmatically, I think it's time we turned LRA on by default now that
we are in stage3 and that would he
On 18/12/13 11:46, Kyrill Tkachov wrote:
Hi all,
This patch adds the recently introduced cores to the t-aprofile multilib
machinery. The values added are cortex-a15.cortex-a7, cortex-a12, cortex-a57 and
cortex-a57.cortex-a53.
Tested arm-none-eabi on qemu and model.
Ok for trunk?
Ok.
Ramana
On Fri, Dec 6, 2013 at 5:35 PM, Tejas Belagod wrote:
>
> Hi,
>
> The attached patch adds crypto types for instruction classificiation.
>
> Tested on aarch64-none-elf. OK for trunk?
Ok but please work with Kyryll to make sure only one version of this
gets in, obviously.
Ramana
>
> Thanks,
> Teja
On Tue, Dec 3, 2013 at 1:46 PM, Kyrill Tkachov wrote:
> Ping?
> http://gcc.gnu.org/ml/gcc-patches/2013-11/msg02351.html
>
> Thanks,
> Kyrill
Ok if no objections in 24 hours.
Ramana
>
>
> On 26/11/13 09:44, Kyrill Tkachov wrote:
>>
>> Ping?
>>
>> Thanks,
>> Kyrill
>>
>> On 19/11/13 17:04, Kyrill
On Wed, Dec 18, 2013 at 1:46 PM, Yvan Roux wrote:
> Hi,
>
> this patch from Vladimir fixes an ICE when compiling newlib in Thumb1.
> It returns NO_REGS in THUMB_SECONDARY_OUTPUT_RELOAD_CLASS, the same
> way we did for THUMB_SECONDARY_INPUT_RELOAD_CLASS.
This is OK if there are no regressions for
On 06/12/13 17:19, Kyrill Tkachov wrote:
Hi all,
Following the implementation of the Crypto intrinsics I posted earlier this
week, this patch implements the vceq_p64 and vtst_p64 intrinsics that operate on
the new poly64_t type. They do not have a regular form and can thus not be
autogenerated f
On 10/07/15 12:35, Christophe Lyon wrote:
> On 10 July 2015 at 09:14, Christian Bruel wrote:
>>
>> On 07/09/2015 05:39 PM, Christophe Lyon wrote:
>>> Some multilibs do not support Thumb mode on ARM targets. This is the
>>> case for instance when target is arm-linux-gnueabihf and with
>>> -march=
had a hand in writing this patch up.
Please add a testcase.
>
>
> 2015-06-24 Michael Collison
> 2012-05-01 Ramana Radhakrishnan
Please fix the Changelog formatting here.
>
> * gcc/config/arm/arm.md (*arm_smin_cmp): New pattern.
> (*arm_umin_cmp): Likewise.
>
&
On 09/07/15 15:40, Szabolcs Nagy wrote:
> On 06/07/15 16:39, Marcus Shawcroft wrote:
>> On 6 July 2015 at 09:20, Szabolcs Nagy wrote:
>>
>>> 2015-07-06 Szabolcs Nagy
PR target/66731 in Changelog ?
Ramana
>>>
>>> * gcc.target/aarch64/fnmul-1.c: New.
>>> * gcc.target/aarch6
sions.
I will apply this to trunk in a couple of days if folks don't have any comments
and try out a few more multilibs in order to stress this a bit.
regards
Ramana
Ramana Radhakrishnan
* config/arm/arm-ldmstm.ml: Rewrite to using unified syntax.
* config/arm/ldms
>>
> Committed to trunk r226036.
> Is patch ok for fsf-5?
OK for all release branches where affected as this is a testism.
Ramana
> kind regards,
> Alex
>
On Fri, Jul 24, 2015 at 10:04 AM, Kyrill Tkachov wrote:
>> It arrives as SSA_NAME == N and you can use get_gimple_for_ssa_name
>> or get_def_for_expr to get at the defining stmt if that is possible
>> (it's still unexpanded and thus TERed) and expand a different
>> expression.
>
>
> Thanks, so it'
>>
>> In expr.c, with TER you can detect such patterns, in this case when
>> expanding the comparison, but perhaps we want a *.pd file that would have
>> rules that would be only GIMPLE and only enabled in a special pass right
>> before (or very close to) expansion, that would perform such instruct
Hi,
movtf is unnecessary as a separate expander. Move this to be with
the standard scalar floating point expanders.
Achieved by adding a new iterator and then using the same.
Tested cross aarch64-none-elf and no regressions.
Ramana
* config/aarch64/aarch.md (mov:GPF): Use ALLTF.
trunk - however this
version is still applicable for all release branches.
More testing is still underway but in the meanwhile I'd like to
put this up for some comments please.
regards
Ramana
Ramana Radhakrishnan
PR target/63304
* config/aarch64/aarch
On 29/07/15 11:09, Prathamesh Kulkarni wrote:
> Hi,
> This patch tries to implement division with multiplication by
> reciprocal using vrecpe/vrecps
> with -funsafe-math-optimizations and -freciprocal-math enabled.
> Tested on arm-none-linux-gnueabihf using qemu.
> OK for trunk ?
>
> Thank you,
On 27/07/15 11:29, Matthew Wahab wrote:
> Ping. Updated patch attached.
>
> Also, retested for arm-none-linux-gnueabihf with native bootstrap and make
> check and for arm-none-eabi with cross compiled make check.
>
> On 02/07/15 14:12, Matthew Wahab wrote:
>> The __sync builtins are implemented
On 27/07/15 11:31, Matthew Wahab wrote:
> Ping. Updated patch attached.
>
> Also, retested for arm-none-linux-gnueabihf with native bootstrap and make
> check and for arm-none-eabi with cross compiled make check.
>
> On 02/07/15 14:17, Matthew Wahab wrote:
>> This patch backports the tests adde
On 27/07/15 11:31, Matthew Wahab wrote:
> Ping. Updated patch attached.
>
> Also, retested for arm-none-linux-gnueabihf with native bootstrap and make
> check and for arm-none-eabi with cross compiled make check.
>
>
> On 02/07/15 14:15, Matthew Wahab wrote:
>> This patch backports the changes
On 27/07/15 11:32, Matthew Wahab wrote:
> Ping. Updated patch attached.
>
> Also, retested for arm-none-linux-gnueabihf with native bootstrap and make
> check and for arm-none-eabi with cross compiled make check.
>
> On 02/07/15 14:18, Matthew Wahab wrote:
>> This patch backports fixes for the
Hmmm, not sure if this is that straightforward just looking at this..
> 2015-07-24 Kyrylo Tkachov
>
> * config/arm/arm.md (*if_neg_move): Convert to insn_and_split.
> Enable for TARGET_32BIT.
> (*if_move_neg): Likewise.
> commit 1b495b6cb68c77f628e1c1d672c06dcdf5ccf79b
> Author:
>>
>>
>> So, we have a predicate that doesn't cover all the constraints - in this
>> case aren't we forcing everything into operand0. What happens if we just
>> delete this pattern instead of turning it into an insn_and_split - after all
>> we have other parts of the backend where conditional n
On 31/07/15 11:49, Kyrill Tkachov wrote:
>
> On 31/07/15 11:34, Ramana Radhakrishnan wrote:
>>>>
>>>> So, we have a predicate that doesn't cover all the constraints - in this
>>>> case aren't we forcing everything into operand0. What hap
>
>
> As mentioned earlier I'll change operand 1 to be use the s_register_operand
> predicate and re-test.
> Is that change ok as well?
Yes that's ok .
Ramana
>
> Thanks,
> Kyrill
>
>>
>>
>> regards
>> Ramana
>>
>
On Wed, Sep 16, 2015 at 3:34 PM, David Edelsohn wrote:
> On Wed, Sep 16, 2015 at 10:28 AM, Bill Schmidt
>
> This is okay.
>
> I don't think that I have seen iterators for UNSPECs, but maybe
> someone else is aware of the right idiom.
https://gcc.gnu.org/onlinedocs/gccint/Int-Iterators.html .
def
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