Hi,
One of our internal patches is a multilib patch that helps in testing
bare-metal toolchains for v7-a and above.
It's a bit brute force but this is something that we use internally
every night to build a set of base libraries in a hierarchical directory
structure to be used by bare metal toolchains along with those that want
to do so from a single toolchain. I don't claim to particularly like
this patch especially the part of writing the MULTILIB_REUSE macros to
match as many of the options that I could think of that folks would use
sensibly along with such a toolchain.
- I've missed a few -mfpu options but I deemed them to be uncommon
enough. If people want to submit a follow on patch for those, I'd be
happy to take them but this will do for now.
- Additionally if people want to extend this to cover M profile cores
and all cores, feel free to do so. I don't intend to do so in this cut
of the makefile fragment.
- I have deliberately avoided documenting that ARM in the supported list
for --with-multilib-list, because we aren't providing this option like
other targets in this regard.
- Additionally one cannot use with --with-cpu , --with-fpu, --with-float
--with-mode --with-arch command line options with this as the make file
fragment is written assuming such a case.
This does not handle all the general options that --with-multilib-list
provides with actually providing options on the command line, trying to
write this with the command lines as suggested in other ports for the
length that I have in mind, is just going to be unweildy and extremely
irritating on the command line.
Additionally there is no easy way of supplying multilib_reuse options on
the command line, with the result that the configure command line would
be long, prone to error and extremely fragile. This is less fragile than
that approach and hence I prefer this form for the ARM backend for the
current work and for people who are interested in this sort of a thing.
Additionally tested with a noddy shell script that goes something like
and checked for no failures.
for mode in marm mthumb ; do
for fabi in hard softfp ; do
for fpu in vfpv3-d16 vfpv3 vfpv4-d16 vfpv4 neon neon-vfpv4 fp-armv8
neon-fp-armv8 ; do
for cpu in cortex-a8 cortex-a5 cortex-a9 cortex-a7 cortex-a15
cortex-a53; do
x=`$COMPILER /tmp/hello.c -mcpu="$cpu" -mfpu="$fpu"
-mfloat-abi="$fabi" "-$mode" -print-multi-directory -lm`
if [ "$x" != "." ];
then
echo "PASS: mcpu=$cpu mfpu=$fpu mfloat-abi=$fabi -$mode"
else
echo "FAIL: mcpu=$cpu mfpu=$fpu mfloat-abi=$fabi -$mode"
fi
done
done
done
for fpu in vfpv3-d16 vfpv3 vfpv4-d16 vfpv4 neon neon-vfpv4 fp-armv8
neon-fp-armv8 crypto-neon-fp-armv8 ; do
for fabi in hard softfp ; do
for arch in armv7-a armv8-a ; do
# $COMPILER /tmp/hello.c -march="$arch" -mfpu="$fpu"
-mfloat-abi="$fabi" -"$mode" -lm
x=`$COMPILER /tmp/hello.c -march="$arch" -mfpu="$fpu"
-mfloat-abi="$fabi" "-$mode" -print-multi-directory -lm`
if [ "$x" != "." ];
then
echo "PASS: march=$arch mfpu=$fpu mfloat-abi=$fabi -$mode"
else
echo "FAIL: march=$arch mfpu=$fpu mfloat-abi=$fabi -$mode"
fi
done
done
done
Tested on arm-none-eabi with --with-multilib-list=aprofile C, C++ and
Fortran with no regressions on an ARM fast model. Note that this is not
on by default so will not affect default build times and we have
auto-testers internally that use this feature.
I think I can apply the changes for config.gcc but I'd still like
another set of eyes on this please.
Ok ?
regards
Ramana
<DATE> Matthew Gretton-Dann <matthew.gretton-d...@arm.com>
Ramana Radhakrishnan <ramana.radhakrish...@arm.com>
* config/arm/t-aprofile: New file.
* config.gcc: Handle --with-multilib-list option.diff --git a/gcc/config.gcc b/gcc/config.gcc
index 605efc0..75ce74a 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3437,6 +3437,43 @@ case "${target}" in
if test "x$with_arch" != x && test "x$with_cpu" != x; then
echo "Warning: --with-arch overrides
--with-cpu=$with_cpu" 1>&2
fi
+
+ # Add extra multilibs
+ if test "x$with_multilib_list" != x; then
+ arm_multilibs=`echo $with_multilib_list | sed -e 's/,/
/g'`
+ for arm_multilib in ${arm_multilibs}; do
+ case ${arm_multilib} in
+ aprofile)
+ # Note that arm/t-aprofile is a
+ # stand-alone make file fragment to be
+ # used only with itself. We do not
+ # specifically use the
+ # TM_MULTILIB_OPTION framework because
+ # this shorthand is more
+ # pragmatic. Additionally it is only
+ # designed to work without any
+ # with-cpu, with-arch with-mode
+ # with-fpu or with-float options.
+ if test "x$with_arch" != x \
+ || test "x$with_cpu" != x \
+ || test "x$with_float" != x \
+ || test "x$with_fpu" != x \
+ || test "x$with_mode" != x ; then
+ echo "Error: You cannot use any of
--with-arch/cpu/fpu/float/mode with --with-multilib-list=aprofile" 1>&2
+ exit 1
+ fi
+ tmake_file="${tmake_file}
arm/t-aprofile"
+ break
+ ;;
+ default)
+ ;;
+ *)
+ echo "Error:
--with-multilib-list=${with_multilib_list} not supported." 1>&2
+ exit 1
+ ;;
+ esac
+ done
+ fi
;;
fr*-*-*linux*)
diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile
new file mode 100644
index 0000000..ce45d4d
--- /dev/null
+++ b/gcc/config/arm/t-aprofile
@@ -0,0 +1,177 @@
+# Copyright (C) 2012-2013 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+# This is a target makefile fragment that attempts to get
+# multilibs built for the range of CPU's, FPU's and ABI's that
+# are relevant for the A-profile architecture. It should
+# not be used in conjunction with another make file fragment and
+# assumes --with-arch, --with-cpu, --with-fpu, --with-float, --with-mode
+# have their default values during the configure step. We enforce
+# this during the top-level configury.
+
+MULTILIB_OPTIONS =
+MULTILIB_DIRNAMES =
+MULTILIB_EXCEPTIONS =
+MULTILIB_MATCHES =
+MULTILIB_REUSE =
+
+# We have the following hierachy:
+# ISA: A32 (.) or T32 (thumb)
+# Architecture: ARMv7-A (v7-a), ARMv7VE (v7ve), or ARMv8-A (v8-a).
+# FPU: VFPv3-D16 (fpv3), NEONv1 (simdv1), VFPv4-D16 (fpv4),
+# NEON-VFPV4 (simdvfpv4), NEON for ARMv8 (simdv8), or None (.).
+# Float-abi: Soft (.), softfp (softfp), or hard (hardfp).
+
+# We use the option -mcpu=cortex-a7 because we do not yet have march=armv7ve
+# or march=armv7a+virt as a command line option for the compiler.
+MULTILIB_OPTIONS += mthumb
+MULTILIB_DIRNAMES += thumb
+
+MULTILIB_OPTIONS += march=armv7-a/mcpu=cortex-a7/march=armv8-a
+MULTILIB_DIRNAMES += v7-a v7ve v8-a
+
+MULTILIB_OPTIONS +=
mfpu=vfpv3-d16/mfpu=neon/mfpu=vfpv4-d16/mfpu=neon-vfpv4/mfpu=neon-fp-armv8
+MULTILIB_DIRNAMES += fpv3 simdv1 fpv4 simdvfpv4 simdv8
+
+MULTILIB_OPTIONS += mfloat-abi=softfp/mfloat-abi=hard
+MULTILIB_DIRNAMES += softfp hard
+
+# We don't build no-float libraries with an FPU.
+MULTILIB_EXCEPTIONS += *mfpu=vfpv3-d16
+MULTILIB_EXCEPTIONS += *mfpu=neon
+MULTILIB_EXCEPTIONS += *mfpu=vfpv4-d16
+MULTILIB_EXCEPTIONS += *mfpu=neon-vfpv4
+MULTILIB_EXCEPTIONS += *mfpu=neon-fp-armv8
+
+# We don't build libraries requiring an FPU at the CPU/Arch/ISA level.
+MULTILIB_EXCEPTIONS += mfloat-abi=*
+MULTILIB_EXCEPTIONS += mfpu=*
+MULTILIB_EXCEPTIONS += mthumb/mfloat-abi=*
+MULTILIB_EXCEPTIONS += mthumb/mfpu=*
+MULTILIB_EXCEPTIONS += *march=armv7-a/mfloat-abi=*
+MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/mfloat-abi=*
+MULTILIB_EXCEPTIONS += *march=armv8-a/mfloat-abi=*
+
+# Ensure the correct FPU variants apply to the correct base architectures.
+MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/*mfpu=vfpv3-d16*
+MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/*mfpu=neon/*
+MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=vfpv3-d16*
+MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=neon/*
+MULTILIB_EXCEPTIONS += *march=armv7-a/*mfpu=vfpv4-d16*
+MULTILIB_EXCEPTIONS += *march=armv7-a/*mfpu=neon-vfpv4*
+MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=vfpv4-d16*
+MULTILIB_EXCEPTIONS += *march=armv8-a/*mfpu=neon-vfpv4*
+MULTILIB_EXCEPTIONS += *march=armv7-a/*mfpu=neon-fp-armv8*
+MULTILIB_EXCEPTIONS += *mcpu=cortex-a7/*mfpu=neon-fp-armv8*
+
+# CPU Matches
+MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a8
+MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a9
+MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a5
+MULTILIB_MATCHES += mcpu?cortex-a7=mcpu?cortex-a15
+MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a53
+
+# FPU matches
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16-d16
+MULTILIB_MATCHES += mfpu?vfpv4-d16=mfpu?vfpv4
+MULTILIB_MATCHES += mfpu?neon-fp-armv8=mfpu?crypto-neon-fp-armv8
+
+
+# Map all requests for vfpv3 with a later CPU to vfpv3-d16 v7-a.
+# So if new CPUs are added above at the newer architecture levels,
+# do something to map them below here.
+# We take the approach of mapping down to v7-a regardless of what
+# the fp option is if the integer architecture brings things down.
+# This applies to any similar combination at the v7ve and v8-a arch
+# levels.
+
+MULTILIB_REUSE +=
march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.hard
+MULTILIB_REUSE +=
march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.softfp
+MULTILIB_REUSE +=
march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.hard
+MULTILIB_REUSE +=
march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp
+MULTILIB_REUSE +=
march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard
+MULTILIB_REUSE +=
march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+MULTILIB_REUSE +=
march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.fp-armv8/mfloat-abi.hard
+MULTILIB_REUSE +=
march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.fp-armv8/mfloat-abi.softfp
+MULTILIB_REUSE +=
march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4/mfloat-abi.hard
+MULTILIB_REUSE +=
march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4/mfloat-abi.softfp
+
+
+MULTILIB_REUSE +=
march.armv7-a/mfpu.neon/mfloat-abi.hard=mcpu.cortex-a7/mfpu.neon/mfloat-abi.hard
+MULTILIB_REUSE +=
march.armv7-a/mfpu.neon/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.neon/mfloat-abi.softfp
+MULTILIB_REUSE +=
march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv8-a/mfpu.neon/mfloat-abi.hard
+MULTILIB_REUSE +=
march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv8-a/mfpu.neon/mfloat-abi.softfp
+MULTILIB_REUSE +=
march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.hard
+MULTILIB_REUSE +=
march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.softfp
+MULTILIB_REUSE +=
march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.hard
+MULTILIB_REUSE +=
march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp
+
+
+MULTILIB_REUSE +=
mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.hard
+MULTILIB_REUSE +=
mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.softfp
+MULTILIB_REUSE +=
mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4/mfloat-abi.hard
+MULTILIB_REUSE +=
mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4/mfloat-abi.softfp
+MULTILIB_REUSE +=
mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard
+MULTILIB_REUSE +=
mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+
+
+MULTILIB_REUSE +=
mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.hard
+MULTILIB_REUSE +=
mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.softfp
+MULTILIB_REUSE +=
mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.hard
+MULTILIB_REUSE +=
mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.softfp
+
+
+
+# And again for mthumb.
+
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.vfpv3-d16/mfloat-abi.softfp
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.fp-armv8/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.fp-armv8/mfloat-abi.softfp
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4/mfloat-abi.softfp
+
+
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.neon/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.neon/mfloat-abi.softfp
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.neon/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.neon/mfloat-abi.softfp
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.softfp
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp
+
+
+MULTILIB_REUSE +=
mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.fp-armv8/mfloat-abi.softfp
+MULTILIB_REUSE +=
mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4/mfloat-abi.softfp
+MULTILIB_REUSE +=
mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/mcpu.cortex-a7/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp
+
+
+MULTILIB_REUSE +=
mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.softfp
+MULTILIB_REUSE +=
mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.hard=mthumb/mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.hard
+MULTILIB_REUSE +=
mthumb/mcpu.cortex-a7/mfpu.neon-vfpv4/mfloat-abi.softfp=mthumb/mcpu.cortex-a7/mfpu.neon-fp-armv8/mfloat-abi.softfp
