++---
1 file changed, 76 insertions(+), 88 deletions(-)
Please add a test case.
--
Michael Eager
On 10/23/23 11:37, Frager, Neal wrote:
Le 23 oct. 2023 à 18:40, Michael Eager a écrit :
On 10/22/23 22:48, Neal Frager wrote:
There is a microblaze cpu version 10.0 included in versal. If the
minor version is only a single digit, then the version comparison
will fail as version 10.0 will
+---
1 file changed, 76 insertions(+), 88 deletions(-)
Please add a test case.
--
Michael Eager
Hi Michael,
Would you mind helping me understand how to make a gcc test case for this patch?
This patch does not change the resulting binaries of a microblaze gcc build.
The ou
target/microblaze/isa/vanilla.c | 2 +-
gcc/testsuite/gcc.target/microblaze/microblaze.exp | 2 +-
20 files changed, 20 insertions(+), 20 deletions(-)
Only two test cases actually test this fix.
Please add a ChangeLog update for these changes.
--
Michael Eager
On 10/26/23 13:37, Neal Frager wrote:
The MICROBLAZE_VERSION_COMPARE was incorrectly using strcasecmp
instead of strverscmp to check the mcpu version against feature
options. By simply changing the define to use strverscmp,
the new version 10.0 is treated correctly as a higher version
than previ
cpu=v6.00.a" } */
+/* { dg-options "-O3 -mcpu=v10.0" } */
volatile int m1, m2, m3;
volatile long l1, l2;
diff --git a/gcc/testsuite/gcc.target/microblaze/microblaze.exp
b/gcc/testsuite/gcc.target/microblaze/microblaze.exp
index 1c7b0e23353..33979ae5e42 100644
--- a/gcc/testsuite/gcc.target/microblaze/microblaze.exp
+++ b/gcc/testsuite/gcc.target/microblaze/microblaze.exp
@@ -49,7 +49,7 @@ dg-runtest [lsort [glob -nocomplain
$srcdir/$subdir/isa/*.\[cSi\]]] \
${default_c_flags} ""
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/others/*.\[cSi\]]] \
-"" "-mcpu=v6.00.a"
+"" "-mcpu=v10.0"
# All done.
--
Michael Eager
roblaze.exp | 2 +-
22 files changed, 46 insertions(+), 20 deletions(-)
Committed.
--
Michael Eager
ired manual editing, were
marked to be added. I'll add the other files.
--
Michael Eager
a.c | 2 +-
.../gcc.target/microblaze/microblaze.exp | 2 +-
22 files changed, 46 insertions(+), 20 deletions(-)
Committed.
Did you commit this patch? I only see the ChangeLog files have been
updated by your commit.
Am I missing something?
Updated.
--
Michael Eager
x27;m receiving a "service not enabled" error when I push.
** Can someone apply this patch while I resolve this issue?
--
Michael EagerFrom a0fd2e9baa51e85f61cebd6e78bef8b5c55199b5 Mon Sep 17 00:00:00 2001
From: Michael Eager
Date: Thu, 20 Oct 2022 09:33:13 -0700
Subject: [PATCH] Fix uniniti
x27;m receiving a "service not enabled" error when I push.
** Can someone apply this patch while I resolve this issue?
--
Michael EagerFrom a0fd2e9baa51e85f61cebd6e78bef8b5c55199b5 Mon Sep 17 00:00:00 2001
From: Michael Eager
Date: Thu, 20 Oct 2022 09:33:13 -0700
Subject: [PATCH] Fix uniniti
The code
generated before applying the patch is
addik r4,r0,0x
addik r5,r0,0xf000 #li => la
Can you provide a test case which fails without the patch but passes
with the patch?
--
Michael Eager
-#define FLOAT_TYPE_SIZE 32
-#define DOUBLE_TYPE_SIZE64
-#define LONG_DOUBLE_TYPE_SIZE 64
#define POINTER_SIZE32
#define PARM_BOUNDARY 32
#define FUNCTION_BOUNDARY 32
--
Michael Eager
On 10/25/2012 06:49 AM, Ralf Corsepius wrote:
Hi,
And another RTEMS-patch, I'd like to apply to GCC trunk and GCC-4_7-branch:
Adding
microblaze*-rtems* target.
This patch has been in use as part of the RTEMS gcc-4.7 patches for ca. 1/2 a
year.
OK to apply.
--
Michael Eager
, \
+ 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1 \
}
#define GP_REG_FIRST0
Committed revision 232682.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA
On 12/07/2015 09:39 AM, Ajit Kumar Agarwal wrote:
-Original Message-
From: Michael Eager [mailto:ea...@eagerm.com]
Sent: Thursday, December 03, 2015 7:27 PM
To: Ajit Kumar Agarwal; GCC Patches
Cc: Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; Nagaraju Mekala
Subject: Re
en_reg_rtx (SImode);
+ rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
nd http://gcc.gnu.org/ml/gcc/2013-11/msg00545.html), though Joern
isn't fond of the idea (cf.
http://gcc.gnu.org/ml/gcc/2013-11/msg00528.html). So I'd quite like to
see a discussion about this.
I have no objections to adding the two targets.
I think that microblaze-rtems will duplicate
OK.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 12/06/13 19:13, Ralf Corsepius wrote:
Hi,
I intend to the patch below to gcc-trunk and 4.8-branch:
It's a partial sync of the microblaze-rtems* section in gcc/config.gcc with
microblaze*-*-elf's:
Add TARGET_BIG_ENDIAN_DEFAULT-switch for microblaze*-*-rtems*.
Ralf
OK.
--
Mic
-64. Ok to commit?
OK for MicroBlaze.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
Installed on the trunk.
OK.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 10/15/2015 12:00 PM, Szabolcs Nagy wrote:
On 06/05/15 12:25, Szabolcs Nagy wrote:
On 29/04/15 14:51, Szabolcs Nagy wrote:
On 29/04/15 14:17, Michael Eager wrote:
On 04/27/2015 07:35 AM, Szabolcs Nagy wrote:
On 20/04/15 19:54, Szabolcs Nagy wrote:
Set up dynamic linker name for microblaze
re_16? What are all these conditions testing?
+ loop_optimizer_finalize();
Space before parens.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
; (regno == MB_ABI_ASM_TEMP_REGNUM
|| regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM)))
return 1;
Attached is the patch.
Thanks
Nagaraju
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306
b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
@@ -5,4 +5,4 @@ void trap ()
__builtin_trap ();
}
-/* { dg-final { scan-assembler "brki\tr0,-1" } } */
\ No newline at end of file
+/* { dg-final { scan-assembler "bri\t0" } } */
Attached is the patch.
Thanks
Nagaraju
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306
long.
OK.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306
instead of .text or any other expected section.
Which results in assembly failures including operations with symbols
across different segments.
Can you give me an example where this causes a problem?
--
Michael Eagerea...@eagerm.com
1960 Park Blvd., Palo Alto, CA 94306
MicroBlaze-specific tests.
--
Michael Eagerea...@eagerm.com
1960 Park Blvd., Palo Alto, CA 94306
-submit patches separately after re-running the whole GCC
Test suite and re-checking code conventions.
For sending to gdb-patches, it was a conflict from my side as
actually I thought it is also for binutils.
On Tue, Feb 27, 2018 at 2:07 AM, Michael Eager mailto:ea..
On 03/12/18 06:19, Andrew Sadek wrote:
On Mon, Mar 5, 2018 at 9:21 PM, Michael Eager <mailto:ea...@eagerm.com>> wrote:
On 03/02/2018 08:12 AM, Andrew Sadek wrote:
Hello Michael,
I tried running the whole GCC test suite on the current head
(without
same regression test with the new PIC options. Ideally
you should have the same results.
On Mon, Mar 12, 2018 at 4:30 PM, Michael Eager <mailto:ea...@eagerm.com>> wrote:
On 03/12/18 06:19, Andrew Sadek wrote:
On Mon, Mar 5, 2018 at 9:21 PM, Michael Eager mailto:ea...@e
ent,
anyway I shall give it a try and send you the results with the new options.
There should be no target dependencies in the generic GCC tests.
Different instruction patterns which generate the correct results should
not be a problem.
--
Michael Eagerea...@eagerm.com
1960 Park Blvd., Palo Alto, CA 94306
' already fails with -fPIE, and for the
others in microblaze,
expectation is r0 or r13 as a base register which is not the case
here 'r20', and these tests also fails with -fPIE.
Moreover, the test cases that failed due 'unresolved
GLOBAL_OFFSET_TABLE'
options.
This is not required -- your patch appears to work OK. Normally,
the new PIC Data options would not be used when running the test
suite, so the tests would not fail. It's just nice to have the
test suite updated when new options are added.
On 03/19/2018 01:07 PM, Michael Eager wrote
Also check the { dg-skip-if } directive.
https://gcc.gnu.org/onlinedocs/gccint/Directives.html
On 03/19/2018 06:14 PM, Michael Eager wrote:
Hi Andrew --
Please take a look at the test case description:
https://gcc.gnu.org/wiki/HowToPrepareATestcase
and see if you can do one of the following
again.
I m actually running the 'check_GNU_Style' in contrib folder,, is this the
correct way ? Is it enough ?
Andrew
On Tue, Mar 20, 2018, 03:30 Michael Eager wrote:
Also check the { dg-skip-if } directive.
https://gcc.gnu.org/onlinedocs/gccint/Directives.html
On 03/19/2018 06:14 P
flag for either generating ADDR_DIF_VEC table
+or ADDR_VEC table for jumps in case of -fPIC.
Explicitly state what true or false means.
target.def:
+(generate_pic_addr_diff_vec,
Explicitly state what true or false means.
targhooks.c:
+bool
+default_generate_pic_addr_diff_vec (void)
+{
+ return true;
+}
This doesn't appear to match the description in target.def.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306
On 04/19/2018 03:43 AM, Andrew Sadek wrote:
On Wed, Apr 18, 2018 at 6:57 PM, Michael Eager wrote:
Hi Andrew --
Check indents in the following files:
(Make sure that your tabs are set at 8 chars.)
--- gcc/config/microblaze/microblaze.c
--- gcc/config/microblaze/microblaze.md
I have re-run
AIL: gcc.dg/uninit-19.c (test for excess errors) => already fails
with -fPIE/-fPIC as mentioned before.
On Thu, May 3, 2018 at 7:13 PM, Andrew Sadek <mailto:andrew.sadek...@gmail.com>> wrote:
--resend Michael's reply
On Mon, Apr 30, 2018 at 1:19 PM, Michael Eager mai
c:109
0x983041 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
/store/Xilinx/repo/fsf/gcc/gcc/rtl-error.c:117
0x9539cd extract_insn(rtx_def*)
/store/Xilinx/repo/fsf/gcc/gcc/recog.c:2204
0x7a5b59 instantiate_virtual_regs_in_insn
/store/Xilinx/repo/fsf/gcc/
L2,%L1\;rsubc\t%M0,%M2,%M1"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set_attr "length""8")])
Committed revision 213913.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
(microblaze_expand_divide): Likewise for locals "jump", "cjump",
"insn". Strengthen locals "div_label", "div_end_label" from rtx
to rtx_code_label *.
OK
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 08/13/14 18:35, Chen Gang wrote:
Firstly, thank you very much for spending your time resource on the
related 2 patches.
You're welcome.
On 8/13/14 23:10, Michael Eager wrote:
On 07/06/14 03:26, Chen Gang wrote:
* microblaze/mocroblaze.md (call_value_intern): Use 'SI&#
.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
. That's been there since 2009, but never noticed.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
(x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
+ iter.skip_subrtxes ();
+}
+ return false;
}
bool
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
e simulator, which microblaze-sim cannot do. QEMU models an
entire processor and can boot a Linux image.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 02/10/14 17:55, Michael Eager wrote:
On 11/25/13 23:54, David Holsgrove wrote:
Added the lwr/swr instructions pattern.
lwr and swr instructions will load/store the data with opposite endianness.
Changelog
2013-11-26 Nagaraju Mekala
* gcc/config/microblaze/microblaze.md: Add movsi4_rev
On 02/13/14 21:48, David Holsgrove wrote:
Hi Michael,
-Original Message-
From: Michael Eager [mailto:ea...@eagerm.com]
Sent: Sunday, 9 February 2014 2:58 am
To: David Holsgrove; gcc-patches@gcc.gnu.org
Cc: Edgar Iglesias; John Williams; Vidhumouli Hunsigida; Nagaraju Mekala
Subject: Re
-function-on-line): Add
MicroBlaze specific pattern.
Committed revision 212189.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
(MUSL_DYNAMIC_LINKER): Define.
(DYNAMIC_LINKER): Change.
Are you building with both glibc and musl to verify these patches?
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 03/04/2015 08:20 AM, Michael Eager wrote:
On 03/04/15 03:53, Ajit Kumar Agarwal wrote:
-Original Message-
From: Michael Eager [mailto:ea...@eagerm.com]
Sent: Thursday, February 26, 2015 4:33 AM
To: Ajit Kumar Agarwal; GCC Patches
Cc: Vinod Kathail; Shail Aditya Gupta; Vidhumouli
On 03/06/2015 07:33 AM, Michael Eager wrote:
On 03/05/15 21:12, Ajit Kumar Agarwal wrote:
Changes are incorporated. Please find the log of the updated patch.
commit 91f275c144165320850ddf18e3a1e059a66c
Author: Ajit Kumar Agarwal
Date: Fri Mar 6 09:55:11 2015 +0530
[Patch
On 12/01/14 14:02, Cary Coutant wrote:
[+cc Michael Eager]
Rather than having to lobby to keep it unchanged because we jumped the gun,
can we lobby to get the number assigned in the near future rather than in
the potentially far future? That feels more cooperative to me :-)
Would that make
(condition, label1));
+}
+ else if (code == NE)
+{
+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, cmp_op1));
+ condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
+ emit_jump_insn (gen_condjump (condition, label1));
+}
+ else
+{
...
--
Michael Eagerea
/microblaze.md (peephole2): New.
+emit_insn (gen_cstoresf4 (comp_reg, operands[2],
+ gen_rtx_REG(SFmode,REGNO(cmp_op0)),
+ gen_rtx_REG(SFmode,REGNO(cmp_op1;
Spaces before left parens and after comma in last two lines.
--
Michael
On 03/04/15 03:53, Ajit Kumar Agarwal wrote:
-Original Message-
From: Michael Eager [mailto:ea...@eagerm.com]
Sent: Thursday, February 26, 2015 4:33 AM
To: Ajit Kumar Agarwal; GCC Patches
Cc: Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; Nagaraju Mekala
Subject: Re: [Patch
/microblaze.c
(microblaze_expand_conditional_branch_reg): New.
* config/microblaze/microblaze-protos.h
(microblaze_expand_conditional_branch_reg): New prototype.
Signed-off-by:Ajit Agarwal ajit...@xilinx.com
Thanks & Regards
Ajit
OK.
--
Michael Eager
-(define_expand "movmemsi"
+(define_expand "cpymemsi"
[(parallel [(set (match_operand:BLK 0 "general_operand")
(match_operand:BLK 1 "general_operand"))
(use (match_operand:SI 2 ""))
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306
int length;
int wic_addr0 = 128 * 4;
- int wic_addr1 = 128 * 4;
int first_addr = INSN_ADDRESSES (INSN_UID (first));
@@ -3693,7 +3694,7 @@ static void
insert_wic (void)
{
rtx_insn *insn;
- int i, j;
+ int i;
basic_block bb, prev = 0;
rtx branch_target = 0;
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
From https://gcc.gnu.org/ml/gcc/2017-05/msg00221.html:
On 05/27/2017 09:09 AM, Michael Eager wrote:
On 05/27/2017 01:51 AM, Waldemar Brodkorb wrote:
Hi,
Buildroot and OpenADK have samples to create a Linux system to be
bootup in Qemu system emulation for microblaze architecture.
With gcc 6.3
nd accepting the patch into GCC would not involve any transfer of
ownership.)
Does anyone have any authority on this copyright issue?
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 01/06/2017 01:34 AM, Edgar E. Iglesias wrote:
On Thu, Jan 05, 2017 at 05:58:01PM +, Joseph Myers wrote:
On Thu, 5 Jan 2017, Michael Eager wrote:
On multiple occasions, I have asked Xilinx to submit patches such
as this one directly to the GCC/Binutils projects (assuming that
nk that this is a glibc problem.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
is branch will be used to update MicroBlaze support from gcc-4.1.2 to
- to the head. It is maintained by Michael Eager
- <mailto:ea...@eagercon.com";>ea...@eagercon.com>.
-
mpx
The goal of this branch is to support Intel MPX technology
(href="https://software.intel.com/
{
- if (REGNO (operands[0]) != REGNO (operands[1]))
- emit_insn (gen_movsi (operands[0], operands[1]));
+ emit_insn (gen_movsi (operands[0], operands[1]));
return 1;
}
Why generate an unnecessary NOP?
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo A
ou could have changed this line to
if (operands[2] == const0_rtx)
as well.
And this would not change the generated code.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 02/21/2017 12:25 PM, Segher Boessenkool wrote:
On Tue, Feb 21, 2017 at 12:08:34PM -0800, Michael Eager wrote:
- /* Shift by zero -- copy regs if necessary. */
+ /* Shift by zero -- copy regs. */
if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2])
On 02/26/2017 01:38 AM, Gerald Pfeifer wrote:
On Mon, 13 Feb 2017, Michael Eager wrote:
The microblaze branch has been merged into the gcc mainline.
Thanks for the patch, Michael. I noticed you had not committed
it, so I just did that for you (with a little tweak in how we
refer to GCC 4.2.1
2017-03-09 Michael Eager
Correct failures with --enable-checking=yes,rtl.
* config/microblaze/microblaze.c (microblaze_expand_shift):
Replace GET_CODE test with CONST_INT_P and INTVAL test with
test for const0_rtx.
* config/microblaze/microblaze.md
On 03/09/2017 03:35 PM, Segher Boessenkool wrote:
Hi!
On Thu, Mar 09, 2017 at 10:18:43AM -0800, Michael Eager wrote:
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -3323,10 +3323,10 @@ microblaze_expand_shift (rtx operands[])
|| (GET_CODE
;
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
#if TARGET_BIG_ENDIAN_DEFAULT == 0 /* LE */
#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:;:el}"
best regards
Waldemar
OK to apply.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 10/31/2016 08:04 AM, Jeff Law wrote:
On 10/28/2016 03:30 PM, Michael Eager wrote:
On 10/28/2016 11:14 AM, Waldemar Brodkorb wrote:
Hi,
uClibc-ng can be used for Microblaze architecture.
It is regulary tested with qemu-system-microblaze in little and
big endian mode.
2016-10-28 Waldemar
ssion of how to use these
features.
-Sandra
OK.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
problem you are working on has changed from the mb-gcc issue,
change the subject. Otherwise, keep up the good work.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
figuration
options and executes runtest directly. This uses a MicroBlaze processor
simulator called vpexec which was included with an older version of
Xilinx's EDK. Xilinx no longer supports vpexec.
You can use a hardware target board to test microblaze-gcc,
or a different simulator such as QEM
On 09/14/14 21:19, Chen Gang wrote:
On 9/15/14 11:03, Michael Eager wrote:
On 09/14/14 00:51, Chen Gang wrote:
Hello maintainers:
I also find some warnings during compiling microblaze, I also shall try
to fix them, but excuse me, I am not quite familiar the testsuite for
microblaze, could
On 09/15/14 15:53, Chen Gang wrote:
On 09/15/2014 11:30 PM, Michael Eager wrote:
Configuring DejaGNU for cross-target testing requires creating a configuration
file describing the target board.
OK, thank you very much. And could you share your configuration file,
which I can reference to
97
# of unresolved testcases 16570
# of unsupported tests1854
/upstream/build-gcc/gcc/xgcc version 5.0.0 20140920 (experimental) (GCC)
Look at gcc.sum and gcc.log to find out what is causing the large number of
unexpected failures. A large number of unresolved test ca
environment.
If you are testing in a Linux environment, the tool chain you uses
should provide a default linker script which matches your hardware's
memory layout. You should not need to provide a separate linker script.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
aze-gchen-linux-ld: warning: cannot find
entry symbol _start; defaulting to 1180
Generally, you should use "gcc" to link programs, not "ld". gcc is
a driver which will select the appropriate libraries and support routines
(such as crt0.o, which contains
On 09/21/14 21:10, Chen Gang wrote:
On 9/22/14 2:09, Michael Eager wrote:
Generally, you should use "gcc" to link programs, not "ld". gcc is
a driver which will select the appropriate libraries and support routines
(such as crt0.o, which contains _start) and pass them
On 09/21/14 20:55, Chen Gang wrote:
On 9/22/14 2:03, Michael Eager wrote:
On 09/20/14 23:24, Chen Gang wrote:
And it seems, we also need 'LinkScr.ld' for ldscript, could you share it
to me, thanks.
set_board_info ldscript "-T/home/eager/Xilinx/dg/microblaze_0/LinkSc
since I have
no enough time resource on glibc, at present).
OK with me.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 09/24/14 09:23, Chen Gang wrote:
On 09/24/2014 11:37 PM, Mike Stump wrote:
On Sep 24, 2014, at 8:28 AM, Michael Eager wrote:
After check the current result log, I find many remote target test
related sentences, do we have to process it?
e.g. "Download to microblaze-xilinx-gdb f
On 09/25/14 07:03, Chen Gang wrote:
Need use VOID instead of SI, or when real VOIDmode comes, it does not
match SImode, so cause issue. This patch can fix this issue and pass
testsuite.
Did you forget to attach the patch?
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA
On 09/25/14 10:38, Michael Eager wrote:
On 09/25/14 07:03, Chen Gang wrote:
Need use VOID instead of SI, or when real VOIDmode comes, it does not
match SImode, so cause issue. This patch can fix this issue and pass
testsuite.
Did you forget to attach the patch?
Never mind. My eyes were
efine_insn "call_internal1"
- [(call (mem (match_operand:SI 0 "call_insn_simple_operand" "ri"))
+ [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
(match_operand:SI 1 "" "i"))
(clobber (reg:SI R_SR))]
: New test.
Committed revision 215684.
Thanks for adding the test case.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
));
(actually, in output_operand() downstream from this statement) while compiling
c++98/strstream.cc, with an error that the "%l" operand was not a label.
This is the first occasion when this routine is called.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 9430
On 07/14/13 21:37, David Holsgrove wrote:
Hi Michael,
-Original Message-
From: Michael Eager [mailto:ea...@eagerm.com]
Sent: Saturday, 13 July 2013 9:33 am
To: David Holsgrove
Cc: gcc-patches@gcc.gnu.org; Edgar Iglesias; John Williams; Vinod Kathail;
Vidhumouli Hunsigida; Nagaraju
On 03/18/13 05:48, David Holsgrove wrote:
Changelog
2013-03-18 David Holsgrove
* gcc/config/microblaze/microblaze.c (microblaze_expand_prologue):
Add check for flag_stack_usage to handle -fstack-usage support
Signed-off-by: David Holsgrove
Applied revision 201035.
--
Michael Eager
On 07/18/13 16:25, David Holsgrove wrote:
On 19 July 2013 02:42, Michael Eager wrote:
On 03/18/13 05:48, David Holsgrove wrote:
Changelog
2013-03-18 David Holsgrove
* gcc/config/microblaze/microblaze.c (microblaze_expand_prologue):
Add check for flag_stack_usage to handle -fstack
On 07/14/13 21:37, David Holsgrove wrote:
Hi Michael,
-Original Message-
From: Michael Eager [mailto:ea...@eagerm.com]
Sent: Saturday, 13 July 2013 9:33 am
To: David Holsgrove
Cc: gcc-patches@gcc.gnu.org; Edgar Iglesias; John Williams; Vinod Kathail;
Vidhumouli Hunsigida; Nagaraju
se send an updated ChangeLog when it is different from the
original.
ChangeLog:
2013-07-23 David Holsgrove
* config/microblaze/microblaze.c (microblaze_expand_prologue):
Rename flag_stack_usage to flag_stack_usage_info.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Pal
d: Add memory_contraint
'Q' which is a single register.
thanks,
David
Committed revision 201185.
ChangeLog corrected: revision 201200
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 07/23/13 16:23, David Holsgrove wrote:
On 24 July 2013 07:10, Michael Eager wrote:
On 07/14/13 21:37, David Holsgrove wrote:
Hi Michael,
-Original Message-
From: Michael Eager [mailto:ea...@eagerm.com]
Sent: Saturday, 13 July 2013 9:33 am
To: David Holsgrove
Cc: gcc-patches
means that no other change to microblaze is
needed and the question about elfos.h is moot.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
l-reorder
Target RejectNegative Mask(REORDER)
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
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