[PATCH] RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483]

. Otherwise, the tail elements of next will be polluted. DEF_SEW_LMUL_RULE (ge_sew, ratio_and_ge_sew, ratio_and_ge_sew, max_sew_overlap_and_next_ratio_valid_for_prev_sew_p, always_false, use_max_sew_and_lmul_with_next_ratio) Passed the rv64gcv full regression test. Signed-off-by: Li Xu

Re: Re: [PATCH 1/2 v3] Match: Simplify unsigned scalar sat_sub(x, 1) to (x - x != 0)

> -原始邮件-发件人:"Andrew Pinski" 发送时间:2024-10-24 10:23:01 > (星期四)收件人:"Li Xu" 抄送:gcc-patches@gcc.gnu.org, > kito.ch...@gmail.com, richard.guent...@gmail.com, tamar.christ...@arm.com, > juzhe.zh...@rivai.ai, pan2...@intel.com, jeffreya...@gmail.com, > r

[PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form1

; i++) \ out[i] = (T)IMM >= in[i] ? (T)IMM - in[i] : 0; \ } Passed the rv64gcv full regression test. Signed-off-by: Li Xu gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: add data for vec sat_sub. * gcc.target/riscv/rvv/autovec/vec_sat_arith.

[PATCH 2/2] RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IMM = -1.

; 0 \ ? sum\ : (sum ^ x) >= 0 \ ? sum \ : x < 0 ? MIN : MAX; \ } Passed the rv64gcv regression test. Signed-off-by: Li Xu gcc/testsuite/

[PATCH 1/2] Match:Support IMM=-1 for signed scalar SAT_ADD IMM form1

The rv64gcv fully regression tests. 2. The x86 bootstrap tests. 3. The x86 fully regression tests. Signed-off-by: Li Xu gcc/ChangeLog: * match.pd: Add signed scalar SAT_ADD IMM form1 with IMM=-1 matching. * tree-ssa-math-opts.cc (match_unsigned_sat

[PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4

unsigned i; \ for (i = 0; i < limit; i++) \ out[i] = in[i] > (T)IMM ? in[i] - (T)IMM : 0; \ } Passed the rv64gcv full regression test. Signed-off-by: Li Xu gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/ve

[PATCH 2/2] RISC-V: Add testcases for signed vector SAT_ADD IMM form 1

? sum \ : x < 0 ? MIN : MAX; \ }\ } Passed the rv64gcv regression test. Signed-off-by: Li Xu gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv

[PATCH 1/2] Match:Support signed vector SAT_ADD IMM form 1

tch: 1. The rv64gcv fully regression tests. 2. The x86 bootstrap tests. 3. The x86 fully regression tests. Signed-off-by: Li Xu gcc/ChangeLog: * match.pd: add singned vector SAT_ADD IMM form1 matching. --- gcc/match.pd | 10 ++ 1 file changed, 10 insertions(+) diff --git a/gc

[PATCH] RISC-V: Refine registered_functions list for rvv overloaded intrinsics.

intrinsic once. Only gcc's rfn will be added to the non_overloaded_function_table. Passed the rv64gcv regression test. Signed-off-by: Li Xu gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (function_builder::add_unique_function): Only register overloaded intrinsic

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