From: xuli <xu...@eswincomputing.com>
Form2:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
out[i] = in[i] >= (T)IMM ? in[i] - (T)IMM : 0; \
}
Form3:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
out[i] = (T)IMM > in[i] ? (T)IMM - in[i] : 0; \
}
Form4:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
out[i] = in[i] > (T)IMM ? in[i] - (T)IMM : 0; \
}
Passed the rv64gcv full regression test.
Signed-off-by: Li Xu <xu...@eswincomputing.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: add unsigned imm
vec sat_sub form2~4.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h: add data for vec
sat_sub.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u16.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u32.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u64.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u8.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u16.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u32.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u64.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u8.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u16.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u32.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u64.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u8.c: New
test.
---
.../riscv/rvv/autovec/sat/vec_sat_arith.h | 54 ++++
.../riscv/rvv/autovec/sat/vec_sat_data.h | 256 ++++++++++++++++--
.../rvv/autovec/sat/vec_sat_u_sub_imm-2-u16.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-2-u32.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-2-u64.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-2-u8.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-3-u16.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-3-u32.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-3-u64.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-3-u8.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-4-u16.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-4-u32.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-4-u64.c | 9 +
.../rvv/autovec/sat/vec_sat_u_sub_imm-4-u8.c | 9 +
.../autovec/sat/vec_sat_u_sub_imm-run-2-u16.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-2-u32.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-2-u64.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-2-u8.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-3-u16.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-3-u32.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-3-u64.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-3-u8.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-4-u16.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-4-u32.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-4-u64.c | 28 ++
.../autovec/sat/vec_sat_u_sub_imm-run-4-u8.c | 28 ++
26 files changed, 738 insertions(+), 16 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
index cb419553926..7db892cc2e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
@@ -480,12 +480,66 @@ vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in,
unsigned limit) \
#define DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, IMM) \
DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM)
+#define DEF_VEC_SAT_U_SUB_IMM_FMT_2(T, IMM) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ out[i] = in[i] >= (T)IMM ? in[i] - (T)IMM : 0; \
+}
+
+#define DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP(T, IMM) \
+ DEF_VEC_SAT_U_SUB_IMM_FMT_2(T, IMM)
+
+#define DEF_VEC_SAT_U_SUB_IMM_FMT_3(T, IMM) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ out[i] = (T)IMM > in[i] ? (T)IMM - in[i] : 0; \
+}
+
+#define DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP(T, IMM) \
+ DEF_VEC_SAT_U_SUB_IMM_FMT_3(T, IMM)
+
+#define DEF_VEC_SAT_U_SUB_IMM_FMT_4(T, IMM) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ out[i] = in[i] > (T)IMM ? in[i] - (T)IMM : 0; \
+}
+
+#define DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP(T, IMM) \
+ DEF_VEC_SAT_U_SUB_IMM_FMT_4(T, IMM)
+
#define RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_1(out, op_1, N); \
VALIDATE_RESULT (out, expect, N)
#define RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N)
+#define RUN_VEC_SAT_U_SUB_IMM_FMT_2(T, out, op_1, expect, IMM, N) \
+ vec_sat_u_sub_imm##IMM##_##T##_fmt_2(out, op_1, N); \
+ VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_U_SUB_IMM_FMT_2_WRAP(T, out, op_1, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_2(T, out, op_1, expect, IMM, N)
+
+#define RUN_VEC_SAT_U_SUB_IMM_FMT_3(T, out, op_1, expect, IMM, N) \
+ vec_sat_u_sub_imm##IMM##_##T##_fmt_3(out, op_1, N); \
+ VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_U_SUB_IMM_FMT_3_WRAP(T, out, op_1, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_3(T, out, op_1, expect, IMM, N)
+
+#define RUN_VEC_SAT_U_SUB_IMM_FMT_4(T, out, op_1, expect, IMM, N) \
+ vec_sat_u_sub_imm##IMM##_##T##_fmt_4(out, op_1, N); \
+ VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_U_SUB_IMM_FMT_4_WRAP(T, out, op_1, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_4(T, out, op_1, expect, IMM, N)
+
#define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h
index 3db7a5c7d28..ec4d64cc100 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h
@@ -282,7 +282,7 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_add_imm)[][2][N] =
uint8_t TEST_UNARY_DATA(uint8_t, sat_u_sub_imm)[][2][N] =
{
- { /* For sub imm 0 */
+ { /* For sub form1 & form3 imm 0 */
{
0, 1, 5, 255,
0, 1, 5, 255,
@@ -296,7 +296,7 @@ uint8_t TEST_UNARY_DATA(uint8_t, sat_u_sub_imm)[][2][N] =
0, 0, 0, 0,
},
},
- { /* For sub imm 1 */
+ { /* For sub form1 & form3 imm 1 */
{
0, 1, 2, 8,
0, 1, 2, 8,
@@ -310,7 +310,7 @@ uint8_t TEST_UNARY_DATA(uint8_t, sat_u_sub_imm)[][2][N] =
1, 0, 0, 0,
},
},
- { /* For sub imm 254 */
+ { /* For sub form1 & form3 imm 254 */
{
0, 1, 254, 255,
0, 1, 254, 255,
@@ -324,7 +324,7 @@ uint8_t TEST_UNARY_DATA(uint8_t, sat_u_sub_imm)[][2][N] =
254, 253, 0, 0,
},
},
- { /* For sub imm 255 */
+ { /* For sub form1 & form3 imm 255 */
{
0, 1, 5, 255,
0, 1, 5, 255,
@@ -338,11 +338,67 @@ uint8_t TEST_UNARY_DATA(uint8_t, sat_u_sub_imm)[][2][N] =
255, 254, 250, 0,
},
},
+ { /* For sub form2 & form4 imm 0 */
+ {
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ },
+ {
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ },
+ },
+ { /* For sub form2 & form4 imm 1 */
+ {
+ 0, 1, 2, 8,
+ 0, 1, 2, 8,
+ 0, 1, 2, 8,
+ 0, 1, 2, 8,
+ },
+ {
+ 0, 0, 1, 7,
+ 0, 0, 1, 7,
+ 0, 0, 1, 7,
+ 0, 0, 1, 7,
+ },
+ },
+ { /* For sub form2 & form4 imm 254 */
+ {
+ 0, 1, 254, 255,
+ 0, 1, 254, 255,
+ 0, 1, 254, 255,
+ 0, 1, 254, 255,
+ },
+ {
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ },
+ },
+ { /* For sub form2 & form4 imm 255 */
+ {
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
};
uint16_t TEST_UNARY_DATA(uint16_t, sat_u_sub_imm)[][2][N] =
{
- { /* For sub imm 0 */
+ { /* For sub form1 & form3 imm 0 */
{
0, 1, 5, 65535,
0, 1, 5, 65535,
@@ -356,7 +412,7 @@ uint16_t TEST_UNARY_DATA(uint16_t, sat_u_sub_imm)[][2][N] =
0, 0, 0, 0,
},
},
- { /* For sub imm 1 */
+ { /* For sub form1 & form3 imm 1 */
{
0, 1, 5, 8,
0, 1, 5, 8,
@@ -370,7 +426,7 @@ uint16_t TEST_UNARY_DATA(uint16_t, sat_u_sub_imm)[][2][N] =
1, 0, 0, 0,
},
},
- { /* For sub imm 65534 */
+ { /* For sub form1 & form3 imm 65534 */
{
0, 1, 65534, 65535,
0, 1, 65534, 65535,
@@ -384,7 +440,7 @@ uint16_t TEST_UNARY_DATA(uint16_t, sat_u_sub_imm)[][2][N] =
65534, 65533, 0, 0,
},
},
- { /* For sub imm 65535 */
+ { /* For sub form1 & form3 imm 65535 */
{
0, 1, 65534, 65535,
0, 1, 65534, 65535,
@@ -398,11 +454,67 @@ uint16_t TEST_UNARY_DATA(uint16_t, sat_u_sub_imm)[][2][N]
=
65535, 65534, 1, 0,
},
},
+ { /* For sub form2 & form4 imm 0 */
+ {
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ },
+ {
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ },
+ },
+ { /* For sub form2 & form4 imm 1 */
+ {
+ 0, 1, 5, 8,
+ 0, 1, 5, 8,
+ 0, 1, 5, 8,
+ 0, 1, 5, 8,
+ },
+ {
+ 0, 0, 4, 7,
+ 0, 0, 4, 7,
+ 0, 0, 4, 7,
+ 0, 0, 4, 7,
+ },
+ },
+ { /* For sub form2 & form4 imm 65534 */
+ {
+ 0, 1, 65534, 65535,
+ 0, 1, 65534, 65535,
+ 0, 1, 65534, 65535,
+ 0, 1, 65534, 65535,
+ },
+ {
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ },
+ },
+ { /* For sub form2 & form4 imm 65535 */
+ {
+ 0, 1, 65534, 65535,
+ 0, 1, 65534, 65535,
+ 0, 1, 65534, 65535,
+ 0, 1, 65534, 65535,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
};
uint32_t TEST_UNARY_DATA(uint32_t, sat_u_sub_imm)[][2][N] =
{
- { /* For sub imm 0 */
+ { /* For sub form1 & form3 imm 0 */
{
0, 1, 5, 4294967295,
0, 1, 5, 4294967295,
@@ -416,7 +528,7 @@ uint32_t TEST_UNARY_DATA(uint32_t, sat_u_sub_imm)[][2][N] =
0, 0, 0, 0,
},
},
- { /* For sub imm 1 */
+ { /* For sub form1 & form3 imm 1 */
{
0, 1, 5, 8,
0, 1, 5, 8,
@@ -430,7 +542,7 @@ uint32_t TEST_UNARY_DATA(uint32_t, sat_u_sub_imm)[][2][N] =
1, 0, 0, 0,
},
},
- { /* For sub imm 4294967294 */
+ { /* For sub form1 & form3 imm 4294967294 */
{
0, 1, 4294967294, 4294967295,
0, 1, 4294967294, 4294967295,
@@ -444,7 +556,7 @@ uint32_t TEST_UNARY_DATA(uint32_t, sat_u_sub_imm)[][2][N] =
4294967294, 4294967293, 0, 0,
},
},
- { /* For sub imm 4294967295 */
+ { /* For sub form1 & form3 imm 4294967295 */
{
0, 1, 4294967294, 4294967295,
0, 1, 4294967294, 4294967295,
@@ -458,11 +570,67 @@ uint32_t TEST_UNARY_DATA(uint32_t, sat_u_sub_imm)[][2][N]
=
4294967295, 4294967294, 1, 0,
},
},
+ { /* For sub form2 & form4 imm 0 */
+ {
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ },
+ {
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ },
+ },
+ { /* For sub form2 & form4 imm 1 */
+ {
+ 0, 1, 5, 8,
+ 0, 1, 5, 8,
+ 0, 1, 5, 8,
+ 0, 1, 5, 8,
+ },
+ {
+ 0, 0, 4, 7,
+ 0, 0, 4, 7,
+ 0, 0, 4, 7,
+ 0, 0, 4, 7,
+ },
+ },
+ { /* For sub form2 & form4 imm 4294967294 */
+ {
+ 0, 1, 4294967294, 4294967295,
+ 0, 1, 4294967294, 4294967295,
+ 0, 1, 4294967294, 4294967295,
+ 0, 1, 4294967294, 4294967295,
+ },
+ {
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ },
+ },
+ { /* For sub form2 & form4 imm 4294967295 */
+ {
+ 0, 1, 4294967294, 4294967295,
+ 0, 1, 4294967294, 4294967295,
+ 0, 1, 4294967294, 4294967295,
+ 0, 1, 4294967294, 4294967295,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
};
uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] =
{
- { /* For sub imm 0 */
+ { /* For sub form1 & form3 imm 0 */
{
0, 1, 5, 18446744073709551615u,
0, 1, 5, 18446744073709551615u,
@@ -476,7 +644,7 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] =
0, 0, 0, 0,
},
},
- { /* For sub imm 1 */
+ { /* For sub form1 & form3 imm 1 */
{
0, 1, 5, 8,
0, 1, 5, 8,
@@ -490,7 +658,7 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] =
1, 0, 0, 0,
},
},
- { /* For sub imm 18446744073709551614 */
+ { /* For sub form1 & form3 imm 18446744073709551614 */
{
0, 1, 18446744073709551614u, 18446744073709551615u,
0, 1, 18446744073709551614u, 18446744073709551615u,
@@ -504,7 +672,7 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] =
18446744073709551614u, 18446744073709551613u, 0, 0,
},
},
- { /* For sub imm 18446744073709551615 */
+ { /* For sub form1 & form3 imm 18446744073709551615 */
{
0, 1, 18446744073709551614u, 18446744073709551615u,
0, 1, 18446744073709551614u, 18446744073709551615u,
@@ -518,6 +686,62 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] =
18446744073709551615u, 18446744073709551614u, 1, 0,
},
},
+ { /* For sub form2 & form4 imm 0 */
+ {
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ },
+ {
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ },
+ },
+ { /* For sub form2 & form4 imm 1 */
+ {
+ 0, 1, 5, 8,
+ 0, 1, 5, 8,
+ 0, 1, 5, 8,
+ 0, 1, 5, 8,
+ },
+ {
+ 0, 0, 4, 7,
+ 0, 0, 4, 7,
+ 0, 0, 4, 7,
+ 0, 0, 4, 7,
+ },
+ },
+ { /* For sub form2 & form4 imm 18446744073709551614 */
+ {
+ 0, 1, 18446744073709551614u, 18446744073709551615u,
+ 0, 1, 18446744073709551614u, 18446744073709551615u,
+ 0, 1, 18446744073709551614u, 18446744073709551615u,
+ 0, 1, 18446744073709551614u, 18446744073709551615u,
+ },
+ {
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ 0, 0, 0, 1,
+ },
+ },
+ { /* For sub form2 & form4 imm 18446744073709551615 */
+ {
+ 0, 1, 18446744073709551614u, 18446744073709551615u,
+ 0, 1, 18446744073709551614u, 18446744073709551615u,
+ 0, 1, 18446744073709551614u, 18446744073709551615u,
+ 0, 1, 18446744073709551614u, 18446744073709551615u,
+ },
+ {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ },
+ },
};
#define TEST_BINARY_DATA_NAME(T1, T2, NAME)
test_bin_##T1##_##T2##_##NAME##_data
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u16.c
new file mode 100644
index 00000000000..7d654279c5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_2(uint16_t, 70)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u32.c
new file mode 100644
index 00000000000..cb903c49897
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_2(uint32_t, 5)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u64.c
new file mode 100644
index 00000000000..718f8505eae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u64.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_2(uint64_t, 9)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u8.c
new file mode 100644
index 00000000000..ff05fc68152
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_2(uint8_t, 10)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u16.c
new file mode 100644
index 00000000000..e9ece55d3ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_3(uint16_t, 70)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u32.c
new file mode 100644
index 00000000000..6564d4b9a27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_3(uint32_t, 5)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u64.c
new file mode 100644
index 00000000000..9f90030c430
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u64.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_3(uint64_t, 9)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u8.c
new file mode 100644
index 00000000000..13264a3022b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_3(uint8_t, 10)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u16.c
new file mode 100644
index 00000000000..5b5439152d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_4(uint16_t, 70)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u32.c
new file mode 100644
index 00000000000..08e32220ca6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_4(uint32_t, 5)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u64.c
new file mode 100644
index 00000000000..954c37616e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u64.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_4(uint64_t, 9)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u8.c
new file mode 100644
index 00000000000..18e1dd404b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_4(uint8_t, 10)
+
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u16.c
new file mode 100644
index 00000000000..420ec276466
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u16.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint16_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 65534)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 65535)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[4][0], d[4][1], 0, N);
+ RUN (T, out, d[5][0], d[5][1], 1, N);
+ RUN (T, out, d[6][0], d[6][1], 65534, N);
+ RUN (T, out, d[7][0], d[7][1], 65535, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u32.c
new file mode 100644
index 00000000000..2767175e574
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u32.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint32_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 4294967294)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 4294967295)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[4][0], d[4][1], 0, N);
+ RUN (T, out, d[5][0], d[5][1], 1, N);
+ RUN (T, out, d[6][0], d[6][1], 4294967294, N);
+ RUN (T, out, d[7][0], d[7][1], 4294967295, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u64.c
new file mode 100644
index 00000000000..64468d8c381
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u64.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint64_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 18446744073709551614u)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 18446744073709551615u)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[4][0], d[4][1], 0, N);
+ RUN (T, out, d[5][0], d[5][1], 1, N);
+ RUN (T, out, d[6][0], d[6][1], 18446744073709551614u, N);
+ RUN (T, out, d[7][0], d[7][1], 18446744073709551615u, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u8.c
new file mode 100644
index 00000000000..c9a8795bcf9
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u8.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint8_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 254)
+DEF_VEC_SAT_U_SUB_IMM_FMT_2_WRAP (T, 255)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[4][0], d[4][1], 0, N);
+ RUN (T, out, d[5][0], d[5][1], 1, N);
+ RUN (T, out, d[6][0], d[6][1], 254, N);
+ RUN (T, out, d[7][0], d[7][1], 255, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u16.c
new file mode 100644
index 00000000000..cff212b2ec2
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u16.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint16_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 65534)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 65535)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0, N);
+ RUN (T, out, d[1][0], d[1][1], 1, N);
+ RUN (T, out, d[2][0], d[2][1], 65534, N);
+ RUN (T, out, d[3][0], d[3][1], 65535, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u32.c
new file mode 100644
index 00000000000..aa2e549e4d8
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u32.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint32_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 4294967294)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 4294967295)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0, N);
+ RUN (T, out, d[1][0], d[1][1], 1, N);
+ RUN (T, out, d[2][0], d[2][1], 4294967294, N);
+ RUN (T, out, d[3][0], d[3][1], 4294967295, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u64.c
new file mode 100644
index 00000000000..7a3d837450c
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u64.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint64_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 18446744073709551614u)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 18446744073709551615u)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0, N);
+ RUN (T, out, d[1][0], d[1][1], 1, N);
+ RUN (T, out, d[2][0], d[2][1], 18446744073709551614u, N);
+ RUN (T, out, d[3][0], d[3][1], 18446744073709551615u, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u8.c
new file mode 100644
index 00000000000..063c79e7b6d
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u8.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint8_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 254)
+DEF_VEC_SAT_U_SUB_IMM_FMT_3_WRAP (T, 255)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0, N);
+ RUN (T, out, d[1][0], d[1][1], 1, N);
+ RUN (T, out, d[2][0], d[2][1], 254, N);
+ RUN (T, out, d[3][0], d[3][1], 255, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u16.c
new file mode 100644
index 00000000000..2785a21c464
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u16.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint16_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 65534)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 65535)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[4][0], d[4][1], 0, N);
+ RUN (T, out, d[5][0], d[5][1], 1, N);
+ RUN (T, out, d[6][0], d[6][1], 65534, N);
+ RUN (T, out, d[7][0], d[7][1], 65535, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u32.c
new file mode 100644
index 00000000000..1d751e3a562
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u32.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint32_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 4294967294)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 4294967295)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[4][0], d[4][1], 0, N);
+ RUN (T, out, d[5][0], d[5][1], 1, N);
+ RUN (T, out, d[6][0], d[6][1], 4294967294, N);
+ RUN (T, out, d[7][0], d[7][1], 4294967295, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u64.c
new file mode 100644
index 00000000000..d7ed62733b0
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u64.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint64_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 18446744073709551614u)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 18446744073709551615u)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[4][0], d[4][1], 0, N);
+ RUN (T, out, d[5][0], d[5][1], 1, N);
+ RUN (T, out, d[6][0], d[6][1], 18446744073709551614u, N);
+ RUN (T, out, d[7][0], d[7][1], 18446744073709551615u, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u8.c
new file mode 100644
index 00000000000..85ef38e322a
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u8.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint8_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 254)
+DEF_VEC_SAT_U_SUB_IMM_FMT_4_WRAP (T, 255)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+ RUN (T, out, d[4][0], d[4][1], 0, N);
+ RUN (T, out, d[5][0], d[5][1], 1, N);
+ RUN (T, out, d[6][0], d[6][1], 254, N);
+ RUN (T, out, d[7][0], d[7][1], 255, N);
+
+ return 0;
+}
--
2.17.1
