[Public]
Hi Honza,
> -Original Message-
> From: Jan Hubicka
> Sent: Tuesday, March 12, 2024 4:11 AM
> To: Anbazhagan, Karthiban
> Cc: gcc-patches@gcc.gnu.org; Kumar, Venkataramanan
> ; Joshi, Tejas Sanjay
> ; Nagarajan, Muthu kumar raj
> ; Gopalasubramanian,
ences.
so I thought of dumping the references here.
Is there a cleaner way to dump the references at one place?
Regards,
Venkat.
-Original Message-
From: Richard Guenther [mailto:rguent...@suse.de]
Sent: Tuesday, October 02, 2012 5:42 PM
To: Kumar, Venkataramanan
Cc: gcc-patches
richard.guent...@gmail.com]
Sent: Thursday, October 04, 2012 6:26 PM
To: Kumar, Venkataramanan
Cc: Richard Guenther; gcc-patches@gcc.gnu.org
Subject: Re: [Patch] Fix PR53397
On Tue, Oct 2, 2012 at 6:40 PM, Kumar, Venkataramanan
wrote:
> Hi Richi,
>
> (Snip)
>> + (!cst_and_fits_
Wednesday, October 10, 2012 12:06 PM
To: Kumar, Venkataramanan
Cc: Richard Guenther; gcc-patches@gcc.gnu.org
Subject: Re: [Patch] Fix PR53397
Hi!
On Mon, Oct 08, 2012 at 10:01:53AM +0000, Kumar, Venkataramanan wrote:
Both the testcases fail on i686-linux unfortunately:
Excess errors:
/usr/src/gcc/gcc
Hi Uros,
> -Original Message-
> From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Wednesday, February 03, 2016 2:20 AM
> To: Stepanyan, Victoria
> Cc: gcc-patches@gcc.gnu.org; ger...@pfeifer.com; rguent...@suse.de;
> Kumar, Venkataramanan
> Subject: Re: Turnoff p
Hi Maintainers,
Below patch does some minor changes to pipe reservations in znver1.md.
GCC bootstrap completed.
GCC regression testing underway. Ok for trunk if the testing passes?
ChangeLog
-
2016-02-12 Venkataramanan Kumar
* config/i386/znver1.md
(znver1_pop,
Hi Uros,
> -Original Message-
> From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Friday, February 12, 2016 11:06 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [Patch X86_64]: Minor changes to znver1 pipe reservations.
>
> On Fri,
Hi Richard,
As discussed in PR, tried to adjust the test case by initializing array, but
looks like for building with -fpic it needs visibility to be set a hidden.
The below patch does that.
Ok for trunk ?
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 82e538e..f6bcb07 10
ent: Tuesday, March 01, 2016 10:23 PM
> To: Kumar, Venkataramanan
> Cc: Richard Beiner (richard.guent...@gmail.com); gcc-patches@gcc.gnu.org;
> hjl.to...@gmail.com
> Subject: Re: [PATCH] Fix PR68621
>
> On Tue, Mar 01, 2016 at 04:48:40PM +, Kumar, Venkataramanan wrote:
> >
Hi Maintainers,
The below patch corrects the type attribute for "sseimul" type reservations in
znver1.md.
(snip)
diff --git a/gcc/config/i386/znver1.md b/gcc/config/i386/znver1.md
index 3db3bed..feeccd7 100644
--- a/gcc/config/i386/znver1.md
+++ b/gcc/config/i386/znver1.md
@@ -913,28 +913,28 @@
Hi Maintainers,
The below patch changes multiplication cost for -march=znver1 target.
GCC Bootstrap tested with BOOT_CFLAGS="-O2 -g -march=znver1".
(---Snip---)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d8a2909..b5dde5e 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/con
Hi Uros,
> -Original Message-
> From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Friday, March 04, 2016 1:10 AM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [Patch X86_64] : Fix type attribute for sseimul reservations in
> znver1.md
>
Hi Uros,
> -Original Message-
> From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Saturday, March 05, 2016 9:06 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org; Richard Beiner (richard.guent...@gmail.com)
> Subject: Re: [Patch X86_64]: Fix multiplicati
Hi Richard,
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Thursday, July 09, 2015 8:03 PM
> To: Kumar, Venkataramanan
> Cc: Gerald Pfeifer (ger...@pfeifer.com); gcc-patches@gcc.gnu.org
> Subject: Re: [Patch wwwdocs] gcc-5/chang
Hi Richard and Gerald,
This patch adds the documentation in changes.html for the GCC trunk (gcc-6) .
Please let me know if it is good to commit.
Index: htdocs/gcc-6/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.ht
your case.
Regards,
Venkat.
> -Original Message-
> From: Evandro Menezes [mailto:e.mene...@samsung.com]
> Sent: Wednesday, July 15, 2015 3:45 AM
> To: Kumar, Venkataramanan; pins...@gmail.com; 'Dr. Philipp Tomsich'
> Cc: 'James Greenhalgh'; '
Hi Richard,
For Aarch64 target, I was trying to vectorize the expression
"arr[i]=arr[i]*4;" via vector shifts instructions since they don't have
vector mults.
unsigned long int __attribute__ ((aligned (64)))arr[100];
int i;
#if 1
void test_vector_shifts()
{
for(i=0; i<=99;i++)
decide on the default
tuning.
Regards,
Venkat.
> -Original Message-
> From: Benedikt Huber [mailto:benedikt.hu...@theobroma-systems.com]
> Sent: Wednesday, July 29, 2015 11:18 PM
> To: gcc-patches@gcc.gnu.org
> Cc: philipp.toms...@theobroma-systems.com; Kumar, Venkata
Hi Jakub,
Thank you for reviewing the patch.
I have incorporated your comments in the attached patch.
> -Original Message-
> From: Jakub Jelinek [mailto:ja...@redhat.com]
> Sent: Wednesday, July 29, 2015 1:24 AM
> To: Kumar, Venkataramanan
> Cc: Richard Beiner
Hi Jeff,
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Jeff Law
> Sent: Monday, August 03, 2015 11:42 PM
> To: Kumar, Venkataramanan; Jakub Jelinek
> Cc: Richard Beiner (richard.guent...@gmail
Hi Richard,
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Tuesday, August 04, 2015 4:07 PM
> To: Kumar, Venkataramanan
> Cc: Jeff Law; Jakub Jelinek; gcc-patches@gcc.gnu.org
> Subject: Re: [RFC] [Patch]: Try and vectorize with s
Hi Richard,
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Wednesday, August 05, 2015 2:21 PM
> To: Kumar, Venkataramanan
> Cc: Jeff Law; Jakub Jelinek; gcc-patches@gcc.gnu.org
> Subject: Re: [RFC] [Patch]: Try and vectorize w
Hi Richard,
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Wednesday, August 05, 2015 5:11 PM
> To: Kumar, Venkataramanan
> Cc: Jeff Law; Jakub Jelinek; gcc-patches@gcc.gnu.org
> Subject: Re: [RFC] [Patch]: Try and vectorize w
Hi Maintainers,
The attached patch enables -march=znver1 (AMD family 17h Zen processor).
Costs and tunings are copied from bdver4, but we will be adjusting them later
for znver1.
Also a basic scheduler description for znver1 is added and we will update this
as we get more information.
T
t; To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [Patch] [x86_64] znver1 enablement
>
> On Wed, Sep 30, 2015 at 12:05 PM, Kumar, Venkataramanan
> wrote:
> > Hi Maintainers,
> >
> > The attached patch enables -march=znver1 (AMD family 17h Zen
>
Hi Uros,
Please find below patch that adds bdver4 target for multi versioning.
Also I while computing model, the extended_model is incorrectly left shifted
by 4. I have removed it now.
Is below patch Ok for trunk ?
GCC bootstrap and regressions passed.
diff --git a/libgcc/ChangeLog b/libgcc/
Thank you Uros,
I will test and commit model selection change in all release branches as well.
Regards,
Venkat.
> -Original Message-
> From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Friday, October 09, 2015 3:25 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patc
Hi Uros,
I realized both GCC 4.9 and GCC 5 branches includes processor subtype
AMDFAM15H_BDVER4.
So I need to back port not only model selection fix but also the detection of
model for bdver4.
Is that fine?
Regards,
Venkat.
> -Original Message-
> From: Kumar, Venkataramanan
Hi Uros,
> -Original Message-
> From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Tuesday, October 13, 2015 9:12 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [Patch] [x86_64]: Add bdver4 for multi versioning and fix AMD
> cpu model d
Hi Uros,
As per your comments in
https://gcc.gnu.org/ml/gcc-patches/2015-09/msg02326.html please find the patch
that also adds changes to libgcc.
It was bootstrapped and regressed tested on x86_64.
Ok for trunk?
Change logs
gcc/ChangeLog
2015-10-29 Venkataramanan Kumar
* config
Hi Richard,
I am trying to "if covert the store" in the below test case and later help it
to get vectorized under -Ofast -ftree-loop-if-convert-stores -fno-common
#define LEN 4096
__attribute__((aligned(32))) float array[LEN]; void test() { for (int i = 0; i
< LEN; i++) {
if (array[i] > (f
Hi Andrew,
> -Original Message-
> From: Andrew Pinski [mailto:pins...@gmail.com]
> Sent: Friday, October 30, 2015 3:38 PM
> To: Kumar, Venkataramanan
> Cc: Richard Beiner (richard.guent...@gmail.com); gcc-patches@gcc.gnu.org
> Subject: Re: [RFC] [Patch] Relax t
Hi Uros,
> -Original Message-
> From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Friday, October 30, 2015 2:33 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [Patch] [x86_64] libgcc changes to add znver1
>
> On Thu, Oct 29
Hi Richard,
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Friday, October 30, 2015 5:00 PM
> To: Kumar, Venkataramanan
> Cc: Andrew Pinski; gcc-patches@gcc.gnu.org
> Subject: Re: [RFC] [Patch] Relax tree-if-conv.c trap assump
I committed it on behalf of Victoria.
Regards,
Venkat.
> -Original Message-
> From: Gerald Pfeifer [mailto:ger...@pfeifer.com]
> Sent: Friday, November 13, 2015 1:08 AM
> To: Stepanyan, Victoria
> Cc: gcc-patches@gcc.gnu.org; ubiz...@gmail.com; rguent...@suse.de;
> Kum
Hi Richard and Bernhard.
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Tuesday, November 10, 2015 5:33 PM
> To: Kumar, Venkataramanan
> Cc: Andrew Pinski; gcc-patches@gcc.gnu.org
> Subject: Re: [RFC] [PATCH V2]: RE: [RFC] [Pa
Hi Richard,
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Monday, November 16, 2015 3:28 PM
> To: Kumar, Venkataramanan
> Cc: Bernhard Reutner-Fischer; Andrew Pinski; gcc-patches@gcc.gnu.org
> Subject: Re: [RFC] [PATCH V2]
Hi Richard,
As per Jakub suggestion in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67326,
the below patch fixes the regression in tree if conversion.
Basically allowing if conversion to happen for a candidate DR, if we find
similar DR with same dimensions and that DR will not trap.
To find si
Hi Richard,
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Tuesday, November 24, 2015 9:07 PM
> To: Kumar, Venkataramanan
> Cc: Jakub Jelinek (ja...@redhat.com); gcc-patches@gcc.gnu.org
> Subject: Re: [RFC] [Patch] PR67326 - rel
Hi Uros,
> -Original Message-
> From: Stepanyan, Victoria
> Sent: Thursday, November 26, 2015 1:43 AM
> To: Uros Bizjak; gcc-patches@gcc.gnu.org
> Cc: Kumar, Venkataramanan
> Subject: RE: Add support for CLZERO ISA
>
> Thank you for the feedback, PFA fi
Hi all,
> -Original Message-
> From: H.J. Lu [mailto:hjl.to...@gmail.com]
> Sent: Friday, January 12, 2018 7:36 PM
> To: Martin Jambor
> Cc: Nagarajan, Muthu kumar raj ;
> Kumar, Venkataramanan ; GCC
> Patches ; Jeff Law
> Subject: Re: [PATCH 2/5] x86: Ad
Hi all,
> -Original Message-
> From: Kumar, Venkataramanan
> Sent: Friday, January 12, 2018 8:16 PM
> To: 'H.J. Lu' ; Martin Jambor
> Cc: Nagarajan, Muthu kumar raj ;
> GCC Patches ; Jeff Law ; Uros
> Bizjak (ubiz...@gmail.com) ; 'Jan Hubicka
Hi HJ,
> -Original Message-
> From: Kumar, Venkataramanan
> Sent: Friday, January 12, 2018 8:39 PM
> To: 'H.J. Lu' ; 'Martin Jambor'
> Cc: Nagarajan, Muthu kumar raj ;
> 'GCC Patches' ; 'Jeff Law' ;
> Uros Bizjak (ubiz...@gmai
Hi All,
> -Original Message-
> From: H.J. Lu [mailto:hjl.to...@gmail.com]
> Sent: Saturday, January 13, 2018 1:11 AM
> To: Kumar, Venkataramanan
> Cc: Nagarajan, Muthu kumar raj ;
> GCC Patches ; Martin Jambor
> ; Jeff Law ; Uros Bizjak
> (ubiz...@gmail.com) ; J
Hi HJ,
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of H.J. Lu
> Sent: Sunday, January 14, 2018 9:07 AM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH 0/5] x86: CVE-2017-5715, aka Spectre
>
> This set of patches for GCC 8
Hi Arjan,
> -Original Message-
> From: Van De Ven, Arjan [mailto:arjan.van.de@intel.com]
> Sent: Saturday, January 13, 2018 10:16 PM
> To: David Woodhouse ; Kumar, Venkataramanan
> ; H.J. Lu ; Jeff
> Law ; Paul Turner ; Mallick, Asit K
>
> Cc: Nagarajan,
Hi
> -Original Message-
> From: H.J. Lu [mailto:hjl.to...@gmail.com]
> Sent: Sunday, January 14, 2018 7:52 PM
> To: Jan Hubicka
> Cc: Kumar, Venkataramanan ; gcc-
> patc...@gcc.gnu.org; Dharmakan, Rohit arul raj
> ; Nagarajan, Muthu kumar raj
> ; Uros B
Hi Jakub,
> -Original Message-
> From: Jakub Jelinek
> Sent: Tuesday, March 27, 2018 2:40 PM
> To: Richard Biener
> Cc: gcc-patches@gcc.gnu.org; Kumar, Venkataramanan
>
> Subject: [PATCH] Improve TRUTH_{AND,OR}IF_EXPR expansion (PR rtl-
> optimization/
Hi Jakub,
> -Original Message-
> From: Jakub Jelinek
> Sent: Tuesday, March 27, 2018 2:40 PM
> To: Richard Biener
> Cc: gcc-patches@gcc.gnu.org; Kumar, Venkataramanan
>
> Subject: [PATCH] Improve TRUTH_{AND,OR}IF_EXPR expansion (PR rtl-
> optimization/
Hi Jakub,
> -Original Message-
> From: Jakub Jelinek
> Sent: Tuesday, March 27, 2018 4:43 PM
> To: Kumar, Venkataramanan
> Cc: Richard Biener ; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] Improve TRUTH_{AND,OR}IF_EXPR expansion (PR rtl-
> optimization/78200)
>
Hi Maintainers,
Please find the attached patch, that fixes add/extend gcc test suite failures
in Aarch64 target.
Ref: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66049
These tests started to fail after we prevented combiner from converting shift
RTX to mult RTX, when the RTX is not inside a
Hi Kyrill,
Sorry for little delay in responding.
> -Original Message-
> From: Kyrill Tkachov [mailto:kyrylo.tkac...@foss.arm.com]
> Sent: Tuesday, May 19, 2015 9:13 PM
> To: Kumar, Venkataramanan; James Greenhalgh; gcc-patches@gcc.gnu.org
> Cc: Ramana Rad
Ping!
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On
Behalf Of Kumar, Venkataramanan
Sent: Tuesday, May 19, 2015 9:07 PM
To: James Greenhalgh (james.greenha...@arm.com); gcc-patches@gcc.gnu.org
Cc: Kyrill Tkachov (kyrylo.tkac...@arm.com
Thanks James
Committed as https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=223703
Regards,
Venkat.
> -Original Message-
> From: James Greenhalgh [mailto:james.greenha...@arm.com]
> Sent: Tuesday, May 26, 2015 2:09 PM
> To: Kumar, Venkataramanan
> Cc: gcc-
Hi Uros,
As discussed here https://gcc.gnu.org/ml/gcc/2015-06/msg00043.html
I am going to install the following patch to trunk.
GCC bootstrap and regressions tests passed.
Regards,
Venkat.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ab5c004..2fa6e96 100644
--- a/gcc/ChangeLog
+++ b/gcc/C
8 branch
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=224147
Trunk
https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=224146
regards,
Venkat.
> -Original Message-----
> From: Kumar, Venkataramanan
> Sent: Thursday, June 04, 2015 8:44 PM
> To: Uros Biz
Hi Kyrill,
In AMD Seattle board, I see that CPU implementer is 0x41 and CPU part is
0xd07.CPU variant is 1 but you don’t do anything with that.
It matches with cortex-a57 and its features.
I will try a bootstrap test as well.
Regards,
Venkat.
-Original Message-
From: gcc-pat
Hi Kyrill,
I checked this patch on AMD seattle board and it bootstrapped cleanly with
BOOT_CFLAGS=-O2 -mcpu=native and CFLAGS_FOR_TARGET=-O2 -mcpu=native.
With -mcpu=cortex-57, I get
.cpu cortex-a57+fp+simd+crc
options passed: test.c -mcpu=cortex-a57 -mlittle-endian -mabi=lp64
-auxbase-s
Hi Jeff/Segher,
Restarting the discussion on the GCC combiner assumption about Memory/address
type.
Ref: https://gcc.gnu.org/ml/gcc-patches/2015-01/msg01298.html
https://gcc.gnu.org/ml/gcc/2015-04/msg00028.html
While working on the test case in PR 63949, I came across the below code in
combin
01, 2015 8:48 PM
To: Kumar, Venkataramanan
Cc: Jeff Law (l...@redhat.com); gcc-patches@gcc.gnu.org;
maxim.kuvyr...@linaro.org
Subject: Re: [RFC]: Remove Mem/address type assumption in combiner
On Wed, Apr 29, 2015 at 12:03:35PM -0500, Segher Boessenkool wrote:
> On Wed, Apr 29, 2015 at 09:2
Hi Segher,
Thank you I committed as r222874.
Ref: https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=222874
Regards,
Venkat.
-Original Message-
From: Segher Boessenkool [mailto:seg...@kernel.crashing.org]
Sent: Tuesday, May 05, 2015 10:46 PM
To: Kumar, Venkataramanan
Cc:
Hi Steve,
Yes this is expected. As Segher pointed out, we need to change .md patterns in
target to be based on shifts instead of mults.
Regards,
Venkat.
-Original Message-
From: Steve Ellcey [mailto:sell...@imgtec.com]
Sent: Monday, May 11, 2015 11:20 PM
To: Kumar, Venkataramanan
Cc
Hi Maintainers,
This patch adds support for new MONITORX and MWAITX instructions and also
enables them via builtins.
The ISA is enabled by new -mmwaitx option and is available for AMD bdver4
target (-march=bdver4).
MONITORX and MWAITX implements same functionality as old MONITOR and MWAIT.
Hi Uros,
> -Original Message-
> From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Thursday, June 11, 2015 3:50 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] [X86_64]: Add support for MONITORX and MWAITX ISA
>
> On Thu,
From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Friday, June 12, 2015 4:02 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] [X86_64]: Add support for MONITORX and MWAITX ISA
>
> On Fri, Jun 12, 2015 at 12:27 PM, Kumar, Venkataramanan
>
Hi,
is there a plan to support -mrecip=rsqrt for Aarch64?
Regards,
Venkat.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Benedikt Huber
> Sent: Thursday, June 18, 2015 5:34 PM
> To: gcc-patches@gcc.gnu.org
> Cc: benedi
Hi,
If I understand correct, current implementation replaces
fdiv
fsqrt
by
frsqrte
for i=0 to 3
fmul
frsqrts
fmul
So I think gains depends latency of frsqrts insn.
I see patch has patterns for vector versions of frsqrts, but does not enable
them?
Regards,
Venkat.
> -Original
Changing to "1 step for float" and "2 steps for double" gives better gains now
for gromacs on cortex-a57.
Regards,
Venkat.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Benedikt Huber
> Sent: Thursday, June 25, 2015 4:09
I got around ~12% gain with -Ofast -mcpu=cortex-a57.
Regards,
Venkat.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Dr. Philipp Tomsich
> Sent: Thursday, June 25, 2015 9:13 PM
> To: Kumar, Venk
ong in my local tree.
Regards,
Venkat.
> -Original Message-
> From: pins...@gmail.com [mailto:pins...@gmail.com]
> Sent: Sunday, June 28, 2015 8:35 PM
> To: Kumar, Venkataramanan
> Cc: Dr. Philipp Tomsich; Benedikt Huber; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] [aarch
> -Original Message-
> From: Dr. Philipp Tomsich [mailto:philipp.toms...@theobroma-systems.com]
> Sent: Monday, June 29, 2015 2:17 PM
> To: Kumar, Venkataramanan
> Cc: pins...@gmail.com; Benedikt Huber; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] [aarch64] Implemented
Hi,
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Benedikt Huber
> Sent: Monday, June 29, 2015 11:04 PM
> To: Kumar, Venkataramanan
> Cc: pins...@gmail.com; Dr. Philipp Tomsich; gcc-patches@gcc.gnu
Hi,
> -Original Message-
> From: pins...@gmail.com [mailto:pins...@gmail.com]
> Sent: Monday, June 29, 2015 10:23 PM
> To: Dr. Philipp Tomsich
> Cc: James Greenhalgh; Kumar, Venkataramanan; Benedikt Huber; gcc-
> patc...@gcc.gnu.org; Marcus Shawcroft; Ramana Radh
Hi Gerald,
This patch documents about AMD instructions "mwaitx" and "monitorx" in GCC- 5
changes.html.
Please let me know if this ok to commit?
Index: htdocs/gcc-5/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-5/changes.h
Hi Maintainers,
PFA, the patch that enables support for the next generation AMD Zen CPU via
-march=znver2.
As of now, znver2 is using the same costs and scheduler descriptions written
for znver1.
We will update scheduler descriptions and costing for znver2 later as we get
more information.
Hi Uros,
> -Original Message-
> From: Uros Bizjak
> Sent: Friday, November 2, 2018 9:06 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org; Jan Hubicka
> Subject: Re: [patch][x86_64]: AMD znver2 enablement
>
> On Wed, Oct 31, 2018 at 6:25 AM Kumar,
Hi Uros and Honza,
I have committed the znver2 patch.
Ref:https://gcc.gnu.org/viewcvs/gcc?limit_changes=0&view=revision&revision=265775
Thanks you.
regards,
Venkat.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org
> On Behalf Of Kumar, Venkataramanan
> Se
Hi Uros,
> -Original Message-
> From: Uros Bizjak [mailto:ubiz...@gmail.com]
> Sent: Monday, August 22, 2016 12:36 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Kumar, Venkataramanan ; NightStrike
> StrikeNight
> Subject: [PATCH, i386]: Fine tune prefetchw emission
Hi Christophe,
> -Original Message-
> From: Christophe Lyon [mailto:christophe.l...@linaro.org]
> Sent: Tuesday, May 24, 2016 8:45 PM
> To: Kumar, Venkataramanan
> Cc: Richard Biener ; gcc-patches@gcc.gnu.org
> Subject: Re: [Patch V2] Fix SLP PR58135.
>
> Hi V
Hi Honza,
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Jan Hubicka
> Sent: Thursday, October 26, 2017 12:49 AM
> To: gcc-patches@gcc.gnu.org
> Subject: Add scatter/gather costs
>
> Hi,
> this patch adds computation of s
Hi,
The attached patch implements an RTL pass which splits generated FMA
instruction into MUL/ADD sequence.
The pass is enabled for Zen and done when we find it is profitable to split the
FMA.
On Zen, we found that for a tight loop with FMA (reduction) operation as show
below, generating
Hi Maarc,
> -Original Message-
> From: Marc Glisse [mailto:marc.gli...@inria.fr]
> Sent: Tuesday, November 7, 2017 12:52 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org; Dharmakan, Rohit arul raj
> ; Jan Hubicka (hubi...@ucw.cz)
> ; Uros Bizjak
> S
Hi Honza,
-Original Message-
From: Jan Hubicka [mailto:hubi...@ucw.cz]
Sent: Thursday, October 5, 2017 8:41 PM
To: gcc-patches@gcc.gnu.org; Kumar, Venkataramanan
Subject: Zen tuning part 2: Increase branch_cost to 3
Hi,
this patch increases branch_cost to 3. Constant 2 is apparently
gcc-patches@gcc.gnu.org; Kumar, Venkataramanan
>
> Subject: Re: [PATCH] [X86_64] Fix alignment for znver1 arch.
>
> On Tue, Feb 14, 2017 at 8:48 AM, Pawar, Amit wrote:
> > Hi maintainers,
> >
> > Please find the below patch which changes the code alignment values for
&g
Hi Uros,
While debugging GCC to see if cost of multiplication for DI mode is set
correctly for znver1 target.
I found that the order of cost table insertion is wrong for znver1 and it
worked because btver2 had same cost for multiply .
The patch corrects the mistake I made.
2016-03-08 Venkata
Hi Uros,
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Kumar, Venkataramanan
> Sent: Tuesday, March 08, 2016 7:21 PM
> To: Uros Bizjak (ubiz...@gmail.com); gcc-patches@gcc.gnu.org
> Cc: Richard Bei
Hi Maintainers,
> -Original Message-
> From: Kumar, Venkataramanan
> Sent: Tuesday, March 08, 2016 7:27 PM
> To: Uros Bizjak (ubiz...@gmail.com); gcc-patches@gcc.gnu.org
> Cc: Richard Beiner (richard.guent...@gmail.com); Kumar, Venkataramanan
> Subject: RE: [Patch x86
Hi Uros,
The below patch changes the latency values for fp type load reservations.
It passes normal bootstrap and bootstrap with BOOT_CFLAGS="-O2 -g -
march=znver1 -mno-clzero -mno-sha " on avx2 target.
Also compiled and ran SPEC2006 with -march=znver1 and -Ofast .
Ok for trunk?
ChangeLog
2
Hi Maintainers,
The below patch fixes integer load type reservations for -march=znver1.
Bootstrapped and regtested on x86_64-pc-linux-gnu.
Ok to commit to trunk ?
(-Snip)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9659fbf..19b4066 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLo
Hi Richard,
As per your suggestion I tried to fix the PR by splitting the SLP store group
at vector boundary after the SLP tree is built.
Boot strap PASSED on x86_64.
Checked the patch with check_GNU_style.sh.
The gfortran.dg/pr46519-1.f test now does SLP vectorization. Hence it
generated 2
Hi Richard,
I created the patch by passing -b option to git. Now the patch is more readable.
As per your suggestion I tried to fix the PR by splitting the SLP store group
at vector boundary after the SLP tree is built.
Boot strap PASSED on x86_64.
Checked the patch with check_GNU_style.sh.
Th
Hi Richard,
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Tuesday, May 17, 2016 5:40 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [Patch V2] Fix SLP PR58135.
>
> On Tue, May 17
Hi Richard,
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Thursday, May 19, 2016 4:08 PM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [Patch V2] Fix SLP PR58135.
>
> On Wed, May 18
Hi ,
For the below code x86_64 is able to vectorize.
#define LEN 32000
__attribute__((aligned(32))) float a[LEN], b[LEN],c[LEN];
void test()
{
for (int i = 0; i < LEN; i++) {
if (b[i] > (float)0.) {
a[i] = b[i];
}
}
}
X86_64 ASM
L2:
vmovaps b(%rax), %ymm0
Hi James,
> -Original Message-
> From: James Greenhalgh [mailto:james.greenha...@arm.com]
> Sent: Monday, January 11, 2016 5:24 PM
> To: gcc-patches@gcc.gnu.org
> Cc: n...@arm.com; marcus.shawcr...@arm.com;
> richard.earns...@arm.com; Kumar, Venkataramanan;
> phil
Hi
The code below it looks like we always call “vect_permute_load_chain” to load
non-unit strides of size powers of 2.
(---snip---)
/* If reassociation width for vector type is 2 or greater target machine can
execute 2 or more vector instructions in parallel. Otherwise try to
get ch
Hi Maintainers,
Please fine below patch that sets preferred vectorization mode for btver2 as
avx128.
We tested some benchmarks and found that enabling 128-bit AVX instruction
generation by the auto vectorizer performs better than
default 256-bit AVX.
Completed bootstrap and make -k check p
btver2_fp_check
00012788 r btver2_fp_transitions
00053730 r btver2_fp_min_issue_delay
(Snip)
Regards,
Venkat.
-Original Message-
From: Jan Hubicka [mailto:hubi...@ucw.cz]
Sent: Thursday, January 17, 2013 6:02 PM
To: Uros Bizjak
Cc: Kumar, Venkataramanan; gcc-patches
egards,
Venkat.
-Original Message-
From: Steven Bosscher [mailto:stevenb@gmail.com]
Sent: Thursday, January 17, 2013 7:10 PM
To: Kumar, Venkataramanan
Cc: Jan Hubicka; Uros Bizjak; gcc-patches@gcc.gnu.org
Subject: Re: [Patch i386]: btver2 pipeline descriptions.
On Thu, Jan 17, 2013 at
Hi Uros,
Thank you for the review comments.
Committed to trunk at http://gcc.gnu.org/viewcvs?view=revision&revision=191245
Regards,
Venkat.
-Original Message-
From: Uros Bizjak [mailto:ubiz...@gmail.com]
Sent: Wednesday, September 12, 2012 9:14 PM
To: Kumar, Venkataramanan
Cc:
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