[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we use "group_overlap" and "enabled" attribu

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we use "group_overlap" and "enabled" attribu

[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * con

[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * con

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we add an attribute "spec_restriction" to di

[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (class th_extract): Define new builtin bases.

[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (class th_extract): Define new builtin bases.

[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH v5] RISC-V: Support XTheadVector extension

This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in order not to generate instructions that xtheadvector does not

[PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0

This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Add new vendor extens

[PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. We only check the prefix is 'v', so that no extra attribute is needed. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): Add new function to add assembl

[PATCH v6] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (class th_extract): Define new builtin bases.

[PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we add an attribute "spec_restriction" to di

[PATCH v5] RISC-V: Rewrite some instructions using ASM targethook

There are some xtheadvector instructions that differ from RVV1.0 apart from simply adding "th." prefix. For example, RVV1.0 load/store instructions will have SEW while xtheadvector not; RVV1.0 will have "o" for indexed-ordered store instructions while xtheadvecotr not; xtheadvector and RVV1.0 have

[PATCH v3 0/6] RISC-V: Support XTheadVector extension

This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in order not to generate instructions that xtheadvector does not

[PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc

This patch moves the definition of the enums lst_type and frm_op_type into riscv-vector-builtins-bases.h and removes the static visibility of fold_fault_load(), so these can be used in other compile units. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (enum lst_type):

[PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns.

This patch splits the definition of csr_operand in predicates.md. The newly defined vector_csr_operand has the same functionality as csr_operand but can only be used in vector patterns, so that changes for vector will not affect scalar patterns in files like riscv.md. gcc/ChangeLog: * con

[PATCH v3 3/6] RISC-V: Introduce XTheadVector as a subset of V1.0.0

This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Add new vendor extens

[PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): New function. * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. * config/ri

[PATCH v3 6/6] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * con

[PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. In this version, we follow Kito's suggestions and only check the prefix is 'v', so that no extra attribute is needed. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output

[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH v4 6/6] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * con

[PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. In this version, we follow Kito's suggestions and only check the prefix is 'v', so that no extra attribute is needed. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output

[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH v4 6/6] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * con

[PATCH v4] RISC-V: Support XTheadVector extension

This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in order not to generate instructions that xtheadvector does not

[PATCH v4] RISC-V: Refactor riscv-vector-builtins-bases.cc

This patch moves the definition of the enums lst_type and frm_op_type into riscv-vector-builtins-bases.h and removes the static visibility of fold_fault_load(), so these can be used in other compile units. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (enum lst_type):

[PATCH v4] RISC-V: Change csr_operand into

This patch use vector_length_operand instead of csr_operand for vsetvl patterns, so that changes for vector will not affect scalar patterns using csr_operand in riscv.md. gcc/ChangeLog: * config/riscv/vector.md: Use vector_length_operand for vsetvl patterns. Co-authored-by: Jin M

[PATCH v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns.

This patch use vector_length_operand instead of csr_operand for vsetvl patterns, so that changes for vector will not affect scalar patterns using csr_operand in riscv.md. gcc/ChangeLog: * config/riscv/vector.md: Use vector_length_operand for vsetvl patterns. Co-authored-by: Jin M

[PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0

This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Add new vendor extens

[PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. We only check the prefix is 'v', so that no extra attribute is needed. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): New function to add assembler

[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH v4 6/6] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * con

[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH v4] RISC-V: Fix register overlap issue for some xtheadvector instructions

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we use "group_overlap" and "enabled" attribu

[PATCH v4] RISC-V: Rewrite some instructions using ASM targethook

There are some xtheadvector instructions that differ from RVV1.0 apart from simply adding "th." prefix. For example, RVV1.0 load/store instructions will have SEW while xtheadvector not; RVV1.0 will have "o" for indexed-ordered store instructions while xtheadvecotr not; xtheadvector and RVV1.0 have

[PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. We only check the prefix is 'v', so that no extra attribute is needed. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): New function to add assembler i

[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH v4] RISC-V: Fix register overlap issue for some xtheadvector instructions

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we use "group_overlap" and "enabled" attribu

[PATCH v4] RISC-V: Rewrite some instructions using ASM targethook

There are some xtheadvector instructions that differ from RVV1.0 apart from simply adding "th." prefix. For example, RVV1.0 load/store instructions will have SEW while xtheadvector not; RVV1.0 will have "o" for indexed-ordered store instructions while xtheadvecotr not; xtheadvector and RVV1.0 have

[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH v4] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * con

[PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0

This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Add new vendor extens

[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation between Vector and XTheadVector. In this version, we only support partial xtheadvector instructions that leverage directly from current RVV1.0 with simple adding "th." prefix. For different name xtheadvector instructions but share sa

[PATCH 0/9] RISC-V: Support XTheadVector extensions

This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ Contributors: Jun Sha (Joshua) Jin Ma RISC-V: minimal support for xtheadvector RISC-V: Handle differences between xtheadvector and vector

[PATCH 1/9] RISC-V: minimal support for xtheadvector

This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): : Add new vendor exte

[PATCH 2/9] RISC-V: Handle differences between xtheadvector and vector

This patch is to handle the differences in instruction generation between vector and xtheadvector, mainly adding th. prefix to all xtheadvector instructions. gcc/ChangeLog: * config.gcc: Add header for XTheadVector intrinsics. * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):

[PATCH 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c: New test. * gcc

[PATCH 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c: New test. * gc

[PATCH 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c: New test. * gc

[PATCH 6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for ternary and unary operations. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-1.c: New test.

[PATCH 7/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part5)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for auto-vectorization. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/autovec/vadd-run-nofm.c: New test. * gc

[PATCH 8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics

This patch only involves the generation of xtheadvector special load/store instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * config/riscv/riscv-vector

[PATCH 9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension

Because the XTheadVector extension does not support fractional operations, so we need to delete the related intrinsics. The types involved are as follows: v(u)int8mf8_t, v(u)int8mf4_t, v(u)int8mf2_t, v(u)int16mf4_t, v(u)int16mf2_t, v(u)int32mf2_t, vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t gcc/C

[PATCH v2 0/9] RISC-V: Support XTheadVector extensions

This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ I updated my patch series, because I forgot to add co-authors in the last version. Contributors: Jun Sha (Joshua) Jin Ma Christoph

[PATCH v2 1/9] RISC-V: minimal support for xtheadvector

This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/ChangeLog: * common

[PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector

This patch is to handle the differences in instruction generation between vector and xtheadvector, mainly adding th. prefix to all xtheadvector instructions. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/ChangeLog: * config.gcc: Add header for

[PATCH v2 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/testsuite/ChangeLog

[PATCH v2 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/testsuite/ChangeLog

[PATCH v2 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for binary operations. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/testsuite/ChangeLog

[PATCH v2 6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4)

For big changes in instruction generation, we can only duplicate some typical tests in testsuite/gcc.target/riscv/rvv/base. This patch is adding some tests for ternary and unary operations. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/testsuite

[PATCH v2 8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics

This patch involves the generation of xtheadvector special load/store instructions. Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin

[PATCH v2 9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension

Contributors: Jun Sha (Joshua) Jin Ma Christoph Müllner gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_v_ext_mode_p): New extern. * config/riscv/riscv-vector-builtins-shapes.cc (check_type): New function. (build_one): If the