This patch series presents gcc implementation of the XTheadVector extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/ For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in order not to generate instructions that xtheadvector does not support, causing 10 changes in vector.md. For the th. prefix issue, we use current_output_insn and the ASM_OUTPUT_OPCODE hook instead of directly modifying patterns in vector.md. We have run the GCC test suite and can confirm that there are no regressions. Furthermore, we have run the tests in https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples, and all the tests passed. Co-authored-by: Jin Ma <ji...@linux.alibaba.com> Co-authored-by: Xianmiao Qu <cooper...@linux.alibaba.com> Co-authored-by: Christoph Müllner <christoph.muell...@vrull.eu> [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 [PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector [PATCH v6] RISC-V: Handle differences between XTheadvector and Vector [PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics [PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions [PATCH v5] RISC-V: Rewrite some instructions using ASM targethook
