[PATCH v3] MIPS16: Implement `code_readable` function attribute.

From: Simon Dardis Support for __attribute__ ((code_readable)). Takes up to one argument of "yes", "no", "pcrel". This will change the code readability setting for just that function. If no argument is supplied, then the setting is 'yes'. gcc/ChangeLog: * config/mips/mips.cc (enum mi

[PATCH v4 3/9] MIPS: Add instruction about global pointer register for mips16e2

The mips16e2 ASE uses eight general-purpose registers from mips32, with some special-purpose registers, these registers are GPRs: s0-1, v0-1, a0-3, and special registers: t8, gp, sp, ra. As mentioned above, the special register gp is used in mips16e2, which is the global pointer register, it is us

[PATCH v4 5/9] MIPS: Add LUI instruction for mips16e2

This patch adds LUI instruction from mips16e2 with corresponding test. gcc/ChangeLog: * config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction. (mips_const_insns): Same as above. (mips_output_move): Same as above. (mips_output_function_prologue): Same

[PATCH v4 7/9] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2

The MIPS16e2 ASE has PREF, LL and SC instructions, they use 9 bits immediate, like mips32r6. The MIPS32 PRE-R6 uses 16 bits immediate. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause for ISA_HAS_MIPS16E2. (ISA_HAS_SYNC): Same as above. (I

[PATCH v4 0/9] MIPS: Add MIPS16e2 ASE instrucions.

instructions from MIPS16E2 ASE with corresponding tests. Jie Mei (9): MIPS: Add basic support for mips16e2 MIPS: Add MOVx instructions support for mips16e2 MIPS: Add instruction about global pointer register for mips16e2 MIPS: Add bitwise instructions for mips16e2 MIPS: Add LUI instruction

[PATCH v4 6/9] MIPS: Add load/store word left/right instructions for mips16e2

This patch adds LWL/LWR, SWL/SWR instructions with their corresponding tests. gcc/ChangeLog: * config/mips/mips.cc(mips_expand_ins_as_unaligned_store): Add logics for generating instruction. * config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2. *

[PATCH v4 9/9] MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions

This patch allows mips16e2 acts the same with -O1~3 when generating ZEB/ZEH instead of ANDI under the -O0 option, which shrinks the code size. gcc/ChangeLog: * config/mips/mips.md(*and3_mips16): Generates ZEB/ZEH instructions. --- gcc/config/mips/mips.md | 30 +

[PATCH v4 8/9] MIPS: Add CACHE instruction for mips16e2

This patch adds CACHE instruction from mips16e2 with corresponding tests. gcc/ChangeLog: * config/mips/mips.c(mips_9bit_offset_address_p): Restrict the address register to M16_REGS for MIPS16. (BUILTIN_AVAIL_MIPS16E2): Defined a new macro. (AVAIL_MIPS16E2_OR_NON_MI

[PATCH v4 1/9] MIPS: Add basic support for mips16e2

The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. It defines new special instructions for increasing code density (e.g. Extend, PC-relative instructions, etc.). This patch adds basic support for mips16e2 used by the following series

[PATCH v4 2/9] MIPS: Add MOVx instructions support for mips16e2

This patch adds MOVx instructions from mips16e2 (movn,movz,movtn,movtz) with corresponding tests. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for ISA_HAS_MIPS16E2. * config/mips/mips.md(*mov_on_): Add logics for MOVx insts. (*mov_on__mips16e2): G

[PATCH v4 4/9] MIPS: Add bitwise instructions for mips16e2

There are shortened bitwise instructions in the mips16e2 ASE, for instance, ANDI, ORI/XORI, EXT, INS etc. . This patch adds these instrutions with corresponding tests. gcc/ChangeLog: * config/mips/constraints.md(Yz): New constraints for mips16e2. * config/mips/mips-protos.h(mips_

[PATCH] MIPS: Adjust mips16e2 related tests for ifcvt costing changes

A mips16e2 related test fails after the ifcvt change. The mips16e2 addition also causes a test for unrelated module to fail. This patch adjusts branch costs when running the two affected tests. These tests should not require the -mbranch-cost option, and this issue needs to be addressed. gcc/tes

[PATCH v2 7/9] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2

The MIPS16e2 ASE has PREF, LL and SC instructions, they use 9 bits immediate, like mips32r6. The MIPS32 PRE-R6 uses 16 bits immediate. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause for ISA_HAS_MIPS16E2. (ISA_HAS_SYNC): Same as above. (I

[PATCH v2 1/9] MIPS: Add basic support for mips16e2

The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. It defines new special instructions for increasing code density (e.g. Extend, PC-relative instructions, etc.). This patch adds basic support for mips16e2 used by the following series

[PATCH v2 8/9] MIPS: Add CACHE instruction for mips16e2

This patch adds CACHE instruction from mips16e2 with corresponding tests. gcc/ChangeLog: * config/mips/mips.c(mips_9bit_offset_address_p): Restrict the address register to M16_REGS for MIPS16. (BUILTIN_AVAIL_MIPS16E2): Defined a new macro. (AVAIL_MIPS16E2_OR_NON_MI

[PATCH v2 0/9] MIPS: Add MIPS16e2 ASE instrucions.

The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. This series of patches adds all instructions of MIPS16E2 ASE. Jie Mei (9): MIPS: Add basic support for mips16e2 MIPS: Add MOVx instructions support for mips16e2 MIPS: Add

[PATCH v2 2/9] MIPS: Add MOVx instructions support for mips16e2

This patch adds MOVx instructions from mips16e2 (movn,movz,movtn,movtz) with corresponding tests. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for ISA_HAS_MIPS16E2. * config/mips/mips.md(*mov_on_): Add logics for MOVx insts. (*mov_on__mips16e2): G

[PATCH v2 3/9] MIPS: Add instruction about global pointer register for mips16e2

The mips16e2 ASE uses eight general-purpose registers from mips32, with some special-purpose registers, these registers are GPRs: s0-1, v0-1, a0-3, and special registers: t8, gp, sp, ra. As mentioned above, the special register gp is used in mips16e2, which is the global pointer register, it is us

[PATCH v2 5/9] MIPS: Add LUI instruction for mips16e2

This patch adds LUI instruction from mips16e2 with corresponding test. gcc/ChangeLog: * config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction. (mips_const_insns): Same as above. (mips_output_move): Same as above. (mips_output_function_prologue): Same

[PATCH v2 6/9] MIPS: Add load/store word left/right instructions for mips16e2

This patch adds LWL/LWR, SWL/SWR instructions with their corresponding tests. gcc/ChangeLog: * config/mips/mips.cc(mips_expand_ins_as_unaligned_store): Add logics for generating instruction. * config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2. *

[PATCH v2 4/9] MIPS: Add bitwise instructions for mips16e2

There are shortened bitwise instructions in the mips16e2 ASE, for instance, ANDI, ORI/XORI, EXT, INS etc. . This patch adds these instrutions with corresponding tests. gcc/ChangeLog: * config/mips/constraints.md(Yz): New constraints for mips16e2. * config/mips/mips-protos.h(mips_

[PATCH v2 9/9] MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions

This patch allows mips16e2 acts the same with -O1~3 when generating ZEB/ZEH instead of ANDI under the -O0 option, which shrinks the code size. gcc/ChangeLog: * config/mips/mips.md(*and3_mips16): Generates ZEB/ZEH instructions. --- gcc/config/mips/mips.md | 30 +

[PATCH] MIPS16: Implement `code_readable` function attribute.

Support for __attribute__ ((code_readable)). Takes up to one argument of "yes", "no", "pcrel". This will change the code readability setting for just that function. If no argument is supplied, then the setting is 'yes'. gcc/ChangeLog: * config/mips/mips.cc (enum mips_code_readable_sett

[PATCH v2] MIPS16: Implement `code_readable` function attribute.

From: Simon Dardis Support for __attribute__ ((code_readable)). Takes up to one argument of "yes", "no", "pcrel". This will change the code readability setting for just that function. If no argument is supplied, then the setting is 'yes'. gcc/ChangeLog: * config/mips/mips.cc (enum mi

[PATCH v3 0/9] MIPS: Add MIPS16e2 ASE instrucions.

corresponding tests. Jie Mei (9): MIPS: Add basic support for mips16e2 MIPS: Add MOVx instructions support for mips16e2 MIPS: Add instruction about global pointer register for mips16e2 MIPS: Add bitwise instructions for mips16e2 MIPS: Add LUI instruction for mips16e2 MIPS: Add load/store word left

[PATCH v3 4/9] MIPS: Add bitwise instructions for mips16e2

There are shortened bitwise instructions in the mips16e2 ASE, for instance, ANDI, ORI/XORI, EXT, INS etc. . This patch adds these instrutions with corresponding tests. gcc/ChangeLog: * config/mips/constraints.md(Yz): New constraints for mips16e2. * config/mips/mips-protos.h(mips_

[PATCH v3 5/9] MIPS: Add LUI instruction for mips16e2

This patch adds LUI instruction from mips16e2 with corresponding test. gcc/ChangeLog: * config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction. (mips_const_insns): Same as above. (mips_output_move): Same as above. (mips_output_function_prologue): Same

[PATCH v3 2/9] MIPS: Add MOVx instructions support for mips16e2

This patch adds MOVx instructions from mips16e2 (movn,movz,movtn,movtz) with corresponding tests. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for ISA_HAS_MIPS16E2. * config/mips/mips.md(*mov_on_): Add logics for MOVx insts. (*mov_on__mips16e2): G

[PATCH v3 1/9] MIPS: Add basic support for mips16e2

The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. It defines new special instructions for increasing code density (e.g. Extend, PC-relative instructions, etc.). This patch adds basic support for mips16e2 used by the following series

[PATCH v3 6/9] MIPS: Add load/store word left/right instructions for mips16e2

This patch adds LWL/LWR, SWL/SWR instructions with their corresponding tests. gcc/ChangeLog: * config/mips/mips.cc(mips_expand_ins_as_unaligned_store): Add logics for generating instruction. * config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2. *

[PATCH v3 3/9] MIPS: Add instruction about global pointer register for mips16e2

The mips16e2 ASE uses eight general-purpose registers from mips32, with some special-purpose registers, these registers are GPRs: s0-1, v0-1, a0-3, and special registers: t8, gp, sp, ra. As mentioned above, the special register gp is used in mips16e2, which is the global pointer register, it is us

[PATCH v3 7/9] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2

The MIPS16e2 ASE has PREF, LL and SC instructions, they use 9 bits immediate, like mips32r6. The MIPS32 PRE-R6 uses 16 bits immediate. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause for ISA_HAS_MIPS16E2. (ISA_HAS_SYNC): Same as above. (I

[PATCH v3 8/9] MIPS: Add CACHE instruction for mips16e2

This patch adds CACHE instruction from mips16e2 with corresponding tests. gcc/ChangeLog: * config/mips/mips.c(mips_9bit_offset_address_p): Restrict the address register to M16_REGS for MIPS16. (BUILTIN_AVAIL_MIPS16E2): Defined a new macro. (AVAIL_MIPS16E2_OR_NON_MI

[PATCH v3 9/9] MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions

This patch allows mips16e2 acts the same with -O1~3 when generating ZEB/ZEH instead of ANDI under the -O0 option, which shrinks the code size. gcc/ChangeLog: * config/mips/mips.md(*and3_mips16): Generates ZEB/ZEH instructions. --- gcc/config/mips/mips.md | 30 +

[PATCH] MIPS: Add MIN/MAX.fmt instructions support for MIPS R6

This patch adds MIN/MAX.fmt instructios from MIPS R6 with corresponding tests. gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_minmax): New define_insn_reservation. * config/mips/mips.h (ISA_HAS_FMIN_FMAX): Define new macro. * config/mips/mips.md (type): Add fminm

[PATCH v2] MIPS: Add MIN/MAX.fmt instructions support for MIPS R6

This patch adds the smin/smax RTL mode for the min/max.fmt instructions. Also, since the min/max.fmt instrucions applies to the IEEE 754-2008 "minNum" and "maxNum" operations, this patch also provides the new "fmin3" and "fmax3" modes. gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_min

[PATCH] MIPS: Add some floating point instructions support for MIPSr6

This patch adds some floating point instructiions from mips32r6, for instance, MINA/MAXA.fmt, RINT.fmt, CLASS.fmt etc. Also add built-in functions to MIPSr6 to better handle tests for MIPSr6. gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_minmax): Include fclass type. (

[PATCH v3] MIPS: Add MIN/MAX.fmt instructions support for MIPS R6

This patch adds the smin/smax RTL mode for the min/max.fmt instructions. Also, since the min/max.fmt instrucions applies to the IEEE 754-2008 "minNum" and "maxNum" operations, this patch also provides the new "fmin3" and "fmax3" modes. gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_min

[PATCH] MIPS: Add MSUBF.fmt instruction for MIPSr6

GCC currently uses two instructions (NEG.fmt and MADDF.fmt) for operations like `x - (y * z)' for MIPSr6. We can further tune this by using only MSUBF.fmt instead of those two. This patch adds MSUBF.fmt instrutions with corresponding tests. gcc/ChangeLog: * config/mips/mips.md (fms4): Ge

[PATCH 5/8] MIPS: Add LUI instruction for mips16e2

This patch adds LUI instruction from mips16e2 with corresponding test. gcc/ChangeLog: * gcc/config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction. (mips_const_insns): Same as above. (mips_output_move): Same as above. (mips_output_function_prologue):

[PATCH 6/8] MIPS: Add load/store word left/right instructions for mips16e2

This patch adds LWL/LWR, SWL/SWR instructions with their corresponding tests. gcc/ChangeLog: * gcc/config/mips/mips.cc(mips_expand_ins_as_unaligned_store): Add logics for generating instruction. * gcc/config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2.

[PATCH 2/8] MIPS: Add MOVx instructions support for mips16e2

This patch adds MOVx instructions from mips16e2 (movn,movz,movtn,movtz) with corresponding tests. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for ISA_HAS_MIPS16E2. * config/mips/mips.md(*mov_on_): Add logics for MOVx insts. (*mov_on__mips16e2): G

[PATCH 3/8] MIPS: Add instruction about global pointer register for mips16e2

The mips16e2 ASE uses eight general-purpose registers from mips32, with some special-purpose registers, these registers are GPRs: s0-1, v0-1, a0-3, and special registers: t8, gp, sp, ra. As mentioned above, the special register gp is used in mips16e2, which is the global pointer register, it is us

[PATCH 0/8] MIPS: Add MIPS16e2 ASE instrucions.

The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. This series of patches adds all instructions of MIPS16E2 ASE. Jie Mei (8): MIPS: Add basic support for mips16e2 MIPS: Add MOVx instructions support for mips16e2 MIPS: Add

[PATCH 1/8] MIPS: Add basic support for mips16e2

The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. It defines new special instructions for increasing code density (e.g. Extend, PC-relative instructions, etc.). This patch adds basic support for mips16e2 used by the following series

[PATCH 4/8] MIPS: Add bitwise instructions for mips16e2

There are shortened bitwise instructions in the mips16e2 ASE, for instance, ANDI, ORI/XORI, EXT, INS etc. . This patch adds these instrutions with corresponding tests. gcc/ChangeLog: * gcc/config/mips/constraints.md(Yz): New constraints for mips16e2. * gcc/config/mips/mips-protos

[PATCH 7/8] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2

The MIPS16e2 ASE has PREF, LL and SC instructions, they use 9 bits immediate, like mips32r6. The MIPS32 PRE-R6 uses 16 bits immediate. gcc/ChangeLog: * gcc/config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause for ISA_HAS_MIPS16E2. (ISA_HAS_SYNC): Same as above.

[PATCH 8/8] MIPS: Add CACHE instruction for mips16e2

This patch adds CACHE instruction from mips16e2 with corresponding tests. gcc/ChangeLog: * config/mips/mips.c(mips_9bit_offset_address_p): Restrict the address register to M16_REGS for MIPS16. (BUILTIN_AVAIL_MIPS16E2): Defined a new macro. (AVAIL_MIPS16E2_OR_NON_MI

[PATCH v2] MIPS: Add some floating point instructions support for MIPSr6

* gcc.target/mips/mips-minamaxa.c: Same as above. * gcc.target/mips/mips-rint.c: Same as above. Signed-off-by: Jie Mei Co-authored-by: Xi Ruoyao --- gcc/config/mips/i6400.md | 8 +-- gcc/config/mips/mips.cc | 24 + gcc/config/mips/mips.h

[PATCH] MIPS: Add conditions for use of the -mmips16e2 and -mips16 option.

MIPS16e2 ASE is a superset of MIPS16e ASE, which is again a superset of MIPS16 ASE. Later, all of them are forbidden in Release 6. Make -mmips16e2 imply -mips16 as the ASE requires, so users won't be surprised even if they expect it to. Meanwhile, check if mips_isa_rev <= 5 when -mips16 is effecti

[PATCH v2] MIPS: Add conditions for use of the -mmips16e2 and -mips16 option.

Changes from V1: * Raise the minimal revision to r2. MIPS16e2 ASE is a superset of MIPS16e ASE, which is again a superset of MIPS16 ASE. Later, all of them are forbidden in Release 6. Make -mmips16e2 imply -mips16 as the ASE requires, so users won't be surprised even if they expect it to. Meanwhi