Changes from V1:
* Raise the minimal revision to r2.
MIPS16e2 ASE is a superset of MIPS16e ASE, which is again a superset
of MIPS16 ASE. Later, all of them are forbidden in Release 6.
Make -mmips16e2 imply -mips16 as the ASE requires, so users won't
be surprised even if they expect it to. Meanwhile, check if
mips_isa_rev <= 5 when -mips16 is effective and >= 2 when -mmips16e2
is effective.
gcc/ChangeLog:
* config/mips/mips.cc(mips_option_override):Add conditions
for use of the -mmips16e2 and -mips16 option.
gcc/testsuite/ChangeLog:
* gcc.target/mips/mips16e2-cache.c: Use isa_rev>=2 instead of
-mips32r2 and remove -mips16 option.
* gcc.target/mips/mips16e2-cmov.c: Add isa_rev>=2 and remove
-mips16 option.
* gcc.target/mips/mips16e2-gp.c: Same as above.
* gcc.target/mips/mips16e2.c: Same as above.
Co-developed-by: Rong Zhang <rongr...@oss.cipunited.com>
Signed-off-by: Rong Zhang <rongr...@oss.cipunited.com>
---
gcc/config/mips/mips.cc | 19 +++++++++++++++++++
.../gcc.target/mips/mips16e2-cache.c | 2 +-
gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 2 +-
gcc/testsuite/gcc.target/mips/mips16e2-gp.c | 2 +-
gcc/testsuite/gcc.target/mips/mips16e2.c | 2 +-
5 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 492fa285477..173e3fe72e6 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -20402,6 +20402,16 @@ mips_option_override (void)
if (TARGET_MICROMIPS && TARGET_MIPS16)
error ("unsupported combination: %s", "-mips16 -mmicromips");
+ /* Make -mmips16e2 imply -mips16 and forbid its coexistence with
+ -mmicromips as the ASE requires. */
+ if (TARGET_MIPS16E2)
+ {
+ if (TARGET_MICROMIPS)
+ error ("unsupported combination: %s", "-mmips16e2 -mmicromips");
+
+ target_flags |= MASK_MIPS16;
+ }
+
/* Prohibit Paired-Single and MSA combination. This is software restriction
rather than architectural. */
if (ISA_HAS_MSA && TARGET_PAIRED_SINGLE_FLOAT)
@@ -20654,6 +20664,15 @@ mips_option_override (void)
"-mcompact-branches=never");
}
+ /* MIPS16* ASE is forbidden in Release 6, so -mips16 is not available
+ for MIPS R6 onwards. */
+ if ((mips_base_compression_flags & MASK_MIPS16) && mips_isa_rev >= 6)
+ error ("MIPS16* ASE is forbidden in Release 6");
+
+ /* Make sure that the user use Release[2,5] when using -mmips16e2. */
+ if (TARGET_MIPS16E2 && mips_isa_rev < 2)
+ error ("%<-mmips16e2%> requires Release[2,5]");
+
/* Require explicit relocs for MIPS R6 onwards. This enables simplification
of the compact branch and jump support through the backend. */
if (!TARGET_EXPLICIT_RELOCS && mips_isa_rev >= 6)
diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
index dcc39b580f5..8caacb17d7a 100644
--- a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips32r2 -mips16
-mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } {
"-O0" } { "" } } */
/* Test cache. */
diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
index 129ea23b65b..a8a28a4d860 100644
--- a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2
-mbranch-cost=2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2
-mbranch-cost=2" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* Test MOVN. */
diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c
b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c
index 7955472bde3..70d6230f017 100644
--- a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
/* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } }
*/
/* Generate GP-relative ADDIU. */
diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c
b/gcc/testsuite/gcc.target/mips/mips16e2.c
index 166aa742268..1b4b840bb40 100644
--- a/gcc/testsuite/gcc.target/mips/mips16e2.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */
/* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } }
*/
/* ANDI is a two operand instruction. Hence, it won't be generated if src and
--
2.42.0
