On 12/20/23 11:41, Palmer Dabbelt wrote:
I couldn't find another way to set the default code model.
gcc/ChangeLog:
* config.gcc (RISC-V): Add --with-cmodel
* config/riscv/riscv.h (TARGET_DEFAULT_CMODEL): Use
TARGET_RISCV_DEFAULT_CMODEL
OK once its sniff tested.
jeff
On 12/21/23 12:35, Palmer Dabbelt wrote:
On Thu, 21 Dec 2023 11:18:22 PST (-0800), jeffreya...@gmail.com wrote:
On 12/20/23 11:41, Palmer Dabbelt wrote:
I couldn't find another way to set the default code model.
gcc/ChangeLog:
* config.gcc (RISC-V): Add --with-cmodel
* config/ris
On 12/22/23 02:51, Juzhe-Zhong wrote:
Consider this following case:
foo:
ble a0,zero,.L11
lui a2,%hi(.LANCHOR0)
addisp,sp,-128
addia2,a2,%lo(.LANCHOR0)
mv a1,a0
vsetvli a6,zero,e32,m8,ta,ma
vid.v v8
On 12/22/23 01:07, juzhe.zh...@rivai.ai wrote:
You mean theadvector doesn't want the current RVV1.0 register overlap
magic as follows ?
*
The destination EEW is smaller than the source EEW and the overlap
is in the lowest-numbered part of the source register group (e.g.,
when
On 12/23/23 05:39, pan2...@intel.com wrote:
From: Pan Li
This patch would like to XFail the signbit-5 run test case for
the RVV. Given the case has one limitation like "This test does not
work when the truth type does not match vector type." in the beginning
of the test file. Aka, the RVV
On 12/23/23 01:58, YunQiang Su wrote:
On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms,
if 31 or above bits is polluted by an bitops, we will need an
truncate. Let's emit one, and mark let's use the same hardreg
as in and out, the RTL may like:
(insn 21 20 24 2 (set (subre
On 12/23/23 04:07, pan2...@intel.com wrote:
From: Pan Li
This patch would like to XFAIL the test case pr30957-1.c for the RVV when
build the elf with some configurations (list at the end of the log)
It will be vectorized during vect_transform_loop with a variable factor.
It won't benefit fro
On 12/23/23 15:46, YunQiang Su wrote:
Jeff Law 于2023年12月24日周日 00:51写道：
On 12/23/23 01:58, YunQiang Su wrote:
On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms,
if 31 or above bits is polluted by an bitops, we will need an
truncate. Let's emit one, and mark let&
On 12/23/23 17:49, Roger Sayle wrote:
Hi YunQiang (and Jeff),
MIPS claims TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) ==
true based on that the hard register is always sign-extended, but
here the hard register is polluted by zero_extract.
I suspect that the bug here is that the MIPS b
On 12/26/23 19:49, joshua wrote:
Hi Jeff,
Yes, I will change soemthing in vector_csr_operand in the following
patches.
Constraints will be added that the AVL cannot be encoded as an
immediate for xtheadvecotr vsetvl.
Ah. Thanks. Makes sense.
jeff
On 12/26/23 19:47, Kito Cheng wrote:
Thanks Feng, the patch is LGTM from my side, I am happy to accept
vector crypto stuffs for GCC 14, it's mostly intrinsic stuff, and the
only few non-intrinsic stuff also low risk enough (e.g. vrol, vctz)
I won't object. I'm disappointed that we're in a sim
On 12/25/23 01:45, Kito Cheng wrote:
`interrupt` function will backup fcsr register, but it fixed to SImode,
it's not big issue since fcsr only used 8 bits so far, however the
offset should still using UNITS_PER_WORD to prevent the stack offset
become non 8 byte aligned, it will cause problem
On 12/23/23 16:37, Roger Sayle wrote:
One of the cool features of the H8 backend is its use of tables to select
optimal shift implementations for different CPU variants. This patch
borrows (plagiarizes) that idiom for SImode left shifts in the ARC backend
(for CPUs without a barrel-shifter).
On 12/26/23 19:38, Juzhe-Zhong wrote:
Notice we have this following situation:
vsetivlizero,4,e32,m1,ta,ma
vlseg4e32.v v4,(a5)
vlseg4e32.v v12,(a3)
vsetvli a5,zero,e32,m1,tu,ma ---> This is redundant since
VLMAX AVL = 4 when it
On 12/26/23 02:34, pan2...@intel.com wrote:
From: Pan Li
This patch would like to XFAIL the test case pr30957-1.c for the RVV when
build the elf with some configurations (list at the end of the log)
It will be vectorized during vect_transform_loop with a variable factor.
It won't benefit fro
On 12/24/23 01:11, YunQiang Su wrote:
Yes. I also guess so. Any new idea?
Well, I see multiple intertwined issues and I think MIPS has largely
mucked this up.
At a high level DI -> SI truncation is not a nop on MIPS64. We must
explicitly sign extend the value from SI->DI to preserve the in
On 12/28/23 07:59, Roger Sayle wrote:
This patch fixes PR rtl-optmization/104914 by tweaking/improving the way
that fields are written into a pseudo register that needs to be kept sign
extended.
Well, I think "fixes" is a bit of a stretch. We're avoiding the issue
by changing the early RTL
On 12/24/23 05:24, Roger Sayle wrote:
What's exceedingly weird is T_N_T_M_P (DImode, SImode) isn't
actually a truncation! The output precision is first, the input
precision is second. The docs explicitly state the output precision
should be smaller than the input precision (which makes sen
On 12/28/23 17:42, Li, Pan2 wrote:
Thanks Jeff for comments, and Happy new year!
Interesting. So I'd actually peel one more layer off this onion. Why
do the aarch64 and riscv targets generate different constants (0.0 vs
-0.0)?
Yeah, it surprise me too when debugging the foo function. But
On 12/28/23 22:56, Li, Pan2 wrote:
Thanks Jeff.
I think I locate where aarch64 performs the trick here.
1. In the .final we have rtl like
(insn:TI 6 8 29 (set (reg:SF 32 v0)
(const_double:SF -0.0 [-0x0.0p+0]))
"/home/box/panli/gnu-toolchain/gcc/gcc/testsuite/gcc.dg/pr30957-1.c":31
On 12/28/23 19:07, YunQiang Su wrote:
In general, I agree with this change.
When gcc12 on RV64, more than one `sext.w` will be produced with our test.
(Note, use -O1).
There are two things that help here. The first is that the most significant
bit never appears in the middle of a field, so
On 12/29/23 10:46, YunQiang Su wrote:
When we try to combine RTLs, the result may be very complex,
and `rtx_cost` may think that it need lots of costs. But in
fact, it may match a pattern in machine descriptions, which
may emit only 1 or 2 hardware instructions. This combination
may be refuse
On 12/30/23 14:21, Tom Tromey wrote:
When I enable cgen rebuilding in the binutils-gdb tree, the default is
to run cgen using 'guile'. However, on my host, guile is guile 2.2,
which doesn't work for me -- I have to use guile3.0.
This patch arranges to pass "GUILE" down to subdirectories, so
On 12/28/23 21:19, Jun Sha (Joshua) wrote:
This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. We only check the
prefix is 'v', so that no extra attribute is needed.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_asm_output_
On 12/28/23 18:21, Juzhe-Zhong wrote:
This patch fixes the following choosing unexpected big LMUL which cause
register spillings.
Before this patch, choosing LMUL = 4:
addisp,sp,-160
addiw t1,a2,-1
li a5,7
bleut1,a5,.L16
vsetivli
I know we're deep into stage3 and about to transition to stage4. So if
the consensus is for this to wait, I'll understand
This it the V3 of the ext-dce patch based on Joern's work from last year.
Changes since V2:
Handle MINUS
Minor logic cleanup for SUBREGs in ext_dce_process_sets
I
On 1/2/24 06:56, Andreas Schwab wrote:
All new (tsan) tests are working as expected.
* configure.tgt (riscv64-*-linux*): Enable LSan and TSan.
OK
Jeff
On 1/1/24 19:25, Feng Wang wrote:
gcc/ChangeLog:
* config/riscv/vector-crypto.md: Modify copyright year.
---
gcc/config/riscv/vector-crypto.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/vector-crypto.md
b/gcc/config/riscv/vector-crypto.md
i
On 12/30/23 21:34, YunQiang Su wrote:
Right. But that's the whole point behind avoiding the narrowing subreg
and forcing use of a truncate operation.
So basically the question becomes is there a way to modify those bits in
a way that GCC doesn't know that it needs to to truncate/extend?
I
On 12/28/23 12:35, Roger Sayle wrote:
Hi Jeff,
Thanks for the speedy review.
On 12/28/23 07:59, Roger Sayle wrote:
This patch fixes PR rtl-optmization/104914 by tweaking/improving the
way that fields are written into a pseudo register that needs to be
kept sign extended.
Well, I think "fi
On 1/1/24 09:48, YunQiang Su wrote:
When building multilib libraries, CC/CXX etc are set with an option
-B*/lib/, instead of -B/lib/.
This will make some trouble in some case, for example building
cross toolchain based on Debian's cross packages:
If we have libc6-dev-i386-amd64-cross packa
On 12/22/23 12:45, Vineet Gupta wrote:
RVV requires VSET?VL? instructions to dynamically configure VLEN at
runtime. There's a custom pass to do that which has a simple mode
which generates a VSETVL for each V insn and a lazy/optimal mode which
uses LCM dataflow to move VSETVL around, identify/
On 1/1/24 20:22, Hans-Peter Nilsson wrote:
Tested mmix-knuth-mmixware (where all torture-variants of
gcc.dg/torture/inline-mem-cpy-1.c now pass) and native
x86_64-pc-linux-gnu. Also stepped through the test for native,
w/wo. RUN_FRACTION defined to see that it worked as intended.
You may won
On 1/2/24 13:17, trdth...@gmail.com wrote:
From: trdthg
This patch supports Zacas extension.
It includes instruction's machine description and built-in functions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_implied_info): Add zacas extensions.
(riscv
On 10/24/23 12:49, Richard Sandiford wrote:
This patch adds a combine pass that runs late in the pipeline.
There are two instances: one between combine and split1, and one
after postreload.
So have you done any investigation on cases caught by your new pass
between combine and split1 to chara
On 12/19/23 15:17, Jason Merrill wrote:
Tested x86_64-pc-linux-gnu, OK for trunk?
-- 8< --
-Werror=foo implying -Wfoo wasn't working for -Wdeprecated-copy-dtor,
because it is specified as the value 2 of warn_deprecated_copy, which shows
up as CLVC_EQUAL, which is not one of the three var_typ
On 1/2/24 12:41, Ilya Leoshkevich wrote:
gccint recommends using ASM_OUTPUT_FUNCTION_LABEL in
ASM_DECLARE_FUNCTION_NAME, but many implementations use
ASM_OUTPUT_LABEL instead. It's inconsistent and prevents changes to
ASM_OUTPUT_FUNCTION_LABEL from affecting the respective targets.
---
gcc/
On 12/31/23 21:03, Andrew Pinski wrote:
For boolean types, `a ^ b` is a valid form for `a != b`. This means for
gimple_bitwise_inverted_equal_p, we catch some inverted value forms. This
patch extends inverted_equal_p to allow matching of `^` with the
corresponding `==`. Note in the testcase pr
On 1/4/24 06:36, Stefan Schulze Frielinghaus wrote:
I have successfully bootstrapped and regtested the patch on s390. Out
of curiosity I also ran some benchmarks which didn't show much changes
except in one case which I will have to analyze further. If there is
anything interesting I will re
On 1/4/24 02:23, Mikael Pettersson wrote:
emit_library_call_value_1 calls emit_push_insn with NULL_TREE
for TYPE. Sometimes emit_push_insn needs to assign a temp with
that TYPE, which causes a segfault.
Fixed by computing the TYPE from MODE when needed.
Original patch by Thorsten Otto.
gcc
On 1/4/24 02:34, Jakub Jelinek wrote:
Hi!
The following testcase ICEs when rslt is SSA_NAME_OCCURS_IN_ABNORMAL_PHI
and we call replace_uses_by with a INTEGER_CST def, where it ICEs on:
if (e->flags & EDGE_ABNORMAL
&& !SSA_NAME_OCCURS_IN_ABNORMAL_PHI (val))
be
On 1/4/24 02:11, Jakub Jelinek wrote:
Hi!
We expand __builtin_popcount* (x) == 1 as
x ^ (x - 1) > x - 1, either unconditionally in tree-ssa-math-opts.cc
if we don't have a direct optab support for popcount, or during
expansion where we compare the costs of comparison of the popcount
against o
On 1/4/24 20:24, Palmer Dabbelt wrote:
On Thu, 04 Jan 2024 19:17:21 PST (-0800), juzhe.zh...@rivai.ai wrote:
Hi, Wang Feng.
Your patch has some ICEs:
FAIL: gcc.target/riscv/rvv/base/zvbc-intrinsic.c (internal compiler
error: RTL check: expected code 'const_int', have 'reg' in
vlmax_avl_typ
On 1/4/24 13:44, Xi Ruoyao wrote:
I have successfully bootstrapped and regtested the patch on loongarch64-
linux-gnu. The test cases in the patch (intended for RISC-V) also works
on LoongArch per my manual testing.
I find myself wondering if we should create some kind of target-supports
test
On 1/7/24 08:53, Georg-Johann Lay wrote:
Made some tests more generic so they can pass on more targets.
Johann
--
testsuite/52641: Fix fallout from sloppy tests.
gcc/testsuite/
PR testsuite/52641
* gcc.dg/torture/pr110838.c: Use proper shift offset to get MSB or
int.
* gcc
Tester started complaining about this change as soon as it went in.
Clearly there's an extraneous "short" in the testcase.
Pushed to the trunk.
Jeff
commit 66d82874d2254bcb0124f77e6be220d299eab5f1
Author: Jeff Law
Date: Sun Jan 7 09:52:44 2024 -0700
Fix typo
On 1/7/24 10:17, Georg-Johann Lay wrote:
Am 07.01.24 um 17:45 schrieb Jeff Law:
On 1/7/24 08:53, Georg-Johann Lay wrote:
Made some tests more generic so they can pass on more targets.
Johann
--
testsuite/52641: Fix fallout from sloppy tests.
gcc/testsuite/
PR testsuite/52641
On 1/6/24 17:36, Juzhe-Zhong wrote:
Obvious fix, Committed.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
Curious why you made this change -- in general we're moving to
std::{min,max,swap} and away from macro-ized min/max/swap.
Jeff
On 1/3/24 05:07, Richard Sandiford wrote:
+
+ if (GET_CODE (x) == ZERO_EXTRACT)
+ {
+ /* If either the size or the start position is unknown,
+then assume we know nothing about what is overwritten.
+This is overly conservative, but
On 1/5/24 10:35, Richard Sandiford wrote:
Jeff Law writes:
On 10/24/23 12:49, Richard Sandiford wrote:
This patch adds a combine pass that runs late in the pipeline.
There are two instances: one between combine and split1, and one
after postreload.
So have you done any investigation on
On 1/8/24 04:52, Richard Sandiford wrote:
Jeff Law writes:
The other issue that's been in the back of my mind is costing. But I
think the model here is combine without regards to cost.
No, it does take costing into account. For size, it's the usual
"sum up the before
On 1/8/24 09:57, Andrew Pinski wrote:
On Mon, Jan 8, 2024 at 6:44 AM Uros Bizjak wrote:
Instead of converting XOR or PLUS of two values, ANDed with two constants that
have no bits in common, to IOR expression, convert IOR or XOR of said two
ANDed values to PLUS expression.
I think this on
On 1/8/24 09:59, Richard Sandiford wrote:
This is a bit of a hopeful stab, but is the problem that recog_data still
had the previous contents of insn 3674, and so extract_insn_cached wrongly
thought that it doesn't need to do anything? If so, does something like:
diff --git a/gcc/recog.cc
On 1/8/24 12:11, Richard Sandiford wrote:
Thanks. That led me to the following, which seems a bit more plausible
than my first attempt. I'll test it on aarch64-linux-gnu and
x86_64-linux-gnu. Does it look OK?
It looks reasonable to me. I'm going to send another failure (ICE in
finalize_
On 1/7/24 16:07, 钟居哲 wrote:
Since in the previous review from Robin, he have ever asked me change
std::max into MAX,
I thought the policy is preferring MAX instead of std::max.
I change the codes to make them consistent but it seems I am wrong.
So is it reasonable that I change all RVV-rela
On 1/7/24 17:06, Maciej W. Rozycki wrote:
Complement commit c1e8cb3d9f94 ("RISC-V: Rework branch costing model for
if-conversion") and also handle extraneous sign extend operations that
are sometimes produced by `noce_try_cmove_arith' instead of zero extend
operations, making branch costing co
Richard Sandiford debugged a failure on the mn103 port with his
late-combine patches down to the subdi3 pattern not specifying the isa
on alternatives which required newer variants of the chip family.
This patch adds the missing isa attribute and the port now works with
his late-combine patc
to the trunk.
jeffcommit 0beb20c01cf7120c724f9882be41a77e970fe63d
Author: Jeff Law
Date: Tue Jan 9 10:17:54 2024 -0700
[committed] Fix minor bug in epiphany port
So I consider this port dead as it semi-randomly fails in reload due to
unrelated changes earlier in the gimple and R
xstormy16 has failed since the c99 transition due to a missing prototype
for __clzhi2 in the implementation of storm16_count_loaading_zeros.
This fixes the missing prototype. Pushed to the trunk.
jeffcommit 9f7afa99c67f039e43019ebd08d14a7f01e2d89c
Author: Jeff Law
Date: Tue Jan 9 10:21:28
On 1/8/24 03:45, Richard Biener wrote:
On Tue, Jan 2, 2024 at 2:37 PM wrote:
From: Pan Li
According to the sematics of no-signed-zeros option, the backend
like RISC-V should treat the minus zero -0.0f as plus zero 0.0f.
Consider below example with option -fno-signed-zeros.
void
test (fl
On 1/8/24 16:04, 钟居哲 wrote:
This patch looks ok from myside.
Likewise.
So I think the only question for this specific patch is whether or not
it makes sense to include it now or wait for more of the thead bits to
get to acceptance.
I tend to think it should wait since I don't think it ha
On 11/17/23 00:33, Jin Ma wrote:
The XTheadInt ISA extension provides acceleration interruption
instructions as defined in T-Head-specific:
* th.ipush
* th.ipop
Ref:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
gcc/ChangeLog:
On 1/9/24 01:52, Jakub Jelinek wrote:
Hi!
The copy attributes is allowed on decls as well as types and even has
checks whether decl (set to *node) is DECL_P or TYPE_P, but for diagnostics
unconditionally uses DECL_SOURCE_LOCATION (decl), which obviously only works
if it applies to a decl.
Th
On 1/8/24 06:47, Kito Cheng wrote:
Do you know how to build a ISA string with following extension?
- g
- c
- zba
- zbs
- svnapot
- zve64d
- zvl128b
Don't trial and error with your gcc and don't read RISC-V ISA spec! OK, I
believe it's impossible for most people, even I work for RISC-V so ma
On 1/8/24 06:14, Mary Bennett wrote:
Spec:
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
Contributors:
Mary Bennett
Nandni Jamnadas
Pietra Ferreira
Charlie Keaney
Jessica Mills
Craig Blackmore
Simon Cook
Jeremy Bennett
Hele
On 1/5/24 09:28, Richard Sandiford wrote:
function.cc emits a NOTE_FUNCTION_BEG after all arguments have
been copied to pseudos. It then records this note in parm_birth_insn.
Various other pieces of code use this insn as a convenient place to
insert things at the start of the function.
Howev
On 1/3/24 16:39, Richard Sandiford wrote:
YunQiang Su writes:
On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms,
if 31 or above bits is polluted by an bitops, we will need an
truncate. Let's emit one, and mark let's use the same hardreg
as in and out, the RTL may like:
(i
On 1/2/24 12:41, Ilya Leoshkevich wrote:
GCC can emit code between the function label and the .LASANPC label,
making the latter unaligned. Some architectures cannot load unaligned
labels directly and require literal pool entries, which is inefficient.
Move the invocation of asan_function_sta
On 1/6/24 01:59, Jakub Jelinek wrote:
Hi!
The following testcase ICEs (on ARM/RISCV with certain options), because niters
analysis
computes number of latch executions for the loop as
(short unsigned int) (a.0_1 + 255) + 1 > 256 ? ~(short unsigned int) (a.0_1 +
255) : 0
where a.0_1 is unsign
On 11/29/23 10:37, Joern Rennecke wrote:
Why did you leave out MINUS from safe_for_live_propagation ?
As Jivan noted, mistake on my part.
jeff
On 11/29/23 02:33, Xi Ruoyao wrote:
On Mon, 2023-11-27 at 23:06 -0700, Jeff Law wrote:
This has (of course) been tested on rv64. It's also been bootstrapped
and regression tested on x86. Bootstrap and regression tested (C only)
for m68k, sh4, sh4eb, alpha. Earlier versions were
On 11/29/23 19:39, Joern Rennecke wrote:
On Wed, 29 Nov 2023 at 20:05, Joern Rennecke
wrote:
I suspect it'd be more useful to add handling of LSHIFTRT and ASHIFTRT
. Some ports do
a lot of static shifting.
+case SS_ASHIFT:
+case US_ASHIFT:
+ if (!mask || XEXP (x, 1) == cons
On 11/28/23 06:36, Joern Rennecke wrote:
On Mon, 27 Nov 2023 at 20:18, Jeff Law wrote:
On 11/27/23 13:03, Richard Sandiford wrote:
Joern Rennecke writes:
On 11/20/23 11:26, Richard Sandiford wrote:
+ /* ?!? What is the point of this adjustment to DST_MASK? */
+ if (code
On 11/29/23 19:39, Joern Rennecke wrote:
On Wed, 29 Nov 2023 at 20:05, Joern Rennecke
wrote:
I suspect it'd be more useful to add handling of LSHIFTRT and ASHIFTRT
. Some ports do
a lot of static shifting.
+case SS_ASHIFT:
+case US_ASHIFT:
+ if (!mask || XEXP (x, 1) == const0
On 11/30/23 11:31, Joern Rennecke wrote:
Pretending the vector modes don't happen is not making the code safe.
We have to handle them somehow, so we might as well do that in a way
that is consistent and gives more potential for optimization.
We're not pretending they don't happen. Quite the
On 11/30/23 14:22, Jeff Law wrote:
So if you're going to add opcodes in here, don't they also need to be in
safe_for_propagation_p as well? Otherwise they won't get used, right?
I'm thinking about the HIGHPART cases for example. As well as the
saturating shifts which
On 11/30/23 15:22, Robin Dapp wrote:
Hi,
this adds vectorized implementations of strcmp and strncmp as well as
strlen. strlen falls back to the previously implemented rawmemchr.
Also, it fixes a rawmemchr bug causing a SPEC2017 execution failure:
We would only ever increment the source addre
On 11/30/23 10:27, Hans-Peter Nilsson wrote:
My plan was to split up the test case in one which is for
-Wstringop-overflow and one which is for -Wnonnull and then
one could turn off the -Wstringop-overflow for the tests
which are actually for -Wnonnull. But adding the dg-blah
would certain
On 12/1/23 03:26, Jakub Jelinek wrote:
Hi!
In
https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html#index-_005f_005fbuiltin_005fstdc_005fbit_005ffloor
I've noticed that while e.g. __builtin_stdc_bit_floor builtin is properly
rendered in bold and bigger size, for the __builtin_stdc_bit_width
On 11/30/23 18:08, Hans-Peter Nilsson wrote:
Date: Sun, 19 Nov 2023 17:47:56 -0700
From: Jeff Law
Locally we have had this enabled at -O1 and above to encourage testing,
but I'm thinking that for the trunk enabling at -O2 and above is the
right thing to do.
Yes.
Thoughts, com
On 12/1/23 18:13, Sam James wrote:
钟居哲 writes:
Hi, This patch cause error on building newlib/glibc/musl on RISC-V port:
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib/libgloss/riscv/sys_access.c:8:40:
error: passing argument
On 12/1/23 22:47, Sam James wrote:
Jeff Law writes:
On 12/1/23 18:13, Sam James wrote:
钟居哲 writes:
Hi, This patch cause error on building newlib/glibc/musl on RISC-V port:
/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zvfh_zfh-lp64d-medany-newlib-spike-debug/../../newlib
prototype is added
into frvbegin.c to fix that problem.
That's enough to get the compiler building again.
Pushed to the trunk,
Jeffcommit 870b63fe71607b94c0e5b0c6e61cd807e0216ddd
Author: Jeff Law
Date: Sat Dec 2 21:54:36 2023 -0700
[committed] Fix frv build after C99 changes
tests.
Pushed to the trunk,
Jeff
commit 622c5356676caec1dc970869d6671244703f0559
Author: Jeff Law
Date: Sat Dec 2 22:03:28 2023 -0700
[committed] Fix minor testsuite problems on H8 after C99 changes
Two minor regressions on the H8 were triggered by the C99 changes. First
f1fdd2839ccbc1028b59fbaa7f342e41e3bef848
Author: Jeff Law
Date: Sat Dec 2 22:07:59 2023 -0700
[committed] Fix rx build failure in libgcc
The rx port has a bunch of what I presume are ABI compatibility functions in
libgcc. Those compatibility functions routines such as __eqdf2 from libgcc,
but without a
uthor: Jeff Law
Date: Sat Dec 2 22:12:55 2023 -0700
[committed] Fix nios2 tests
The nios2 port has two tests that are affected by the recent changes. In
cdx-ldstwm-1.c it was easiest to just add -fpermissive. for cdx-ldstwm-2.c
adding an prototype for exit and abort is all t
Similar to others. Where it's easy to fix the implicit types or add
prototypes I did. One was just ugly and I didn't want to think too
hard, so I just added -fpermissive.
Pushed to the trunk.
Jeff
commit 595c695216e72c8491bf20d30e5298e2064caa73
Author: Jeff Law
Date: Sat D
Jeffcommit d5c823b033bb6409bbcd115b318093126f5a674f
Author: Jeff Law
Date: Sat Dec 2 22:32:22 2023 -0700
[committed] Fix comp-goto-1.c on 16 bit targets
I don't remember what port triggered this, but it's obviously that
comp-goto-1.c needs to be fixed.
Basically the test has two implementat
Pushed to the trunk.
Jeffcommit 3da08ffa6df2634092a6292b045568fc326e28e6
Author: Jeff Law
Date: Sat Dec 2 22:40:41 2023 -0700
[committed] Fix pr65369.c
There's a caller/callee type mismatch in this test that shows up on targets
where ints are something other than 32 bit t
1a81e
Author: Jeff Law
Date: Sat Dec 2 22:45:48 2023 -0700
[committed] Fix build of libgcc on ports using FDPIC
read_encoded_value_with_base has an ifdef'd code path conditional on
__FDPIC__
which was calling _Unwind_gnu_Find_got without a prototype. This naturally
caus
Jeffcommit f37744662cbc74efcceb790b99dcd6521c51a578
Author: Jeff Law
Date: Sat Dec 2 22:54:46 2023 -0700
[committed] Fix gnu23-builtins-no-dfp
Last patch for the night. There's still a bit of minor fallout left in GCC
(loongarch testsuite for example). But things are looking good on the
tar
On 12/3/23 05:23, Thomas Schwinge wrote:
Hi!
On 2023-12-03T08:41:59+0100, Florian Weimer wrote:
* Jeff Law:
Anyway, this test was the one I was most concerned about. Basically
we're testing that on a !dfp target that the builtins are not available.
It expects a warning, but ge
On 12/4/23 06:17, Robin Dapp wrote:
Hi,
recent -std changes caused testsuite failures. Fix those by adding
-std=gnu99 and -Wno-incompatible-pointer-types.
Going to commit as obvious.
Regards
Robin
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr112552.c: Add
-
effcommit b544ec681bdc9c48587d2e014f9559674097738a
Author: Jeff Law
Date: Mon Dec 4 10:06:49 2023 -0700
[committed] Fix HImode load mnemonic on microblaze port
The tester recently started failing va-arg-22.c on microblaze-linux:
gcc.c-torture/execute/va-arg-22.c -O0 (test
On 12/4/23 18:38, Vincenzo Palazzo wrote:
Ciao all,
+1. I think this is best left to the distros.
What do you mean? this is not a package, it is an env shell in order
to build an work on GCC on NixOS.
Distro build procedures are not something the GCC project generally gets
involved with
On 12/4/23 18:02, Andrew Pinski wrote:
On Mon, Dec 4, 2023 at 4:58 PM Vincenzo Palazzo
wrote:
This commit is specifically targeting enhancements in
Nix support for GCC development. This initiative stems
from the recognized need within our community for a more
streamlined and efficient devel
On 12/6/23 05:12, Florian Weimer wrote:
* Yang Yujie:
From: Yang Yujie
Subject: [PATCH] testsuite: Adjust for the new permerror
-Wincompatible-pointer-types
To: gcc-patches@gcc.gnu.org
Cc: r...@cebitec.uni-bielefeld.de, mikest...@comcast.net, fwei...@redhat.com,
Yang Yujie
Date: Wed,
On 12/6/23 03:04, Jakub Jelinek wrote:
Hi!
When libgcc is being built in --disable-tls configuration or on
a target without native TLS support, one gets annoying warnings:
../../../../libgcc/emutls.c:61:7: warning: conflicting types for built-in
function ‘__emutls_get_address’; expected ‘voi
On 12/5/23 09:41, Eric Gallager wrote:
On GitHub, Joseph Myers (@jsm28 there) says in MentorEmbedded/qmtest#1
that the qmtest-related targets should have been removed long ago. This
patch does so.
Ref:
https://github.com/MentorEmbedded/qmtest/issues/1
gcc/ChangeLog:
* Makefile.in: R
On 12/5/23 08:30, Kito Cheng wrote:
index 7d7b952d817..e7d4ad1760c 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -27,6 +27,25 @@
;;CORE-V EVENT LOAD
UNSPECV_CV_ELW
+
+ ;;CORE-V BITMANIP
+ UNSPEC_CV_BITMANIP_EXTRACT
+ UNSPEC_CV_BITMANIP_EXTRACT_INSN
+ UN
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