On 12/26/23 19:49, joshua wrote:
Hi Jeff, Yes, I will change soemthing in vector_csr_operand in the following patches.
Constraints will be added that the AVL cannot be encoded as an immediate for xtheadvecotr vsetvl.
Ah. Thanks. Makes sense. jeff
- [PATCH v3 0/6] RISC-V: Support XTheadVector extension Jun Sha (Joshua)
- [PATCH v3 1/6] RISC-V: Refactor riscv-vector-bui... Jun Sha (Joshua)
- [PATCH v3 2/6] RISC-V: Split csr_operand in pred... Jun Sha (Joshua)
- Re: [PATCH v3 2/6] RISC-V: Split csr_operand... Jeff Law
- 回复：[PATCH v3 2/6] RISC-V: Split csr_oper... joshua
- Re: 回复：[PATCH v3 2/6] RISC-V: Split ... Jeff Law
- [PATCH v3 3/6] RISC-V: Introduce XTheadVector as... Jun Sha (Joshua)
- [PATCH v3 4/6] RISC-V: Adds the prefix "th.... Jun Sha (Joshua)
- Re: [PATCH v3 4/6] RISC-V: Adds the prefix &... Jeff Law
- [PATCH v4 4/6] RISC-V: Adds the prefix "... Jun Sha (Joshua)
- Re: [PATCH v4 4/6] RISC-V: Adds the pref... juzhe.zh...@rivai.ai
- 回复：[PATCH v4 4/6] RISC-V: Adds the p... joshua
- Re: 回复：[PATCH v4 4/6] RISC-V: A... juzhe.zh...@rivai.ai
