Re: [PATCH] Remove poly_int_pod

On 9/28/23 11:26, Jason Merrill wrote: On 9/28/23 05:55, Richard Sandiford wrote: poly_int was written before the switch to C++11 and so couldn't use explicit default constructors.  This led to an awkward split between poly_int_pod and poly_int.  poly_int simply inherited from poly_int_pod an

Re: [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466]

On 9/28/23 15:43, Vineet Gupta wrote: RISC-V suffers from extraneous sign extensions, despite/given the ABI guarantee that 32-bit quantities are sign-extended into 64-bit registers, meaning incoming SI function args need not be explicitly sign extended (so do SI return values as most ALU insns

Re: [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466]

On 9/28/23 21:49, Vineet Gupta wrote: On 9/28/23 20:17, Jeff Law wrote: I can bootstrap & regression test alpha using QEMU user mode emulation. So we might be able to trigger something that way. It'll take some time, but might prove fruitful. That would be awesome. It's

Re: [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466]

On 9/29/23 04:40, Roger Sayle wrote: I agree that this looks dubious. Normally, if the middle-end/optimizers wish to reuse a SUBREG in a context where the flags are not valid, it should create a new one with the desired flags, rather than "mutate" an existing (and possibly shared) RTX. SUBRE

Re: committed [RISC-V]: Harden test scan patterns

On 9/27/23 17:21, Vineet Gupta wrote: On 9/27/23 13:14, Jeff Law wrote: It would help to describe how these patterns were under specified so that folks don't continue to make the same mistake as new tests get added. dg-final scan-assembler, scan-assembler-not, and scan-assembler-

Re: [PING] [PATCH] Harmonize headers between both dg-extract-results scripts

On 9/29/23 02:19, Paul Iannetta wrote: On Tue, Sep 26, 2023 at 08:29:11AM -0600, Jeff Law wrote: On 9/25/23 03:55, Paul Iannetta wrote: On Mon, Sep 18, 2023 at 08:39:34AM +0200, Paul Iannetta wrote: On Thu, Sep 14, 2023 at 04:24:33PM +0200, Paul Iannetta wrote: Hi, This is a small

Re: [PATCH]middle-end match.pd: optimize fneg (fabs (x)) to x | (1 << signbit(x)) [PR109154]

On 9/26/23 18:50, Tamar Christina wrote: Hi All, For targets that allow conversion between int and float modes this adds a new optimization transforming fneg (fabs (x)) into x | (1 << signbit(x)). Such sequences are common in scientific code working with gradients. The transformed instructi

Re: [PATCH] Testsuite, DWARF2: adjust regexp to match darwin output

On 9/20/23 07:53, FX Coudert wrote: ping**2 Hi, This was a painful one to fix, because I hate regexps, especially when they are quoted. On darwin, we have this failure: FAIL: gcc.dg/debug/dwarf2/inline4.c scan-assembler DW_TAG_inlined_subroutine[^(]*([^)]*)[^(]*\

Re: [RFC 1/2] RISC-V: Add support for _Bfloat16.

On 9/19/23 02:44, Jin Ma wrote: gcc/ChangeLog: * config/riscv/iterators.md (HFBF): New. * config/riscv/riscv-builtins.cc (riscv_init_builtin_types): Initialize data type_Bfloat16. * config/riscv/riscv-modes.def (FLOAT_MODE): New. (ADJUST_FLOAT_FORMAT):

Re: [RFC 2/2] RISC-V: Add 'Zfbfmin' extension.

On 9/19/23 02:46, Jin Ma wrote: This patch adds the 'Zfbfmin' extension for riscv, which is based on spec of bfloat16: https://github.com/riscv/riscv-bfloat16/commit/5578e34e15a44e9ad13246072a29f51274b4d999 The 'Zfbfmin' extension of binutils-gdb (REVIEW ONLY): https://sourceware.org/piperma

Re: [PATCH v6] RISC-V:Optimize the MASK opt generation

On 9/29/23 12:05, Kito Cheng wrote: Hi Jeff: Could you take a look for this? RISC-V part is ok to me. Thanks :) Yea, I've got two things on my list to review from a doc standpoint. This is one of 'em. jeff

Re: PING^5: [PATCH] rtl-optimization/110939 Really fix narrow comparison of memory and constant

On 9/19/23 10:06, Stefan Schulze Frielinghaus wrote: Since this patch is sitting in the queue for quite some time and (more importantly?) solves a bootstrap problem let me reiterate: While writing the initial commit 7cdd0860949c6c3232e6cff1d7ca37bb5234074c and the subsequent (potential) fix 4

Re: [PATCH] rtl-optimization/110939 Really fix narrow comparison of memory and constant

On 8/10/23 07:04, Stefan Schulze Frielinghaus via Gcc-patches wrote: In the former fix in commit 41ef5a34161356817807be3a2e51fbdbe575ae85 I completely missed the fact that the normal form of a generated constant for a mode with fewer bits than in HOST_WIDE_INT is a sign extended version of the

Re: [PATCH] check_GNU_style.py: Skip .md square bracket linting

On 9/12/23 12:54, Patrick O'Neill wrote: This testcase causes lots of false-positives for machine description files. contrib/ChangeLog: * check_GNU_style_lib.py: Skip machine description file bracket linting. OK. We probably need a completely separate checker for for .md files. j

Re: [PATCH v5] Implement new RTL optimizations pass: fold-mem-offsets.

On 9/12/23 04:13, Manolis Tsamis wrote: + +/* Get the single reaching definition of an instruction inside a BB. + The definition is desired for REG used in INSN. + Return the definition insn or NULL if there's no definition with + the desired criteria. */ +static rtx_insn* +get_single_

Re: [PATCH v6] RISC-V:Optimize the MASK opt generation

On 9/12/23 03:18, Feng Wang wrote: New patch add some comments and update docs for this new usage. --- Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)" to generate MASK and TARGET MACRO automatically. This patch improve the MACRO generation of MASK_* and TARGET_*. Due to the

Re: [V2] RISC-V: Replace not + bitwise_imm with li + bitwise_not

On 9/12/23 13:09, Jivan Hakobyan via Gcc-patches wrote: In the case when we have C code like this int foo (int a) { return 100 & ~a; } GCC generates the following instruction sequence foo: not a0,a0 andia0,a0,100 ret This patch replaces that with this sequence

Re: [PATCH] ssa_name_has_boolean_range vs signed-boolean:31 types

On 9/5/23 01:46, Andrew Pinski wrote: On Tue, Sep 5, 2023 at 12:09 AM Jeff Law via Gcc-patches wrote: On 9/1/23 20:32, Andrew Pinski via Gcc-patches wrote: This turns out to be a latent bug in ssa_name_has_boolean_range where it would return true for all boolean types but all of the

Re: [PATCH 2/2] VR-VALUES: Rewrite test_for_singularity using range_op_handler

On 9/5/23 01:12, Andrew Pinski wrote: On Mon, Sep 4, 2023 at 11:06 PM Jeff Law via Gcc-patches wrote: On 9/1/23 11:30, Andrew Pinski via Gcc-patches wrote: So it turns out there was a simplier way of starting to improve VRP to start to fix PR 110131, PR 108360, and PR 108397. That was

Re: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook

On 8/25/23 06:44, Li, Pan2 wrote: Hi Jeff, You might also peek at the RTL gcse/pre code which is also LCM based and has the same class of problems. I found a similar approach to take care of this in gcse.cc/pre_edge_insert with some comments as below. /* We can't insert anything on an

Re: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook

On 8/23/23 22:53, Li, Pan2 wrote: Thanks Jeff. That implies a save/restore pair around the call (possibly optimized so that we minimize the number of save/restores). I would have expected x86 to already be doing this. But maybe there's some ABI thing around mmx vs x86 state that allows it

Re: [PATCH] RISC-V/testsuite: Fix ILP32 RVV failures from missing

On 9/28/23 03:46, Maciej W. Rozycki wrote: On Wed, 27 Sep 2023, Jeff Law wrote: IMO this is one of those places where we should just be as normal as possible.  So if the other big ports allow system headers then we should, otherwise we should move everyone over to testing in some way we&#x

Re: [PATCH] RISC-V: Specify -mabi=lp64d in wredsum_vlmax.c testcase

On 9/29/23 15:37, Patrick O'Neill wrote: Resolves this error on rv32gcv: cc1: error: ABI requires '-march=rv32' compiler exited with status 1 FAIL: gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c -O0 (test for excess errors) Tested for regressions using glibc rv32gcv/rv64gcv multilib on r14-4

Re: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu (i.e. carry_flag ? 1 : 0)

On 9/29/23 15:11, Roger Sayle wrote: Hi Claudiu, The patch looks sane. Have you run dejagnu test suite? I've not yet managed to set up an emulator or compile the entire toolchain, so my dejagnu results are only useful for catching (serious) problems in the compile only tests:

[committed] RISC-V: Fix INSN costing and more zicond tests

So this ends up looking a lot like the bits that I had to revert several weeks ago :-) The core issue we have is given an INSN the generic code will cost the SET_SRC and SET_DEST and sum them. But that's far from ideal on a RISC target. For a register destination, the cost can be determin

Re: RISC-V: Add type attribute in *_not_const pattern

On 9/29/23 16:53, Jivan Hakobyan wrote: After f088b768d01a commit riscv_sched_variable_issue function requires that all insns should have a type attribute. When I sent my previous patch there was no such limitation. Currently, I have regressions on my tests. This patch fixes them. gcc/Change

Re: [PATCH] rtl-optimization/110939 Really fix narrow comparison of memory and constant

On 10/1/23 08:26, Stefan Schulze Frielinghaus wrote: FWIW, I should definitely have caught this hunk earlier -- we've gone the rounds in this same space (GEN_INT vs gen_int_mode) elsewhere. Again, sorry for the long wait. jeff No worries at all. At least I have learned something new :)

Re: [PATCH v3] RISC-V:Optimize the MASK opt generation

On 10/2/23 11:20, David Edelsohn wrote: Wang, The AWK portions of this patch broke bootstrap on AIX. Also, the AWK portions are common code, not RISC-V specific.  I don't see anywhere that the common portions of the patch were reviewed or approved by anyone with authority to approve the ch

Re: [PATCH v3] RISC-V:Optimize the MASK opt generation

On 10/2/23 12:03, David Edelsohn wrote: On Mon, Oct 2, 2023 at 1:59 PM Jeff Law <mailto:jeffreya...@gmail.com>> wrote: On 10/2/23 11:20, David Edelsohn wrote: > Wang, > > The AWK portions of this patch broke bootstrap on AIX. > > Al

Re: [committed] Require target lra in gcc.dg/pr108095.c

On 10/2/23 14:42, John David Anglin wrote: Committed to trunk. Dave --- Require target lra in gcc.dg/pr108095.c 2023-10-02 John David Anglin gcc/testsuite/ChangeLog: * gcc.dg/pr108095.c: Require target lra. Thanks. I already had this in my local tree. jeff

Re: PING: PR rtl-optimization/110701

On 10/3/23 09:55, Roger Sayle wrote: There are a small handful of middle-end maintainers/reviewers that understand and appreciate the difference between the RTL statements: (set (subreg:HI (reg:SI x)) (reg:HI y)) and (set (strict_lowpart:HI (reg:SI x)) (reg:HI y)) If one (or more) of them

Re: [PATCH v3] RISC-V:Optimize the MASK opt generation

On 10/2/23 20:38, Kito Cheng wrote: Proposed fix, and verified with "mawk" and "gawk -P" (gawk with posix mode) on my linux also some other report it work on freebsd, just wait review :) https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631785.html OK jeff

Re: mvconst_internal splitter gated with !@ira_in_progess (was Re: Yet Another IRA question)

On 10/2/23 18:12, Vineet Gupta wrote: On 9/28/23 12:52, Vineet Gupta wrote: On 9/28/23 05:53, Jeff Law wrote: Vineet -- assuming Vlad's patch goes in, the other obvious candidate for this would be the mvconst_internal define_insn_and_split where we'd probably want to reject t

Re: [PATCH] RISC-V: Unescape chars in pr111566.f90 test

On 10/3/23 14:19, Patrick O'Neill wrote: Some characters are escaped which causes the testcase to fail. This patch restores the original characters. Tested for regressions using multilib rv32gcv-ilp32d, rv64gcv-lp64d. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/fortran/pr111566.

Re: [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466]

On 9/28/23 15:43, Vineet Gupta wrote: RISC-V suffers from extraneous sign extensions, despite/given the ABI guarantee that 32-bit quantities are sign-extended into 64-bit registers, meaning incoming SI function args need not be explicitly sign extended (so do SI return values as most ALU insns

Re: [PATCH] RISC-V: Remove @ of vec_series

On 10/4/23 09:06, Robin Dapp wrote: I'm currently in the process of removing some unused @s. This is OK. Agreed. And if you or Juzhe have other @ cases that are unused, such changes should be considered pre-approved. Jeff

Re: [RFC gcc13 backport 0/3] Add Ztso atomic mappings

using rv32gc/rv64gc glibc. Jeff Law (1): [RISCV][committed] Remove spurious newline in ztso sequence Patrick O'Neill (2): RISC-V: Add Ztso atomic mappings RISC-V: Specify -mabi for ztso testcases I recall discussing Ztso mappings, but not the final conclusion. I think the final deci

Re: [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466]

On 9/28/23 15:43, Vineet Gupta wrote: RISC-V suffers from extraneous sign extensions, despite/given the ABI guarantee that 32-bit quantities are sign-extended into 64-bit registers, meaning incoming SI function args need not be explicitly sign extended (so do SI return values as most ALU insns

Re: [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466]

On 10/4/23 12:14, Vineet Gupta wrote: On 10/4/23 10:59, Jeff Law wrote: On 9/28/23 15:43, Vineet Gupta wrote: RISC-V suffers from extraneous sign extensions, despite/given the ABI guarantee that 32-bit quantities are sign-extended into 64-bit registers, meaning incoming SI function args

Re: [PATCH v6] Implement new RTL optimizations pass: fold-mem-offsets.

On 10/3/23 05:45, Manolis Tsamis wrote: This is a new RTL pass that tries to optimize memory offset calculations by moving them from add immediate instructions to the memory loads/stores. For example it can transform this: addi t4,sp,16 add t2,a6,t4 shl t3,t2,1 ld a2,0(t3)

Re: [PATCH] RISC-V: xfail gcc.dg/pr90263.c for riscv_v

On 10/4/23 15:57, Patrick O'Neill wrote: Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to perform a memcpy. We no longer expect memcpy for riscv_v targets. gcc/testsuite/ChangeLog: * gcc.dg/pr90263.c: xfail riscv_v targets. Or rather than XFAIL skip the test? X

Re: [PATCH] RISC-V: xfail gcc.dg/pr90263.c for riscv_v

On 10/4/23 16:21, Patrick O'Neill wrote: On 10/4/23 15:14, Jeff Law wrote: On 10/4/23 15:57, Patrick O'Neill wrote: Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to perform a memcpy. We no longer expect memcpy for riscv_v targets. gcc/testsuite

Re: [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466]

On 9/28/23 15:43, Vineet Gupta wrote: RISC-V suffers from extraneous sign extensions, despite/given the ABI guarantee that 32-bit quantities are sign-extended into 64-bit registers, meaning incoming SI function args need not be explicitly sign extended (so do SI return values as most ALU insns

Re: [PATCH v6] Implement new RTL optimizations pass: fold-mem-offsets.

On 10/3/23 05:45, Manolis Tsamis wrote: This is a new RTL pass that tries to optimize memory offset calculations + +/* If INSN is a root memory instruction then compute a potentially new offset + for it and test if the resulting instruction is valid. */ +static void +do_check_validity (r

Re: [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466]

On 10/5/23 08:56, Richard Kenner wrote: At that particular time I think Kenner was mostly focused on the alpha and ppc ports, but I think he was also still poking around with romp and a29k. I think romp is an unlikely target for this because it didn't promote modes and it wasn't even building

Re: [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466]

On 10/5/23 07:33, Robin Dapp wrote: So I think Kenner's code is trying to prevent having a value in a SUBREG that is inconsistent with the SUBREG_PROMOTED* flag bits. But I think it's been unnecessary since Matz's rewrite in 2009. I couldn't really tell what the rewrite does entirely so I t

Re: [PATCH v2] RISC-V: Test memcpy inlined on riscv_v

On 10/4/23 16:55, Patrick O'Neill wrote: Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to perform a memcpy. We no longer expect memcpy for riscv_v targets. gcc/testsuite/ChangeLog: * gcc.dg/pr90263.c: Skip riscv_v targets. * gcc.target/riscv/rvv/base/pr9

Re: [PATCH V2] Emit funcall external declarations only if actually used.

On 10/5/23 16:17, Richard Sandiford wrote: "Jose E. Marchesi" writes: ping I don't know this code very well, and have AFAIR haven't worked with an assembler that requires external declarations, but since it's at a second ping :) ping [Differences from V1: - Prototype for call_from_ca

Re: [PATCH] RISC-V: Use stdint-gcc.h in rvv testsuite

On 10/3/23 14:58, Patrick O'Neill wrote: On 10/2/23 06:57, Kito Cheng wrote: On Tue, Sep 26, 2023 at 10:59 AM Patrick O'Neill wrote: stdint.h can be replaced with stdint-gcc.h to resolve some missing system headers in non-multilib installations. Tested using glibc rv32gcv and rv64gcv on r

Re: [PATCH v6] Implement new RTL optimizations pass: fold-mem-offsets.

On 10/6/23 08:17, Manolis Tsamis wrote: SNIP So I was ready to ACK, but realized there weren't any testresults for a primary platform mentioned. So I ran this on x86. It's triggering one regression (code quality). Specifically gcc.target/i386/pr52146.c The f-m-o code is slightly worse than

Re: [PATCH v2] RISC-V: const: hide mvconst splitter from IRA

On 10/6/23 11:49, Vineet Gupta wrote: Vlad recently introduced a new gate @ira_in_progress, similar to counterparts @{reload,lra}_in_progress. Use this to hide the constant synthesis splitter from being recog* () by IRA register equivalence logic which is eager to undo the splits, generating

Re: [PATCH v1] RISC-V: Bugfix for legitimize address PR/111634

On 10/6/23 22:49, pan2...@intel.com wrote: From: Pan Li Given we have RTL as below. (plus:DI (mult:DI (reg:DI 138 [ g.4_6 ]) (const_int 8 [0x8])) (lo_sum:DI (reg:DI 167) (symbol_ref:DI ("f") [flags 0x86] ) )) When handling (plus (plus (mult

Re: [PATCH] TEST: Fix XPASS of TSVC testsuites for RVV

On 10/7/23 03:23, Juzhe-Zhong wrote: Fix these following XPASS FAILs of TSVC for RVV: XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1115.c -flto -ffat-lto-objects scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/vect/tsvc/vect-tsvc-s1115.c scan-tree-dump vect "vectorized 1 loops" XPASS: gcc.dg/

Re: [PATCH] RISC-V: Enable more tests of "vect" for RVV

On 10/7/23 01:04, Juzhe-Zhong wrote: This patch enables almost full coverage vectorization tests for RVV, except these following tests (not enabled yet): 1. Will enable soon: check_effective_target_vect_call_lrint check_effective_target_vect_call_btrunc check_effective_target_vect_call_btru

Re: [PATCH] TEST: Fix vect_cond_arith_* dump checks for RVV

On 10/7/23 05:45, Juzhe-Zhong wrote: This patch fixes the following dumple FAILs: FAIL: gcc.dg/vect/vect-cond-arith-2.c -flto -ffat-lto-objects scan-tree-dump optimized " = \\.COND_SUB" FAIL: gcc.dg/vect/vect-cond-arith-2.c -flto -ffat-lto-objects scan-tree-dump vect " = \\.COND_ADD" FAIL:

Re: [PATCH] RISC-V: add static-pie support

On 10/7/23 05:32, yanzhang.w...@intel.com wrote: From: Yanzhang Wang We only need to pass options to the linker when static-pie is passed. There's another patch to enable static-pie in glibc. And we need to enable in GCC first. gcc/ChangeLog: * config/riscv/linux.h: Pass the static

Re: [PATCH] Support g++ 4.8 as a host compiler.

On 10/4/23 16:19, Roger Sayle wrote: The recent patch to remove poly_int_pod triggers a bug in g++ 4.8.5's C++ 11 support which mistakenly believes poly_uint16 has a non-trivial constructor. This in turn prohibits it from being used as a member in a union (rtxunion) that constructed statical

Re: [PATCH] Support g++ 4.8 as a host compiler.

On 10/7/23 15:30, Sam James wrote: Jeff Law writes: On 10/4/23 16:19, Roger Sayle wrote: The recent patch to remove poly_int_pod triggers a bug in g++ 4.8.5's C++ 11 support which mistakenly believes poly_uint16 has a non-trivial constructor. This in turn prohibits it from being us

Re: [PATCH] TEST: Fix dump FAIL of vect-multitypes-16.c for RVV

On 10/8/23 05:35, Juzhe-Zhong wrote: RVV (RISC-V Vector) doesn't enable vect_unpack, but we still vectorize this case well. So, adjust dump check for RVV. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-multitypes-16.c: Fix dump FAIL of RVV. I'd hoped to avoid a bunch of risc-v special

Re: [PATCH] TEST: Fix vect_cond_arith_* dump checks for RVV

On 10/7/23 16:02, 钟居哲 wrote: Do you mean change it like this ? /* { dg-final { scan-tree-dump-times { = \.COND_L?E?N?_?RDIV} 1 "optimized" { target vect_double_cond_arith } } } */ I was thinking something more like COND(_LEN)?_ADD The idea being we match _LEN conditionally as a group. jef

Re: [PATCH] RISC-V: THead: Fix missing CFI directives for th.sdd in prologue.

On 10/4/23 01:49, Xianmiao Qu wrote: From: quxm When generating CFI directives for the store-pair instruction, if we add two parallel REG_FRAME_RELATED_EXPR expr_lists like (expr_list:REG_FRAME_RELATED_EXPR (set (mem/c:DI (plus:DI (reg/f:DI 2 sp) (const_int 8 [0x8])) [1 S8 A64])

Re: [PATCH] RISC-V Regression test: Adapt SLP tests like ARM SVE

On 10/9/23 07:37, Juzhe-Zhong wrote: Like ARM SVE, RVV is vectorizing these 2 cases in the same way. gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-23.c: Add RVV like ARM SVE. * gcc.dg/vect/slp-perm-10.c: Ditto. OK jeff

Re: [PATCH] RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV

On 10/9/23 07:39, Juzhe-Zhong wrote: RVV vectorize it with stride5 load_lanes. gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-perm-4.c: Adapt test for stride5 load_lanes. OK. As a follow-up, would it make sense to test the .vect dump for something else in the ! {vec_load_lanes && vect

Re: [PATCH] RISC-V Regression test: Fix FAIL of slp-reduc-4.c for RVV

On 10/9/23 07:41, Juzhe-Zhong wrote: RVV vectortizes this case with stride8 load_lanes. gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-reduc-4.c: Adapt test for stride8 load_lanes. OK. Similar question as my last ack. Do we want a follow-up here which tests the .vect dump for the ! {

Re: [PATCH] RISC-V Regression test: Fix FAIL of slp-12a.c

On 10/9/23 07:35, Juzhe-Zhong wrote: This case is vectorized by stride8 load_lanes. gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-12a.c: Adapt for stride 8 load_lanes. OK. Same question as last two ACKs. jeff

Re: [PATCH] RISC-V Regression tests: Fix FAIL of pr97832* for RVV

On 10/9/23 07:15, Juzhe-Zhong wrote: These cases are vectorized by vec_load_lanes with strided = 8 instead of SLP with -fno-vect-cost-model. gcc/testsuite/ChangeLog: * gcc.dg/vect/pr97832-2.c: Adapt dump check for target supports load_lanes with stride = 8. * gcc.dg/vect/pr9

Re: [PATCH v1 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

On 10/3/23 03:09, Kito Cheng wrote: We TARGET__P marcro to test a Mask and InverseMask with user specified target_variable, however we may want to test with specific gcc_options variable rather than target_variable. Like RISC-V has defined lots of Mask with TargetVariable, which is not easy t

Re: [PATCH v1 2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC]

On 10/3/23 03:09, Kito Cheng wrote: Allow those funciton apply from a local gcc_options rather than the global options. Preparatory for target attribute, sperate this change for eaiser reivew since it's a NFC. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_convert_vector_bits): Get s

Re: [PATCH] RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV

On 10/9/23 08:21, juzhe.zhong wrote: Do you mean add a check whether it is vectorized or not？ Yes. Sounds reasonable， I can add that in another patch. Sounds good. Thanks. jeff

Re: [RFC 1/2] RISC-V: Add support for _Bfloat16.

On 10/9/23 00:18, Jin Ma wrote: +;; The conversion of DF to BF needs to be done with SF if there is a +;; chance to generate at least one instruction, otherwise just using +;; libfunc __truncdfbf2. +(define_expand "truncdfbf2" + [(set (match_operand:BF 0 "register_operand" "=f") +

Re: xthead regression with [COMMITTED] RISC-V: const: hide mvconst splitter from IRA

On 10/9/23 14:36, Vineet Gupta wrote: Hi Christoph, On 10/9/23 12:06, Patrick O'Neill wrote: Hi Vineet, We're seeing a regression on all riscv targets after this patch:| FAIL: gcc.target/riscv/xtheadcondmov-indirect.c -O2 check-function-bodies ConNmv_imm_imm_reg|| FAIL: gcc.target/riscv/

Re: [PATCH] RISC-V Regression: Fix FAIL of pr65947-8.c for RVV

On 10/10/23 06:55, Juzhe-Zhong wrote: This test is testing fold_extract_last pattern so it's more reasonable use vect_fold_extract_last instead of specifying targets. This is the vect_fold_extract_last property: proc check_effective_target_vect_fold_extract_last { } { return [expr { [che

Re: [PATCH] RISC-V/testsuite: Enable `vect_pack_trunc'

On 10/9/23 19:13, juzhe.zh...@rivai.ai wrote: Oh. I realize this patch increase FAIL that I recently fixed: https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632247.html This fail because RVV doesn't have vec_pack_tru

Re: [PATCH] RISC-V Regression: Fix dump check of bb-slp-68.c

On 10/9/23 19:16, Juzhe-Zhong wrote: Like GCN, RVV also has 64 bytes vectors (512 bits) which cause FAIL in this test. It's more reasonable to use "vect512" instead of AMDGCN. gcc/testsuite/ChangeLog: * gcc.dg/vect/bb-slp-68.c: Use vect512. Just a note for the record. At this time

Re: [PATCH] RISC-V Regression: Make match patterns more accurate

On 10/9/23 20:47, Juzhe-Zhong wrote: This patch fixes following 2 FAILs in RVV regression since the check is not accurate. It's inspired by Robin's previous patch: https://patchwork.sourceware.org/project/gcc/patch/dde89b9e-49a0-d70b-0906-fb3022cac...@gmail.com/ gcc/testsuite/ChangeLog:

Re: [PATCH] RISC-V Regression: Fix FAIL of predcom-2.c

On 10/9/23 20:58, Juzhe-Zhong wrote: Like GCN, add -fno-tree-vectorize. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/predcom-2.c: Add riscv. OK. jeff

Re: [PATCH v2 1/4] options: Define TARGET__P and TARGET__OPTS_P macro for Mask and InverseMask

On 10/9/23 22:13, Kito Cheng wrote: We TARGET__P marcro to test a Mask and InverseMask with user specified target_variable, however we may want to test with specific gcc_options variable rather than target_variable. Like RISC-V has defined lots of Mask with TargetVariable, which is not easy t

Re: [PATCH v2 2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC]

On 10/9/23 22:13, Kito Cheng wrote: Allow those funciton apply from a local gcc_options rather than the global options. Preparatory for target attribute, sperate this change for eaiser reivew since it's a NFC. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_convert_vector_bits): Get s

Re: [PATCH v2 3/4] RISC-V: Extend riscv_subset_list, preparatory for target attribute support

On 10/9/23 22:13, Kito Cheng wrote: riscv_subset_list only accept a full arch string before, but we need to parse single extension when supporting target attribute, also we may set a riscv_subset_list directly rather than re-parsing the ISA string again. gcc/ChangeLog: * config/riscv

Re: [PATCH] RISC-V/testsuite: Enable `vect_pack_trunc'

On 10/10/23 07:53, juzhe.zhong wrote: I am working on it. Currently,  we have about 50+ additional FAILs after enabling vectorization. some of them need fixed on middle-end. E.g richard fixed a missed cse optimization. Some need fix on test case. I am analyzing each fail one by one. I p

Re: [PATCH v6] Implement new RTL optimizations pass: fold-mem-offsets.

On 10/10/23 05:59, Manolis Tsamis wrote: It's a code quality issue as long as we don't transform the code into movl $0, -18874240, at which point it would become a correctness issue. Ok, thanks for pointing that out as I thought that movl $0, -18874240 and movl $0, -18874240(eax) with eax =

Re: [PATCH] Optimize (ne:SI (subreg:QI (ashift:SI x 7) 0) 0) as (and:SI x 1).

On 10/10/23 06:28, Roger Sayle wrote: This patch is the middle-end piece of an improvement to PRs 101955 and 106245, that adds a missing simplification to the RTL optimizers. This transformation is to simplify (char)(x << 7) != 0 as x & 1. Technically, the cast can be any truncation, where sh

Re: [PATCH] Optimize (ne:SI (subreg:QI (ashift:SI x 7) 0) 0) as (and:SI x 1).

On 10/10/23 08:41, Michael Matz wrote: On Tue, 10 Oct 2023, Roger Sayle wrote: This patch is the middle-end piece of an improvement to PRs 101955 and 106245, that adds a missing simplification to the RTL optimizers. This transformation is to simplify (char)(x << 7) != 0 as x & 1. Random

Re: [PATCH v2 4/4] RISC-V: Implement target attribute

On 10/9/23 22:13, Kito Cheng wrote: The target attribute which proposed in [1], target attribute allow user to specify a local setting per-function basis. The syntax of target attribute is `__attribute__((target("")))`. and the syntax of `` describes below: ``` ATTR-STRING := ATTR-STRING ';'

Re: [PATCH] RISC-V Regression: Make pattern match more accurate of vect-live-2.c

On 10/10/23 08:57, Juzhe-Zhong wrote: Like previous patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632400.html https://patchwork.sourceware.org/project/gcc/patch/dde89b9e-49a0-d70b-0906-fb3022cac...@gmail.com/ gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-live-2.c: Make

Re: [PATCH] RISC-V Regression: Fix FAIL of vect-multitypes-16.c for RVV

On 10/10/23 08:49, Juzhe-Zhong wrote: As Richard suggested: https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632288.html Add vect_ext_char_longlong to fix FAIL for RVV. gcc/testsuite/ChangeLog: * gcc.dg/vect/vect-multitypes-16.c: Adapt check for RVV. * lib/target-supp

Re: [RFC] RISC-V: Handle new types in scheduling descriptions

On 10/9/23 15:02, Edwin Lu wrote: Now that every insn is guaranteed a type, we want to ensure the types are handled by the existing scheduling descriptions. There are 2 approaches I see: 1. Create a new pipeline intended to eventually abort (sifive-7.md) 2. Add the types to an existing pipeli

Re: [PATCH] RFC: Add late-combine pass [PR106594]

On 10/7/23 06:58, Richard Sandiford wrote: Yeah, that'd probably be best. I need to split the patch up into a proper submission sequence, do more testing, and make it RFA quality. Jeff has also found a couple of regressions that I need to look at. When you've got updates, just let me know.

[committed] [PR target/93062] RISC-V: Handle long conditional branches for RISC-V

: Likewise. (gpr_restore_return, riscv_mret): Likewise. (riscv_uret, riscv_sret): Likewise. * config/riscv/generic.md (generic_branch): Also recognize jalr & ret types. * config/riscv/sifive-7.md (sifive_7_jump): Likewise. Co-au

Re: [committed] [PR target/93062] RISC-V: Handle long conditional branches for RISC-V

On 10/10/23 18:24, Andrew Waterman wrote: I remembered another concern since we discussed this patch privately. Using ra for long calls results in a sequence that will corrupt the return-address stack. Yup. We've actually got data on that internally, it's not showing up in a significant way

Re: [PATCH v4 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

On 10/11/23 06:06, Mary Bennett wrote: This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However,

Re: Principles of the C99 testsuite conversion

On 10/11/23 04:39, Florian Weimer wrote: I've started to look at what it is required to convert the testsuite to C99 (without implicit ints, without implicit function declarations, and a few other legacy language features). I bet those older tests originating from c-torture will be a bit pain

Re: Principles of the C99 testsuite conversion

On 10/11/23 08:10, Richard Earnshaw (lists) wrote: On 11/10/2023 14:56, Jeff Law wrote: On 10/11/23 04:39, Florian Weimer wrote: I've started to look at what it is required to convert the testsuite to C99 (without implicit ints, without implicit function declarations, and a few

[committed] RISC-V: Adjust long unconditional branch sequence

fallback to $ra in the future so that we don't muck up the return address predictors. It's not super-high priority and shouldn't be terrible to implement given we've got the $ra fallback when a suitable register can not be found. Pushed to the trunk, Jeffcommit a3e50ee

Re: RISC-V: Support CORE-V XCVMAC and XCVALU extensions

On 10/11/23 19:05, juzhe.zh...@rivai.ai wrote: Plz revert it. It blocks development of all targets. We have specific policies for reversion. In general we want to give folks time to fix the problem rather than reverting, resubmitting, etc. Mary, the issue is the doc changes are apparently

Re: [PATCH] RISCV: Bugfix for incorrect documentation heading nesting

On 10/12/23 04:05, Mary Bennett wrote: gcc/ChangeLog: * doc/extend.texi: Change subsubsection to subsection for CORE-V built-ins. This is OK. I'll commit it shortly it. jeff

Re: [PATCH] RISCV: Bugfix for incorrect documentation heading nesting

On 10/12/23 04:05, Mary Bennett wrote: gcc/ChangeLog: * doc/extend.texi: Change subsubsection to subsection for CORE-V built-ins. Thanks for jumping on it quickly. I added the PR marker to the ChangeLog entry (bugzilla integration) and pushed this to the trunk. jeff

Re: [PATCH] reg-notes.def: Fix up description of REG_NOALIAS

On 10/12/23 03:41, Alex Coplan wrote: Hi, The description of the REG_NOALIAS note in reg-notes.def isn't quite right. It describes it as being attached to call insns, but it is instead attached to a move insn receiving the return value from a call. This can be seen by looking at the code in

Re: Ping: [PATCH v2 1/2] testsuite: Add dg-require-atomic-cmpxchg-word

On 10/12/23 08:38, Christophe Lyon wrote: LGTM but I'm not a maintainer ;-) LGTM to as well -- I usually try to stay out of libstdc++, but this looks simple enough. Both patches in this series are OK. jeff

Re: [PATCH v2] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering

On 10/12/23 07:06, Christoph Muellner wrote: From: Christoph Müllner Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA") A recent change broke the xtheadcondmov-indirect tests, because the order of emitted instructions changed. Since the test is too strict when testing for

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