hat it
saves/restores the 128bit registers; is that documented anywhere? The
main reason why I am asking is because glibc is not the only libc out
there and someone could have a slightly different ABI here.
Thanks,
Andrew Pinski
>
> Alan.
>
> 2017-11-16 Alan Hayward
>
> gcc/
On Fri, Nov 17, 2017 at 12:21 AM, Alan Hayward wrote:
>
>> On 16 Nov 2017, at 19:32, Andrew Pinski wrote:
>>
>> On Thu, Nov 16, 2017 at 4:35 AM, Alan Hayward wrote:
>>> This final patch adds the clobber high expressions to tls_desc for aarch64.
>>> It als
On Thu, Nov 23, 2017 at 11:54 AM, Tom de Vries wrote:
> Hi,
>
> this patch wraps CLASS_TABLE_HASH in "do {} while (0)". This allows the
> macro to be used in if-then-elses without curly braces.
>
> Build libobcj for x86_64.
>
> Committed as obvious.
Yes this is ok.
Thanks,
Andrew
>
> Thanks,
>
was experimenting with optimizing away matching malloc/free pairs,
> moving the allocation to either the stack, or to a thread-local
> obstack, under certain conditions, or to hoist allocations out of
> loops.
>
> I didn't get any significant wins, but much of this was due to
On Tue, Dec 5, 2017 at 9:50 AM, Thomas Preudhomme
wrote:
> Hi,
>
> dump-noaddr test FAILS when $tmpdir is not the same as the directory
> where runtest is called from. Note that this does not happen when
> running make check because tmpdir is set to srcdir.
>
> In that case, file mkdir will create
On Thu, Jan 4, 2018 at 9:46 AM, Wilco Dijkstra wrote:
> This patch improves register allocation of fma by preferring to update the
> accumulator register. This is done by adding fma insns with operand 1 as the
> accumulator. The register allocator considers copy preferences only in
> operand
>
On Tue, Jun 5, 2018 at 9:32 AM Kyrill Tkachov
wrote:
>
>
> On 04/06/18 18:40, Kyrill Tkachov wrote:
> > Hi all,
> >
> > This patch adds support for generating LDPs and STPs of Q-registers.
> > This allows for more compact code generation and makes better use of the
> > ISA.
> >
> > It's implement
On Tue, Jan 9, 2018 at 6:54 AM, Segher Boessenkool
wrote:
> On Tue, Jan 09, 2018 at 12:23:42PM +, Wilco Dijkstra wrote:
>> Segher Boessenkool wrote:
>> > On Mon, Jan 08, 2018 at 0:25:47PM +, Wilco Dijkstra wrote:
>> >> > Always pairing two registers together *also* degrades code quality.
>
On Thu, Jan 18, 2018 at 8:03 AM, Sebastian Perta
wrote:
> Hi,
>
> Thank you!
> As the description says this finds equivalent functions, I would like to find
> identical sequences inside
> functions but at least this will provide all the up to date tools to compare
> code sequences, thank you aga
On Mon, Feb 12, 2018 at 3:55 PM, Kugan Vivekanandarajah
wrote:
> Implements tree loop unroller using the infrastructure provided.
>
> gcc/ChangeLog:
>
> 2018-02-12 Kugan Vivekanandarajah
>
> * Makefile.in (OBJS): Add tree-ssa-loop-unroll.o.
> * common.opt (ftree-loop-unroll): New option
On Fri, Sep 14, 2018 at 1:34 PM Qing Zhao wrote:
>
> Hi,
>
> this is the 2nd version of the patch to add a new first-class option
>
> -finline-only-static
>
> to guide inlining only on static functions.
>
> -finline-only-static
> By default, GCC inlines functions without considering whether they
On Fri, Sep 14, 2018 at 1:42 PM Andrew Pinski wrote:
>
> On Fri, Sep 14, 2018 at 1:34 PM Qing Zhao wrote:
> >
> > Hi,
> >
> > this is the 2nd version of the patch to add a new first-class option
> >
> > -finline-only-static
> >
> > to gui
trunk and the GCC 8 branch.
Thanks,
Andrew Pinski
ChangeLog:
2018-09-24 Andrew Pinski
* config/aarch64/aarch64.c (aarch_macro_fusion_pair_p): Don't access
prev before checking it for NULLness in the AARCH64_FUSE_CMP_BRANCH
case.
Index: config/aarch64/aarc
r __attribute__((vector_size(16) ))
vector unsigned long long f(vector unsigned long long b, vector unsigned int a)
{
b[0] = a[0];
return b;
}
CUT
Something like this will cover w->r zero-extension
unsigned long long g(vector unsigned int a)
{
return a[0];
}
Thanks,
Andrew Pinski
>
> Wilco
>
On Wed, Oct 3, 2018 at 10:50 AM Wilco Dijkstra wrote:
>
> Andrew Pinski wrote:
>
> > Something like will cover w->w zero-extension.
>
> Thanks, those cases trigger and show an improvement, so I've
> added r=w and w=w cases too:
>
> The popcount expansion u
On Fri, May 11, 2018 at 10:15 AM, Richard Sandiford
wrote:
> There are four optabs for various forms of fused multiply-add:
> fma, fms, fnma and fnms. Of these, only fma had a direct gimple
> representation. For the other three we relied on special pattern-
> matching during expand, although tre
On Fri, May 11, 2018 at 11:04 AM, Richard Sandiford
wrote:
> Andrew Pinski writes:
>> On Fri, May 11, 2018 at 10:15 AM, Richard Sandiford
>> wrote:
>>> There are four optabs for various forms of fused multiply-add:
>>> fma, fms, fnma and fnms. Of th
On Wed, May 16, 2018 at 7:14 PM, Kugan Vivekanandarajah
wrote:
> As mentioned in the PR, I am trying to add ABSU_EXPR to fix this
> issue. In the attached patch, in fold_cond_expr_with_comparison I am
> generating ABSU_EXPR for these cases. As I understand, absu_expr is
> well defined in RTL. So,
e first place; I will explain how
in the email with the patch.
Thanks,
Andrew Pinski
Andrew Pinski (2):
Revert: 2011-08-19 H.J. Lu
Fix ILP32 ld.so.
gcc/explow.c | 53 -
1 files changed, 32 insertions(+), 21 deletions(-)
--
1.7.2.5
h64-linux-gnu with no regressions and also fixing ld.so
for ILP32.
Thanks,
Andrew Pinski
ChangeLog:
* explow.c (convert_memory_address_addr_space): Rename to ...
(convert_memory_address_addr_space_1): This. Add in_const argument.
Inside a CONST RTL, permute the conversion and
OK? When the second patch is approved?
Thanks,
Andrew Pinski
ChangeLog:
Revert:
2011-08-19 H.J. Lu
PR middle-end/49721
* explow.c (convert_memory_address_addr_space): Also permute the
conversion and addition of constant for zero-extend.
---
gcc
Hi all,
When I was testing the ccmp set of patches on aarch64, I found a
testcase which would ICE. This patch adds the testcase. I don't know
if this testcase ICEs due to other local set of patches though.
Thanks,
Andrew Pinski
2014-08-16 Andrew Pinski
* gcc.c-torture/compile/20140
r warn_strict_aliasing. */
> +#include "c-family/c-common.h"
You should never be including a c-family header file from
tree-inline.c. if you need warn_strict_aliasing, include options.h
instead.
Now for strict_aliasing_warning, you should move the definition to
tr
On Sun, Aug 24, 2014 at 1:42 PM, Josh Triplett wrote:
> handle_section_attribute contains many levels of nested conditionals and
> branching code flow paths, with the error cases sometimes in the else
> case and sometimes in the if case. Simplify the code flow into a series
> of potential failure
On Thu, Aug 28, 2014 at 3:00 PM, Jan-Benedict Glaw wrote:
> Hi!
>
> The following patch silences two warnings in the mep-elf target,
> fixing the config-list.mk build:
I thought -Werror was only on when the versions of GCC match.
Thanks,
Andrew
>
>
> First one:
> ~~
> g++ -c -DIN_GCC_
days which is why the testcase is dated
two days ago.
Thanks,
Andrew Pinski
ChangeLog:
* gcc.c-torture/execute/20140828-1.c: New testcase.
Index: gcc.c-torture/execute/20140828-1.c
===
--- gcc.c-torture/execute/20140828-1.c (revision 0
ave been bugs in the past in the
area of always_inline too.
Thanks,
Andrew Pinski
>
> Passes bootstrap and testing on x86_64-linux.
>
> Cc: dmalc...@redhat.com
>
> include/:
>
> 2014-09-01 Andi Kleen
>
> * ansidecl.h (ALWAYS_INLINE): Add.
>
> gcc/:
>
On Tue, Sep 2, 2014 at 12:20 AM, Andi Kleen wrote:
>
>> there have been bugs in the past in the area of always_inline too.
>
> You're arguing for my patch. It would find those bugs.
No I am arguing against it since the older versions of GCC we cannot change.
Thanks,
Andrew
>
> -Andi
breakpoint instruction was a common theme between them if there
was not explicit defined undefined instruction to use.
OK? Build and tested on aarch64-elf with no regressions. Also built
a full aarch64-linux-gnu toolchain including glibc.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.md (
raped and tested on an x86-64 machine.
I think you need to look into this issue deeper as the original patch
only enabled it for C99:
http://gcc.gnu.org/ml/gcc-patches/2005-02/msg01483.html .
Just a little deeper will find
http://gcc.gnu.org/ml/gcc/2007-07/msg00124.html which says yes C++
needs
as this default -- very few
> user knows about GCC's strict default, and will think GCC performs
> poorly.
Correctness over speed is better. I am sorry GCC is the only one
which gets it correct here. If people don't like there is a flag to
disable it.
Thanks,
Andrew Pinski
>
On Mon, Nov 18, 2013 at 9:58 AM, Cesar Philippidis
wrote:
> This patch addresses the failures caused by the
> gcc.c-torture/execute/20101011-1.c test on aarch64. The reason why this
> test fails is because aarch64 does not trap on integer division by zero.
>
> Is this OK for trunk? If so, please c
On Tue, Nov 19, 2013 at 1:22 AM, Marcus Shawcroft
wrote:
> On 13 November 2013 00:04, Andrew Pinski
>
> wrote:
>>
>> Hi all,
>> This patch implements the trap pattern for the AARCH64 back-end. I
>> used the "brk #0" instruction as that is the breakpo
d GCC. For testing you might need
something that is included inside testsuite/lib/atomic-dg.exp which
sets the library path to include libatomic build directory.
I think now we require libatomic in more cases (C11 atomic support for
an example).
Thanks,
Andrew Pinski
>
> Is this OK for trunk?
On Wed, Nov 20, 2013 at 10:44 AM, Rong Xu wrote:
> On Tue, Nov 19, 2013 at 5:11 PM, Andrew Pinski wrote:
>> On Tue, Nov 19, 2013 at 5:02 PM, Rong Xu wrote:
>>> Hi all,
>>>
>>> I merged this old patch with current trunk. I also make the following
>>&
On Wed, Nov 20, 2013 at 10:48 AM, Andrew Pinski wrote:
> On Wed, Nov 20, 2013 at 10:44 AM, Rong Xu wrote:
>> On Tue, Nov 19, 2013 at 5:11 PM, Andrew Pinski wrote:
>>> On Tue, Nov 19, 2013 at 5:02 PM, Rong Xu wrote:
>>>> Hi all,
>>>>
>>>> I
On Wed, Nov 20, 2013 at 2:07 PM, Rong Xu wrote:
> Joseph and Andrew, thanks for the suggestion. That's really helpful.
>
> Here is the new patch for gcc.c.
> Basically, it's just what you have suggested: enclosing -latomic with
> --as-needed, and using macros.
> For the case of no --as-needed supp
/main branch, and future merges will go more smoothly if what I
> put in google/main matches what eventually goes into trunk.
Hmm, Stage 1 has been opened for a while now but I could not find
this patch has been committed yet. Is there any plans to include this
patch? It would be useful for San
msg02877.html
The main benefit is it allows for targets to support wider integer
than two times HOST_WIDE_INT. So gfortran, is that it connects to the
rest of the middle-end of GCC.
Thanks,
Andrew Pinski
On Sat, Nov 23, 2013 at 1:31 PM, Andrew Pinski wrote:
> On Sat, Nov 23, 2013 at 12:16 PM, Steve Kargl
> wrote:
>> On Sat, Nov 23, 2013 at 11:21:21AM -0800, Mike Stump wrote:
>>> Richi has asked the we break the wide-int patch so that the individual port
>>> and fr
On Sat, Nov 23, 2013 at 11:19 AM, Mike Stump wrote:
> Richi has asked the we break the wide-int patch so that the individual port
> and front end maintainers can review their parts without have to go through
> the entire patch.This patch covers the aarch64 port.
+ wide_int w = real_to_int
On Sat, Nov 23, 2013 at 4:26 PM, Steve Kargl
wrote:
> On Sat, Nov 23, 2013 at 01:31:04PM -0800, Andrew Pinski wrote:
>> On Sat, Nov 23, 2013 at 12:16 PM, Steve Kargl
>> wrote:
>> > On Sat, Nov 23, 2013 at 11:21:21AM -0800, Mike Stump wrote:
>> >> Richi has a
d4
> +#else
> +#define MOVZ_X8_8B 0xd2801168
> +#define SVC_0 0xd401
> +#endif
I think this should have a comment about the byte-order of
instructions so it is easier to understand why they are different
between big and little-endian.
Thanks,
Andr
On Tue, Oct 7, 2014 at 11:43 PM, Thomas Preud'homme
wrote:
>> From: Jakub Jelinek [mailto:ja...@redhat.com]
>> Sent: Wednesday, October 08, 2014 2:39 PM
>>
>> Doesn't it turn 16-bit {L,R}ROTATE_EXPR used alone into
>> __builtin_bswap16?
>> For those the question is if the canonical GIMPLE should b
On Thu, Oct 9, 2014 at 12:05 AM, Michael Collison
wrote:
>
> The CLZ_DEFINED_VALUE_AT_ZERO macro is harded to return 32. For the vector
> intrinsic vclz this is incorrect and should return the value eight. The
> CTZ_DEFINED_VALUE_AT_ZERO has the same issue.
Do you have a testcase? I almost thin
ding style.
Also you added no comment before each function. The coding style says
each function needs a comment describing what the function does.
Thanks,
Andrew Pinski
>
> Thanks,
> Kyrill
>
> 2014-10-10 Kyrylo Tkachov
> Ramana Radhakrishnan
>
> * conf
On Sat, Oct 11, 2014 at 9:42 AM, Kwok Cheung Yeung
wrote:
> __gthread_active_p() in libgcc checks for thread support by looking for the
> presence of a symbol from libpthread. With glibc, it looks for
> __pthread_key_create. However, it determines that glibc is being used by
> checking for a defi
On Fri, Aug 8, 2014 at 8:51 PM, Andrew Pinski wrote:
> OK? When the second patch is approved?
Ping?
>
> Thanks,
> Andrew Pinski
>
> ChangeLog:
> Revert:
> 2011-08-19 H.J. Lu
>
> PR middle-end/49721
> * explow.c (convert_memory_
On Fri, Aug 8, 2014 at 8:51 PM, Andrew Pinski wrote:
> This patch fixes the original problem that HJL was having with x32 in
> PR 47727, it is more constraint than HJL's patch only care about what
> is happening inside a CONST; if we allow it for other cases,
> the RTL and
On Wed, Oct 15, 2014 at 10:29 AM, Jeff Law wrote:
> On 10/13/14 16:35, Andrew Pinski wrote:
>>
>> On Fri, Aug 8, 2014 at 8:51 PM, Andrew Pinski wrote:
>>>
>>> OK? When the second patch is approved?
>>
>>
>> Ping?
>>
>>>
&g
em_attrs_1 (rtx x, rtx dstref)
{
((x)->volatil) = ((dstref)->volatil);
((x)->in_struct) = ((dstref)->in_struct);
((x)->frame_related) = ((dstref)->frame_related);
((x)->unchanging) = ((dstref)->unchanging);
}
--- CUT ---
Thanks,
Andrew
gresses at -O3 on aarch64:
>
> void saxpy(double* x, double* y, double* z) {
> int i=0;
> for (i = 0 ; i < ARRAY_SIZE; i++) {
> z[i] = x[i] + scalar*y[i];
> }
> }
This looks like a scheduling issue rather than anything else. The
scheduler for a57 is no
On Wed, Oct 15, 2014 at 3:08 AM, Marek Polacek wrote:
> On Tue, Oct 14, 2014 at 09:23:29AM +0200, Marek Polacek wrote:
>> The consensus seems to be to go forward with this change. I will
>> commit the patch in 24 hours unless I hear objections.
>
> I made the change. Please report any fallout to
On Thu, Oct 16, 2014 at 3:35 PM, Andrew Pinski wrote:
> On Wed, Oct 15, 2014 at 3:08 AM, Marek Polacek wrote:
>> On Tue, Oct 14, 2014 at 09:23:29AM +0200, Marek Polacek wrote:
>>> The consensus seems to be to go forward with this change. I will
>>> commit the patc
On Mon, Oct 20, 2014 at 10:46 AM, Sriraman Tallam wrote:
> On Mon, Oct 20, 2014 at 10:42 AM, Xinliang David Li
> wrote:
>> Why removing the tree_code check?
>
> The actual problem happens because STRING_CSTs (end up in .lrodata)
> are not set a far address as they dont match the VAR_DECL check h
-tables.h.
OK? Built and tested for aarch64-elf.
Thanks,
Andrew Pinski
PS The corresponding binutils patch is located at
https://sourceware.org/ml/binutils/2014-10/msg00170.html .
ChangeLog:
* doc/invoke.texi (AARCH64/mtune): Document thunderx as an available
option also.
* config/aarch64/aarch64
On Mon, Oct 20, 2014 at 9:06 PM, Maxim Kuvyrkov
wrote:
> Hi,
>
> This patch adds auto-prefetcher modeling to GCC scheduler. The
> auto-prefetcher model is currently enabled only for ARM Cortex-A15, since
> this is the only CPU that I know of to have the hardware auto-prefetcher unit.
That migh
them. I used a define to allow it
easier instead of having to have "#if HAVE_DESIGNATED_INITIALIZERS &&
GCC_VERSION >= 2007" each time.
OK? Build and tested on aarch64-elf with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64-cost-tables.h (NAM
On Wed, Oct 22, 2014 at 4:43 AM, Rainer Orth
wrote:
> The gnu11 patch broke Solaris 10 and 11 bootstrap:
> has
>
> /*
> * It is invalid to compile an XPG3, XPG4, XPG4v2, or XPG5 application
> * using c99. The same is true for POSIX.1-1990, POSIX.2-1992, POSIX.1b,
> * and POSIX.1c applications
On Thu, Oct 23, 2014 at 11:51 PM, Yangfei (Felix) wrote:
> Thanks for the explanation. I think I am clear about what you are thinking
> now.
> That's an interesting question. I am not sure about reason why GCC's reload
> cannot handle a doloop_end insn.
> I guess maybe the doloop_end pattern is
On Fri, Oct 24, 2014 at 8:44 AM, Christophe Lyon
wrote:
> On 29 September 2014 15:01, Christophe Lyon
> wrote:
>> On 26 September 2014 23:05, Andreas Schwab wrote:
>>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=34c65c4
>>>
>>> * sanitizer_common/sanitizer
quot;je 1f;" \
"ud2;" \
"1:\n" \
: "=c" (__res)); \
__res; })
#endif
This depends on ebx being the PIC register. Now we don't have this so
we get ud2 in some cases.
Thanks,
Andrew Pinski
>> missing :-)
>> Thanks.
>
>
> Any comments?
Yes you can use -mcmodel=large to this effect I think.
Thanks,
Andrew Pinski
erate long calls?
>> >> Any plan on this option? I would like to have a try on this if it's
>> >> missing :-)
>> >> Thanks.
>> >
>> >
>> > Any comments?
>>
>> Yes you can use -mcmodel=large to this effect I th
+ return FALSE;
> + }
Why not do it unconditionally rather than base this on optimize for size?
If the costs are incorrect for non optimize for size, we need to fix those.
Thanks,
Andrew Pinski
> +
> emit_insn_before_setloc (seq, if_info->jump,
>
This factors out the IF_THEN_ELSE from aarch64_rtx_costs as that function was
getting too large.
OK? Build and tested for aarch64-elf with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.c (aarch64_if_then_else_costs): New function.
(aarch64_rtx_costs): Use
no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Allow non
comparisons
for OP0.
testsuite/ChangeLog:
* gcc.c-torture/compile/20140528-1.c: New testcase.
---
gcc/config/aarch64/aarch64.c | 36
ous patch and would be the exact same
patch I would have came up with.
Thanks,
Andrew Pinski
>
>
> Ping.
>
>
>> On Wed, 28 May 2014 23:55:31 +0200, Jan Hubicka wrote:
>> > > On Mon, 26 May 2014 02:16:35 -0700, Andrew Pinski
>> > > wrote:
>> > &g
On Mon, Feb 24, 2014 at 1:18 AM, Zhenqiang Chen
wrote:
> Hi,
>
> The patch (http://gcc.gnu.org/ml/gcc-patches/2014-11/msg03622.html) is
> re-based (the arm port change is stripped as a separate patch), which
> includes only the middle-end changes. The basic logic for the patch
> is:
>
> 1) Ident
On Sat, Jun 14, 2014 at 7:50 PM, Andrew Pinski wrote:
> On Mon, Feb 24, 2014 at 1:18 AM, Zhenqiang Chen
> wrote:
>> Hi,
>>
>> The patch (http://gcc.gnu.org/ml/gcc-patches/2014-11/msg03622.html) is
>> re-based (the arm port change is stripped as a separate patc
+ }
+ /* a = EXP ? b : c is also an use in conditional
+ statement. */
+ else if (gimple_code (use_stmt) == GIMPLE_ASSIGN
+ && gimple_expr_code (use_stmt) == COND_EXPR)
+ {
+ if (gimple_assign_rhs1 (use_stmt) == exp)
+ expand_con
On Mon, Jun 23, 2014 at 12:09 AM, Andrew Pinski wrote:
> On Mon, Jun 23, 2014 at 12:01 AM, Zhenqiang Chen
> wrote:
>> Hi,
>>
>> The patch enhances ifcvt to handle conditional compare instruction
>> (ccmp) to make it work with cmov. For ccmp, ALLOW_CC_MODE
On Mon, Jun 23, 2014 at 11:17 AM, Andi Kleen wrote:
> Marc Glisse writes:
>
>> Hello,
>>
>> this is a stage 1 patch, and I'll ping it then, but if you have
>> comments now...
>
> FWIW i believe the transformation will break a large variety of micro
> benchmarks.
>
> calloc internally knows that
On Mon, Jun 23, 2014 at 1:21 PM, Andi Kleen wrote:
> On Mon, Jun 23, 2014 at 10:14:25PM +0200, Marc Glisse wrote:
>> On Mon, 23 Jun 2014, Andi Kleen wrote:
>>
>> >I would prefer to not do it.
>>
>> For the sake of micro benchmarks?
>
> Yes benchmarks are important.
But micro-benchmarks are not i
re compile test to make
sure we don't ICE (which I think we do currently).
Thanks,
Andrew Pinski
2014-06-23 Andrew Pinski
* gcc.c-torture/compile/20140723-1.c: New testcase.
Index: gcc.c-torture/compile/20140723-1.c
===
--
On Tue, May 20, 2014 at 1:04 PM, Jan Hubicka wrote:
> Hi,
> as disucssed some time ago, our assumption that every symbol of shared
> library can
> be interposed at runtime is expensive and prevents a lot of useful
> optimizations,
> including inlining or IPA propagation.
>
> While this is useful
On Tue, Jun 3, 2014 at 5:07 PM, Jones, Joel
wrote:
> There is duplicate code for determining whether a load or store
> instruction needs acquire or release semantics. This patch removes the
> duplicated code and uses a modifying operator to output a/l instead. Since
> the testsuite already con
I committed this as obvious. The changelog says it all.
Thanks,
Andrew
2014-06-28 Andrew Pinski
* lto.c (lto_read_decls): Fix comment in comment.
Index: lto.c
===
--- lto.c (revision 212118)
+++ lto.c (working copy
kewise.
> * sysdep/i386/backtrace.h: Likewise.
>
> libobjc/
> * configure.ac: Remove manual SJLJ check.
> * config.h.in: Regenerate.
> * configure: Likewise.
> * exception.c: Replace SJLJ_EXCEPTIONS by __USING_SJLJ_EXCEPTIONS__.
The libobjc parts are
On Sat, May 23, 2015 at 1:33 AM, Alan Modra wrote:
> This stops combine messing with parameter and return value copies
> from/to hard registers. Bootstrapped and regression tested
> powerpc64le-linux, powerpc64-linux and x86_64-linux. In looking at a
> number of different powerpc64le gcc/*.o fil
On Wed, May 27, 2015 at 4:38 PM, Kyrill Tkachov wrote:
> Ping.
> https://gcc.gnu.org/ml/gcc-patches/2015-05/msg00054.html
This and the one in AARCH64 is too noisy. Can we have an option to
turn this on and default to turning them off.
Thanks,
Andrew
>
> Thanks,
> Kyrill
>
> On 01/05/15 15:31,
error which uses the
GCC diagnostic format you can just use %wd instead.
So:
error ("%Klane %ld out of range %ld - %ld", exp, lane, low, high - 1);
Becomes:
error ("%Klane %wd out of range %wd - %wd", exp, lane, low, high - 1);
Thanks,
Andrew Pinski
>
>
> Shiva
fix the message since you have better solution ?
I don't build using a 32bit host so I can't test it.
Thanks,
Andrew
>
> Thanks,
>
> Shiva
>
> 2015-05-29 15:13 GMT+08:00 Andrew Pinski :
>> On Fri, May 29, 2015 at 2:33 PM, Shiva Chen wrote:
>>> Hi,
>
53, Cortex-A72, X-Gene 1 cores,
> but I don't have that info for thunderx or exynosm1. Could someone from
> Cavium and Samsung help me out
> here? At present this patch has some false dummy values that I'd like to
> fill out before committing this.
Here is the /proc/cpuinfo f
he stack alignment that is support is not 64k but much
smaller. And the supported static data alignment is much larger,
maybe 20 or more.
Thanks,
Andrew Pinski
>
> Regards,
> Renlin Li
>
> gcc/ChangeLog
>
> 2014-12-16 Renlin Li
>
> * config/aarch
On Tue, Nov 11, 2014 at 3:55 AM, Kyrill Tkachov wrote:
> Hi all,
>
> This is the aarch64 implementation of the macro fusion hook, used to fuse
> mov+movk instructions together.
>
> A new field is declared in the tuning struct and as we add more fuseable ops
> in the future we will fill in more bit
On Thu, Nov 13, 2014 at 9:42 AM, Sandra Loosemore
wrote:
> On 11/13/2014 10:27 AM, Richard Earnshaw wrote:
>>
>> On 13/11/14 17:05, Ramana Radhakrishnan wrote:
>>>
>>> On Thu, Nov 13, 2014 at 4:55 PM, Sandra Loosemore
>>> wrote:
This patch to the AArch64 back end adds a couple of additi
On Thu, Nov 13, 2014 at 7:19 AM, Kyrill Tkachov wrote:
>
> On 13/11/14 07:24, Andrew Pinski wrote:
>>
>> On Tue, Nov 11, 2014 at 3:55 AM, Kyrill Tkachov
>> wrote:
>>>
>>> Hi all,
>>>
>>> This is the aarch64 implementation of the macro
On ThunderX, I found that aligning functions/loops/jumps to an 8 byte
boundary have a slightly better performance because the hardware issue
and dispatch matches what GCC's schedule has created.
I set generic, cortex-a53 and cortex-a57 also to be 8 byte aligned
also. Someone might want to change
In ThunderX, any 1 cycle arthemantic instruction that produces the flags
register, will be fused with a branch. This patch depends on
https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01508.html.
Note I know bit 1 is going is already going to be used and that is why I
proposed this being bit 2.
Build
ig/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
new file mode 100644
index 000..30e4395
--- /dev/null
+++ b/gcc/config/aarch64/thunderx.md
@@ -0,0 +1,260 @@
+;; Cavium ThunderX pipeline description
+;; Copyright (C) 2014 Free Software Foundation, Inc.
+;;
+;; Written by Andrew Pinsk
set the alignment
of functions, loops and jumps.
Thanks,
Andrew Pinski
Andrew Pinski (3):
[AARCH64] Add macro fusion support for cmp/b.X for ThunderX
[AARCH64] Add scheduler for ThunderX
[AARCH64] Add aligning of functions/loops/jumps
gcc/config/aarch64/aarch64-cores.def |2 +-
gcc
at's which are declared in the translation unit. So force them to
memory when really we know they are declared and don't have a value of
zero so they will fit in the medium code model. This happens with
vtables and we lose some performance because of this.
Thanks,
Andrew Pinski
&
On Fri, Nov 14, 2014 at 1:08 AM, Kyrill Tkachov wrote:
> Hi Andrew,
>
>
> On 14/11/14 00:56, Andrew Pinski wrote:
>>
>> In ThunderX, any 1 cycle arthemantic instruction that produces the flags
>> register, will be fused with a branch. This patch depends on
>>
On Fri, Nov 14, 2014 at 2:35 AM, James Greenhalgh
wrote:
>
> Hi,
>
> We currently do not set any interesting default values for jump and function
> alignment in AArch64. I've made the formula for these values derive from
> the issue rate of the processor as so:
>
> jumps: 4 * processor issue-rat
On Fri, Nov 14, 2014 at 12:50 AM, Tejas Belagod wrote:
> On 14/11/14 08:19, Andrew Pinski wrote:
>>
>> On Fri, Nov 14, 2014 at 12:12 AM, Tejas Belagod
>> wrote:
>>>
>>>
>>> Hi,
>>>
>>> Following the discussion here
>>&
options is a time bomb.
Then how are you handling older kernel headers? I guess you guys
don't care that much about older kernels then.
See https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01735.html for more
details and https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01769.html
for the approval
On Fri, Nov 14, 2014 at 11:35 AM, Andrew Pinski wrote:
> On Fri, Nov 14, 2014 at 11:29 AM, Konstantin Serebryany
> wrote:
>> +gcc-patches
>>
>> On Fri, Nov 14, 2014 at 11:26 AM, Konstantin Serebryany
>> wrote:
>>> I am opposed to this change.
&
I thought I would mention the addition of the ThunderX AARCH64
processor support to the changes web page.
OK? Tested by looking at the web page with Chrome.
Thanks,
Andrew
? gcc-4.9/.changes.html.swp
? gcc-5/.changes.html.swp
Index: gcc-5/changes.html
ut now
aarch64_can_eliminate and aarch64_frame_pointer_required are
inconsitant which is not a valid thing for LRA (and reload).
This was mentioned in https://gcc.gnu.org/ml/gcc-patches/2013-12/msg00151.html :
" IRA calls hook frame_pointer_required and it returns false. After
that LRA calls can_eliminate hook and it returns false which means
that fp can not be used for allocation and we should spill all pseudos
assigned to it."
Can you revert your patch until you can figure out how to get LRA (and
reload) to play nicely with what you want to do?
Thanks,
Andrew Pinski
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