On Fri, Sep 28, 2018 at 10:57 AM Wilco Dijkstra <wilco.dijks...@arm.com> wrote:
>
> Richard Henderson wrote:
>
> > If you're going to add moves r->w, why not also go ahead and add w->r.
> > There are also HImode fmov zero-extensions, fwiw.
>
> Well in principle it would be possible to support all 8/16/32-bit zero
> extensions
> for all combinations of int and fp registers. However I prefer to only add
> cases
> which are proven to be useful in real code, so it would need an example where
> it helps.
>
> We've seen too many instances where not keeping a well defined boundary
> between int and fp/simd leads to bad code, so not defining all possible legal
> combinations is intended. I'll check whether 32-bit w->r and w->w
> zero-extension
> could ever trigger.
Something like will cover w->w zero-extension.
#define vector __attribute__((vector_size(16) ))
vector unsigned long long f(vector unsigned long long b, vector unsigned int a)
{
b[0] = a[0];
return b;
}
---- CUT ----
Something like this will cover w->r zero-extension
unsigned long long g(vector unsigned int a)
{
return a[0];
}
Thanks,
Andrew Pinski
>
> Wilco
>
