On Tue, 5 Nov 2024, Soumya AR wrote:
>
>
> > On 29 Oct 2024, at 7:16 PM, Richard Biener wrote:
> >
> > External email: Use caution opening links or attachments
> >
> >
> > On Mon, 28 Oct 2024, Soumya AR wrote:
> >
> >> This patch transforms the following POW calls to equivalent LDEXP calls, as
> -Original Message-
> From: Li, Pan2
> Sent: Thursday, November 7, 2024 12:57 PM
> To: Tamar Christina ; Richard Biener
>
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
> jeffreya...@gmail.com; rdapp@gmail.com
> Subject: RE: [PATCH v2 01/10] Match: Simpli
>> If the problem is tracking liveness, wouldn't it be better to
>> iterate over the "then" block in reverse order? We would start
>> with the liveness set for the join block and update as we move
>> backwards through the "then" block. This liveness set would
>> tell us whether the current instru
On Thu, Nov 7, 2024 at 11:24 AM Jakub Jelinek wrote:
>
> On Thu, Nov 07, 2024 at 09:12:34AM +0100, Uros Bizjak wrote:
> > On Thu, Nov 7, 2024 at 9:00 AM Jakub Jelinek wrote:
> > >
> > > On Thu, Nov 07, 2024 at 08:47:34AM +0100, Uros Bizjak wrote:
> > > > Maybe we should always recognize "redzone"
Tejas Belagod writes:
> There is an assumption in many places in c-typeck.cc that GNU vectors sizes
> are
> always known at compile time. SVE vectors now piggy-back on GNU vector code
> so this patch changes one of the places where there is an assumption of
> vectors
> being fixed-length to bei
Hi Torbjörn,
On Thu, 31 Oct 2024 at 19:34, Torbjörn SVENSSON
wrote:
>
> Ok for trunk and releases/gcc-14?
>
> --
>
> Test uses MVE, so add effective-target arm_fp requirement.
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/arm/mve/general-c++/nomve_fp_1.c: Use
> effective-target ar
Tejas Belagod writes:
> This patch adds a change to handle VLA's poly indices.
>
> gcc/ChangeLog:
>
> * cp/decl.cc (reshape_init_array_1): Handle poly indices.
>
> gcc/testsuite/ChangeLog:
>
> * g++.dg/ext/sve-sizeless-1.C: Update test to test initialize error.
> * g++.dg/ext/sve
Hi Saurabh,
> On 6 Nov 2024, at 11:03, saurabh@arm.com wrote:
>
>
> The AArch64 FEAT_FP8 extension introduces instructions for conversion
> and scaling.
>
> This patch introduces the following intrinsics:
> 1. vcvt{1|2}_{bf16|high_bf16|low_bf16}_mf8_fpm.
> 2. vcvt{q}_mf8_f16_fpm.
> 3. vcvt_
This patch series re-implements the store_scatter and load_gather
intrinsincs using the new framework, similarly to previous series.
A few points worth mentioning:
- unlike other intrinsics, these ones have the predicate after the
mode in their names, hence the need for patch #1
- when checkin
This patch implements vstr?q_scatter_offset using the new MVE builtins
framework.
It uses a similar approach to a previous patch which grouped
truncating and non-truncating stores in two sets of patterns, rather
than having groups of patterns depending on the destination size.
We need to add the
This patch adds the load_gather_base shape description.
Unlike other load_gather shapes, this one does not support overloaded
forms.
gcc/ChangeLog:
* config/arm/arm-mve-builtins-shapes.cc (struct
load_gather_base_def): New.
* config/arm/arm-mve-builtins-shapes.h: (load_ga
I see, thanks a lot.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, November 7, 2024 5:03 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2] D
On 07/11/2024 00:37, haochen.jiang wrote:
On Linux/x86_64,
d334f729e53867b838e867375b3f475ba793d96e is the first bad commit
commit d334f729e53867b838e867375b3f475ba793d96e
Author: Andrew Stubbs
Date: Wed Nov 6 12:26:08 2024 +
openmp: Add testcases for omp_max_vf
caused
FAIL: gcc.d
On 07/11/2024 11:07, Jakub Jelinek wrote:
On Thu, Nov 07, 2024 at 10:54:40AM +, Andrew Stubbs wrote:
On 07/11/2024 00:37, haochen.jiang wrote:
d334f729e53867b838e867375b3f475ba793d96e is the first bad commit
commit d334f729e53867b838e867375b3f475ba793d96e
Author: Andrew Stubbs
Date: Wed
On 11/7/2024 9:03 AM, Kyrylo Tkachov wrote:
Hi Saurabh,
On 6 Nov 2024, at 11:03, saurabh@arm.com wrote:
The AArch64 FEAT_FP8 extension introduces instructions for conversion
and scaling.
This patch introduces the following intrinsics:
1. vcvt{1|2}_{bf16|high_bf16|low_bf16}_mf8_fpm.
2.
On Thu, Nov 07, 2024 at 08:47:34AM +0100, Uros Bizjak wrote:
> Maybe we should always recognize "redzone", even for targets without
> it. This is the way we recognize "cc" even for targets without CC reg
> (e.g. alpha). This would simplify the definition and processing - if
> the hook returns NULL_
On Thu, Nov 7, 2024 at 9:00 AM Jakub Jelinek wrote:
>
> On Thu, Nov 07, 2024 at 08:47:34AM +0100, Uros Bizjak wrote:
> > Maybe we should always recognize "redzone", even for targets without
> > it. This is the way we recognize "cc" even for targets without CC reg
> > (e.g. alpha). This would simpl
On Thu, Nov 7, 2024 at 3:52 PM Jakub Jelinek wrote:
>
> On Thu, Nov 07, 2024 at 01:57:21PM +0800, Hongtao Liu wrote:
> > > Does it turn the sNaNs into infinities or qNaNs silently?
> > Yes.
>
> Into infinities?
Into qNaNs(Sorry, I didn't see it clearly.）
>
> > > Given the rounding, flag_rounding_m
Uros Bizjak 于2024年11月7日周四 15:22写道：
>
> On Thu, Nov 7, 2024 at 6:58 AM Hongyu Wang wrote:
> >
> > Hi,
> >
> > We recently supports cbranchbf4 with AVX10_2 native bf16 comi
> > instructions, so do similar to cstorebf4.
> >
> > Bootstrapped & regtested on x86_64-pc-linux-gnu.
> > Ok for trunk?
> >
>
Hi Victor,
> On 31 Oct 2024, at 22:40, Victor Do Nascimento
> wrote:
>
> Implement -mcpu options for:
>
> - Cortex-A520AE
> - Cortex-A720AE
> - Cortex-R82AE
>
> These all implement the same feature sets as their non-AE
> counterparts, using the same scheduler and costs and differing only i
On Thu, Nov 7, 2024 at 12:43 AM Andrew Pinski wrote:
>
> For `(a | b) == 0`, we can "assert" on the true edge that
> both `a == 0` and `b == 0` but nothing on the false edge.
> For `(a | b) != 0`, we can "assert" on the false edge that
> both `a == 0` and `b == 0` but nothing on the true edge.
> T
On Thu, Nov 7, 2024 at 12:43 AM Andrew Pinski wrote:
>
> After the last patch, we also want to record `(A CMP B) != 0`
> as `(A CMP B)` and `(A CMP B) == 0` as `(A CMP B)` with the
> true/false edges swapped.
>
> This shows up more due to the new handling of
> `(A | B) ==/!= 0` in insert_predicate
Hi, all
-maddress-mode=long will let Pmode = DI_mode, but -mx32 request x32 ABI.
So raise an error to avoid ICE.
Bootstrapped and regtested, OK for trunk?
BRs,
Lin
gcc/ChangeLog:
PR target/117418
* config/i386/i386-options.cc (ix86_option_override_internal): raise an
er
On 11/7/24 5:52 PM, Richard Biener wrote:
On Thu, Nov 7, 2024 at 11:13 AM Tejas Belagod wrote:
On 11/7/24 2:36 PM, Richard Biener wrote:
On Thu, Nov 7, 2024 at 8:25 AM Tejas Belagod wrote:
On 11/6/24 6:02 PM, Richard Biener wrote:
On Wed, Nov 6, 2024 at 12:49 PM Tejas Belagod wrote:
En
Thanks for your suggestions and answer.
This is the current version. There is no problem in my test environment, but
also in the further testing, sent for review.
BRs,
Lin
-maddress-mode=long let Pmode = DI_mode, so zero extend 32-bit address to
64-bit and uses a 64-bit register as a pointer for
On Fri, Nov 8, 2024 at 10:21 AM Mayshao-oc wrote:
>
> > > -Original Message-
> > > From: Xi Ruoyao
> > > Sent: Thursday, November 7, 2024 1:12 PM
> > > To: Liu, Hongtao ; Mayshao-oc > > o...@zhaoxin.com>; Hongtao Liu
> > > Cc: gcc-patches@gcc.gnu.org; hubi...@ucw.cz; ubiz...@gmail.com;
hw instruction doesn't raise exceptions, turns sNAN into qNAN quietly,
and always round to nearest (even). Output denormals are always
flushed to zero and input denormals are always treated as zero. MXCSR
is not consulted nor updated.
W/o native instructions, flag_unsafe_math_optimizations is neede
On Fri, Nov 8, 2024 at 10:41 AM Hu, Lin1 wrote:
>
> Hi, all
>
> -maddress-mode=long will let Pmode = DI_mode, but -mx32 request x32 ABI.
> So raise an error to avoid ICE.
>
> Bootstrapped and regtested, OK for trunk?
>
> BRs,
> Lin
>
> gcc/ChangeLog:
>
> PR target/117418
> * config
On Thu, Nov 7, 2024 at 8:16 PM Richard Biener
wrote:
>
> On Thu, Nov 7, 2024 at 5:50 AM H.J. Lu wrote:
> > > > TARGET_PROMOTE_PROTOTYPES isn't defined for psABI purpose.
> > > > x86 psABI doesn't require it. GCC uses only the lower bits of incoming
> > > > arguments. But it isn't the GCC's j
> > -Original Message-
> > From: Xi Ruoyao
> > Sent: Thursday, November 7, 2024 1:12 PM
> > To: Liu, Hongtao ; Mayshao-oc > o...@zhaoxin.com>; Hongtao Liu
> > Cc: gcc-patches@gcc.gnu.org; hubi...@ucw.cz; ubiz...@gmail.com;
> > richard.guent...@gmail.com; Tim Hu(WH-RD) ; Silvia
> > Zhao(B
On Fri, Nov 8, 2024 at 1:21 PM Hongtao Liu wrote:
>
> On Fri, Nov 8, 2024 at 12:18 PM H.J. Lu wrote:
> >
> > On Fri, Nov 8, 2024 at 10:41 AM Hu, Lin1 wrote:
> > >
> > > Hi, all
> > >
> > > -maddress-mode=long will let Pmode = DI_mode, but -mx32 request x32 ABI.
> > > So raise an error to avoid I
> On Fri, Nov 8, 2024 at 10:21 AM Mayshao-oc wrote:
> > > > -Original Message-
> > > > From: Xi Ruoyao
> > > > Sent: Thursday, November 7, 2024 1:12 PM
> > > > To: Liu, Hongtao ; Mayshao-oc > > > o...@zhaoxin.com>; Hongtao Liu
> > > > Cc: gcc-patches@gcc.gnu.org; hubi...@ucw.cz; ubiz...
On Fri, Nov 8, 2024 at 12:18 PM H.J. Lu wrote:
>
> On Fri, Nov 8, 2024 at 10:41 AM Hu, Lin1 wrote:
> >
> > Hi, all
> >
> > -maddress-mode=long will let Pmode = DI_mode, but -mx32 request x32 ABI.
> > So raise an error to avoid ICE.
> >
> > Bootstrapped and regtested, OK for trunk?
> >
> > BRs,
>
>"Yuta Mukai (Fujitsu)" writes:
>> Thank you for pushing to trunk.
>> Can I also ask for a backport to GCC14?
>>
>> I have attached the patch for GCC14.
>> FP8 has been excluded from the list as it is not supported in GCC14.
>>
>> Bootstrapped/regtested on aarch64-unknown-linux-gnu.
>
>LGTM, thank
LGTM
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-11-08 14:57
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form1
From: xuli
form1:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_
From: xuli
form1:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
Thanks, Kito and yangyu!
在 2024/11/8 0:35, Yangyu Chen 写道:
Thanks for doing this!
On Nov 8, 2024, at 00:19, shiyul...@iscas.ac.cn wrote:
From: yulong
This patch adds norelax function attribute that be discussed in riscv-c-api-doc
PR#94.
URL:https://github.com/riscv-non-isa/riscv-c-api-doc/
On Fri, Nov 8, 2024 at 6:52 AM Hongtao Liu wrote:
> > > > PR target/117418
> > > > * config/i386/i386-options.cc (ix86_option_override_internal):
> > > > raise an
> > > > error with option -mx32 -maddress-mode=long.
> > > >
> > > > gcc/testsuite/ChangeLog:
> > > >
> > > >
On Fri, Nov 8, 2024 at 7:30 AM Tejas Belagod wrote:
>
> On 11/7/24 5:52 PM, Richard Biener wrote:
> > On Thu, Nov 7, 2024 at 11:13 AM Tejas Belagod wrote:
> >>
> >> On 11/7/24 2:36 PM, Richard Biener wrote:
> >>> On Thu, Nov 7, 2024 at 8:25 AM Tejas Belagod
> >>> wrote:
>
> On 11/6/24
On 2024-11-07 23:14, Christophe Lyon wrote:
On Thu, 7 Nov 2024 at 19:09, Torbjorn SVENSSON
wrote:
On 2024-11-07 16:33, Richard Earnshaw (lists) wrote:
On 06/11/2024 19:50, Torbjorn SVENSSON wrote:
On 2024-11-06 19:06, Richard Earnshaw (lists) wrote:
On 06/11/2024 13:50, Torbjorn SVEN
On Thu, Nov 7, 2024 at 10:13 PM Andrew Pinski wrote:
>
> This is the followup as mentioned in
> https://gcc.gnu.org/pipermail/gcc-patches/2024-November/667987.html .
> We need to canonicalize the compares using tree_swap_operands_p instead
> of checking CONSTANT_CLASS_P.
>
> Bootstrapped and teste
> -Original Message-
> From: Jeff Law
> Sent: Thursday, November 7, 2024 8:08 PM
> To: Tamar Christina ; Li, Pan2 ;
> Richard Biener
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
> rdapp@gmail.com
> Subject: Re: [PATCH v2 01/10] Match: Simplify branch form
On Fri, Nov 8, 2024 at 5:32 AM H.J. Lu wrote:
>
> On Thu, Nov 7, 2024 at 8:16 PM Richard Biener
> wrote:
> >
> > On Thu, Nov 7, 2024 at 5:50 AM H.J. Lu wrote:
>
> > > > > TARGET_PROMOTE_PROTOTYPES isn't defined for psABI purpose.
> > > > > x86 psABI doesn't require it. GCC uses only the lower
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