Re: [PATCH] c++: End lifetime of objects in constexpr after destructor call [PR71093]

On Sun, 10 Dec 2023, Jason Merrill wrote: > On 12/10/23 05:22, Richard Biener wrote: > >> Am 09.12.2023 um 21:13 schrieb Jason Merrill : > >> > >> On 11/2/23 21:18, Nathaniel Shead wrote: > >>> Bootstrapped and regtested on x86-64_pc_linux_gnu. > >>> I'm not entirely sure if the change I made to

Re: [PATCHv2 2/2] MATCH: (convert)(zero_one !=/== 0/1) for outer type and zero_one type are the same

On Sun, Dec 10, 2023 at 8:57 PM Andrew Pinski wrote: > > When I moved two_value to match.pd, I removed the check for the {0,+-1} > as I had placed it after the {0,+-1} case for cond in match.pd. > In the case of {0,+-1} and non boolean, before we would optmize those > case to just `(convert)a` but

Re: [PATCH 1/2] analyzer: Remove check of unsigned_char in maybe_undo_optimize_bit_field_compare.

On Sun, Dec 10, 2023 at 8:57 PM Andrew Pinski wrote: > > From: Andrew Pinski > > The check for the type seems unnecessary and gets in the way sometimes. > Also with a patch I am working on for match.pd, it causes a failure to happen. > Before my patch the IR was: > _1 = BIT_FIELD_REF ; > _2 =

Re: PING^2: [PATCH v2] Only allow (int)trunc(x) to (int)x simplification with -ffp-int-builtin-inexact [PR107723]

On Mon, Dec 11, 2023 at 7:39 AM Xi Ruoyao wrote: > > Ping again. OK, sorry for the delay. Richard. > On Fri, 2023-12-01 at 13:44 +0800, Xi Ruoyao wrote: > > Ping. > > > > On Fri, 2023-11-24 at 17:09 +0800, Xi Ruoyao wrote: > > > With -fno-fp-int-builtin-inexact, trunc is not allowed to raise >

Re: [v3 PATCH] Simplify vector ((VCE (a cmp b ? -1 : 0)) < 0) ? c : d to just (VCE ((a cmp b) ? (VCE c) : (VCE d))).

On Mon, Dec 11, 2023 at 7:51 AM liuhongt wrote: > > > since you are looking at TYPE_PRECISION below you want > > VECTOR_INTIEGER_TYPE_P here as well? The alternative > > would be to compare TYPE_SIZE. > > > > Some of the checks feel redundant but are probably good for > > documentation purposes.

Re: [PATCH 1/2] libstdc++: Atomic wait/notify ABI stabilization

Ref: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636805.html, https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636804.html I found a couple of bugs in this patch set. #1: In atomic_wait.h, we have __wait_flags defined to include: __do_spin = 4, __spin_only = 8

Re: [r14-5930 Regression] FAIL: gcc.c-torture/compile/libcall-2.c -Os (test for excess errors) on Linux/x86_64

>> Pushed as >> https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=b74981b5cf32ebf4bfffd25e7174b5c80243447a Somehow I pushed the wrong commit, we should skip the test and not xfail. This showed up in https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/802839.html So, new commit push as o

Re: [v3 PATCH] Simplify vector ((VCE (a cmp b ? -1 : 0)) < 0) ? c : d to just (VCE ((a cmp b) ? (VCE c) : (VCE d))).

On Mon, Dec 11, 2023 at 4:14 PM Richard Biener wrote: > > On Mon, Dec 11, 2023 at 7:51 AM liuhongt wrote: > > > > > since you are looking at TYPE_PRECISION below you want > > > VECTOR_INTIEGER_TYPE_P here as well? The alternative > > > would be to compare TYPE_SIZE. > > > > > > Some of the check

[PATCH] Testsuite: restrict test to nonpic targets

The test is currently failing on x86_64-apple-darwin. This patch requires nonpic, as suggested in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112297 by Andrew Pinski. OK to commit? FX 0001-Testsuite-restrict-test-to-nonpic-targets.patch Description: Binary data

Re: [PATCH] RISC-V: Add vectorized strcmp.

> FYI. I have the some failures as juzhe mentioned, with the emulator > qemu version qemu-riscv64 version 8.1.93 (v8.2.0-rc3). The entire log > may look like below: > > Executing on host: > /home/box/panli/riscv-gnu-toolchain/build-gcc-newlib-stage2/gcc/xgcc > -B/home/box/panli/riscv-gnu-toolcha

[PATCH] Testsuite, i386: mark test as requiring dfp

Test currently fails on darwin with: error: decimal floating-point not supported for this target Pushed as obvious fix. FX 0001-Testsuite-i386-mark-test-as-requiring-dfp.patch Description: Binary data

[PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

Hi, Richard. This patch fixes an ICE on record_use during RTL_SSA initialization RISC-V backend VSETVL PASS. This is the ICE: 0x11a8603 partial_subreg_p(machine_mode, machine_mode) ../../../../gcc/gcc/rtl.h:3187 0x3b695eb rtl_ssa::function_info::record_use(rtl_ssa::function_info::build_

[PATCH] testsuite: Disable -fstack-protector* for some strub tests

Hi! In our distro builds, we test with RUNTESTFLAGS='--target_board=unix\{,-fstack-protector-strong\}' because SSP is something we use widely in the distribution. 4 new strub test FAIL with that option though, as can be seen with a simple make check-gcc check-g++ RUNTESTFLAGS='--target_board=unix

[PATCH] Testsuite, asan, darwin: Adjust output pattern

Since the last import from upstream libsanitizer, the output has changed and now looks more like this: READ of size 6 at 0x7ff7beb2a144 thread T0 #0 0x101cf7796 in MemcmpInterceptorCommon(void*, int (*)(void const*, void const*, unsigned long), void const*, void const*, unsigned long) saniti

RE: [PATCH 15/21]middle-end: [RFC] conditionally support forcing final edge for debugging

> -Original Message- > From: Richard Biener > Sent: Monday, December 11, 2023 7:38 AM > To: Richard Sandiford > Cc: Tamar Christina ; gcc-patches@gcc.gnu.org; nd > ; j...@ventanamicro.com > Subject: Re: [PATCH 15/21]middle-end: [RFC] conditionally support forcing > final > edge for debug

Re: [PATCH v8] c++: implement P2564, consteval needs to propagate up [PR107687]

Hi Marek, The patch is causing three failures on x86_64-apple-darwin21: > FAIL: g++.dg/cpp2a/concepts-explicit-inst1.C -std=c++20 scan-assembler > _Z1gI1XEvT_ > FAIL: g++.dg/cpp2a/concepts-explicit-inst1.C -std=c++20 scan-assembler > _Z1gI1YEvT_ > FAIL: g++.dg/cpp2a/consteval-prop6.C -std=c++20

Re: [PATCH] testsuite: Disable -fstack-protector* for some strub tests

On Mon, 11 Dec 2023, Jakub Jelinek wrote: > Hi! > > In our distro builds, we test with > RUNTESTFLAGS='--target_board=unix\{,-fstack-protector-strong\}' > because SSP is something we use widely in the distribution. > 4 new strub test FAIL with that option though, as can be > seen with a simple >

RE: [PATCH 15/21]middle-end: [RFC] conditionally support forcing final edge for debugging

On Mon, 11 Dec 2023, Tamar Christina wrote: > > -Original Message- > > From: Richard Biener > > Sent: Monday, December 11, 2023 7:38 AM > > To: Richard Sandiford > > Cc: Tamar Christina ; gcc-patches@gcc.gnu.org; nd > > ; j...@ventanamicro.com > > Subject: Re: [PATCH 15/21]middle-end: [R

Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

> In record_use: > > if (HARD_REGISTER_NUM_P (regno) > && partial_subreg_p (use->mode (), mode)) > > Assertion failed on partial_subreg_p which is: > > inline bool > partial_subreg_p (machine_mode outermode, machine_mode innermode) > { > /* Modes involved in a subreg must be orde

Re: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

>> I'm not sure we'd want to model it as subreg here (endianness etc?). >> Could we have a VLS-mode equivalent for the VLA mode that only holds >> one element? Yes. This is the last chance to walk around it here but we will end up with more patterns. since reduction dest operand always LMUL = 1 m

Re: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

I think it's reasonable refactor reduction instruction pattern work around this issue. Going to send a patch to apply this solution. So drop this patch. Sorry for bothering Richard S. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-12-11 17:01 To: Juzhe-Zhong; gcc-patches CC: rdapp.gcc; r

Re: [PATCH v3 11/11] c: Add new -Wdeclaration-missing-parameter-type permerror

* Marek Polacek: > On Mon, Nov 20, 2023 at 10:56:42AM +0100, Florian Weimer wrote: >> This used to be a warning, enabled by default, without its own option. > > I think this patch is OK now. > >> A subsequent change could improve diagnostics and provide spelling >> hints for declarations like “v

Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

> Yes. This is the last chance to walk around it here but we will end up with > more patterns. > since reduction dest operand always LMUL = 1 mode. > > So, when -march=rv64gcv, the dest mode should be V4SI, if > -march=rv64gcv_zvl256b, the dest mode should be V8SI. > ...etc.  Different TARGET_MI

[PATCH] ipa/92606 - properly handle no_icf attribute for variables

The following adds no_icf handling for variables where the attribute was rejected. It also fixes the check for no_icf by checking both the source and the targets decl. Bootstrap / regtest running on x86_64-unknown-linux-gnu. This would solve the AVR issue with merging of "progmem" attributed and

Re: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

Oh. I just confirmed. V1SI make perfect sens since we never apply partial vectorization for VLSmode. Drop this patch and going to refactor reduction pattern to fix this issue. Thanks. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-12-11 17:11 To: juzhe.zh...@rivai.ai; gcc-patches CC: rdapp

Re: [PATCH] treat argp-based mem as frame related in dse

Hi, Thanks for your quick reply! Jeff Law writes: > On 12/10/23 20:07, Jiufu Guo wrote: > > I'm having a bit of a hard time convincing myself this is correct > though. I can't see how rewriting the load to read the source of the > prior store is unsafe. If that fixes a problem,

[patch,avr] PR112944: Support .rodata in RAM for AVR64* and AVR128* devices

This is a patch that locates .rodata in flash for some AVR devices that can support it. All new functionality depends on Binutils PR31124 and is switched on by configure checks for the new emulations. https://sourceware.org/PR31124 For explanation of the gcc part see commit message below. Most

RE: [PATCH 9/21]middle-end: implement vectorizable_early_exit for codegen of exit code

On Mon, 11 Dec 2023, Tamar Christina wrote: > > > > > > > > Hmm, but we're visiting them then? I wonder how you get along > > > > without doing adjustmens on the uses if you consider > > > > > > > > _1 = a < b; > > > > _2 = c != d; > > > > _3 = _1 | _2; > > > > if (_3 != 0) > > >

[PATCH 0/3] RISC-V: vectorised memory operations

This patchset permits generation of inlined vectorised code for movmem, setmem and cmpmem, if and only if the operation size is at least one and at most eight vector registers' worth of data. Further vectorisation rapidly becomes debatable due to code size concerns; however, for these simple cas

[PATCH 2/3] RISC-V: setmem for RISCV with V extension

gcc/ChangeLog * config/riscv/riscv-protos.h (riscv_vector::expand_vec_setmem): New function declaration. * config/riscv/riscv-string.cc (riscv_vector::expand_vec_setmem): New function: this generates an inline vectorised memory set, if and only if we know the entire operation

[PATCH 1/3] RISC-V: movmem for RISCV with V extension

gcc/ChangeLog * config/riscv/riscv.md (movmem): Use riscv_vector::expand_block_move, if and only if we know the entire operation can be performed using one vector load followed by one vector store gcc/testsuite/ChangeLog * gcc.target/riscv/rvv/base/movmem-1.c: New test --- gcc/

[PATCH 3/3] RISC-V: cmpmem for RISCV with V extension

gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_vector::expand_vec_cmpmem): New function declaration. * config/riscv/riscv-string.cc (riscv_vector::expand_vec_cmpmem): New function; this generates an inline vectorised memory compare, if and only if we know the entire oper

[PATCH 2/3] RISC-V: setmem for RISCV with V extension

Hi, Thanks for contributing this. +/* Select appropriate LMUL for a single vector operation based on + byte size of data to be processed. + On success, return true and populate lmul_out. + If length_in is too wide for a single vector operation, return false + and leave lmul_out unchanged.

[committed] d: Merge upstream dmd, druntime 2bbf64907c, phobos b64bfbf91

Hi, This patch merges the D front-end and runtime library with upstream dmd 2bbf64907c, and the standard library with phobos b64bfbf91. Synchronizing with the upstream release of v2.106.0. D front-end changes: - Import dmd v2.106.0. D runtime changes: - Import druntime v2.106.0. Phob

Re: [PATCH 1/3] RISC-V: movmem for RISCV with V extension

Hi Sergei, thanks for contributing this! Small general remarks/nits upfront: The code looks like it hasn't been run through clang-format or similar. Please make sure that it adheres to the GNU coding conventions. The same applies to comments. Some of them start in lowercase. As you rely on t

Re: [committed] d: Merge upstream dmd, druntime 2bbf64907c, phobos b64bfbf91

Excerpts from Iain Buclaw's message of Dezember 11, 2023 11:07 am: > Hi, > > This patch merges the D front-end and runtime library with upstream dmd > 2bbf64907c, and the standard library with phobos b64bfbf91. > > Synchronizing with the upstream release of v2.106.0. > ... > diff --git a/gcc/d

Re: [PATCH 1/3] RISC-V: movmem for RISCV with V extension

Ah, please also ensure to include (and follow) the stringop_strategy checks. (LIBCALL, VECTOR) The naming is a bit unfortunate still but that need not be fixed in this patch. Regards Robin

[PATCH]middle-end: Mark all control flow as used_in_scope.

Hi All, While compiling SPECCPU 2017 I ran accross the reason (I had forgotten) why my initial patch marked all control statements as used in scope and not just gconds: There are other statements that can introduce multiple exits, like switch statements. If we ignore them as not relevant we nev

[PATCH] ada: Fix Ada bootstrap on FreeBSD

Ada bootstrap on FreeBSD/amd64 was also broken by the recent warning changes: terminals.c: In function 'allocate_pty_desc': terminals.c:1200:12: error: implicit declaration of function 'openpty'; did you mean 'openat'? [-Wimplicit-function-declaration] 1200 | status = openpty (&master_fd, &slav

Re: [PATCH] ada: Fix Ada bootstrap on FreeBSD

Rainer Orth writes: > Ada bootstrap on FreeBSD/amd64 was also broken by the recent warning > changes: > > terminals.c: In function 'allocate_pty_desc': > terminals.c:1200:12: error: implicit declaration of function 'openpty'; did > you > mean 'openat'? [-Wimplicit-function-declaration] > 1200

Re: [PATCH] Testsuite, asan, darwin: Adjust output pattern

Hi FX, > On 11 Dec 2023, at 08:43, FX Coudert wrote: > > Since the last import from upstream libsanitizer, the output has changed > and now looks more like this: > > READ of size 6 at 0x7ff7beb2a144 thread T0 >#0 0x101cf7796 in MemcmpInterceptorCommon(void*, int (*)(void const*, void > con

Re: [PATCH] expmed: Perform mask extraction via QImode [PR112773].

What also works is something like: scalar_mode extract_mode = innermode; if (GET_MODE_CLASS (outermode) == MODE_VECTOR_BOOL) extract_mode = smallest_int_mode_for_size (GET_MODE_PRECISION (innermode)); however > So yes, I guess we need to answer BImod

Re: [PATCH]middle-end: Mark all control flow as used_in_scope.

On Mon, 11 Dec 2023, Tamar Christina wrote: > Hi All, > > While compiling SPECCPU 2017 I ran accross the reason (I had forgotten) why my > initial patch marked all control statements as used in scope and not just > gconds: There are other statements that can introduce multiple exits, like > swit

Re: [PATCH v4] [tree-optimization/110279] Consider FMA in get_reassociation_width

On Wed, Nov 29, 2023 at 3:36 PM Di Zhao OS wrote: > > > -Original Message- > > From: Richard Biener > > Sent: Tuesday, November 21, 2023 9:01 PM > > To: Di Zhao OS > > Cc: gcc-patches@gcc.gnu.org > > Subject: Re: [PATCH v4] [tree-optimization/110279] Consider FMA in > > get_reassociation

Re: [PATCH] libstdc++: add ARM SVE support to std::experimental::simd

Richard Sandiford writes: > template > struct _SveMaskWrapper > { > ... > > _GLIBCXX_SIMD_INTRINSIC constexpr value_type > operator[](size_t __i) const > { > return _BuiltinSveMaskType::__sve_mask_active_count( > _BuiltinSveVectorType::__s

RE: [PATCH] RISC-V: Add vectorized strcmp.

Hi Robin, I reduced the SZ size from 10 to 1, and the below case with SZ = 2 will fail. The failed location is "foo is 50, foo2 is 12800, i,j is 1, 0". #define SZ 2 const char *s[SZ] = {"1", "12345678901234567889012345678901234567890"}; Executing on host: /home/pli/gcc/111/riscv-gnu-toolcha

Backport of "fixincludes: Update darwin_flt_eval_method for macOS 14"

Hi, I’d like to backport the fixincludes for macOS 14 SDK at https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=93f803d53b5ccaabded9d7b4512b54da81c1c616 to the active branches, i.e. 13, 12 and 11 (unless I am mistaken). The fix has been there for months, it’s stable and very specific. Without it, w

Re: [PATCH] tree-cfg: Fix misleading error message in verify_gimple_assign_single

Got it, thanks! It is really confusing >,< What about the first one? For case MEM_REF. 在 2023年12月11日星期一，Richard Biener 写道： > On Sun, Dec 10, 2023 at 4:00 PM xndcn wrote: > > > > Hi, I am a newbie in GCC, and I do not have access to git repo. > > > > I found some misleading error messages in ver

Re: [PATCH] tree-cfg: Fix misleading error message in verify_gimple_assign_single

On Mon, Dec 11, 2023 at 12:39 PM xndcn wrote: > > Got it, thanks! It is really confusing >,< > What about the first one? For case MEM_REF. The same - the LHS determines this is a store, if it is the RHS is invalid as diagnosed (it needs to go through a temporary). Richard. > 在 2023年12月11日星期一，

Re: [PATCH v7 3/5] OpenMP: Pointers and member mappings

Hi Julian, On 07.12.23 18:24, Julian Brown wrote: On Wed, 6 Dec 2023 12:36:34 +0100 Tobias Burnus wrote: LGTM, except for: * The 'target exit data' handling - comments below - looks a bit fishy/inconsistent. ... Thus, I wonder whether that shouldn't be instead OMP_CLAUSE_MAP_KIND (node

[Patch] OpenMP: Minor '!$omp allocators' cleanup - and still: Re: [patch] OpenMP/Fortran: Implement omp allocators/allocate for ptr/allocatables

Hi Thomas & Jakub, I included a minor cleanup patch - but the rest is really a bunch of RFC. I intent to commit that patch as obvious, unless there are further comments. On 09.12.23 16:14, Jakub Jelinek wrote: There were 3 reasons to add GOMP_alloc (and 1 for GOMP_free): 1) when it was added,

Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

"juzhe.zh...@rivai.ai" writes: > I think it's reasonable refactor reduction instruction pattern work around > this issue. > > Going to send a patch to apply this solution. > > So drop this patch. Sorry for bothering Richard S. It wasn't a bother. On the patch: as things stand, we try to make t

Re: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

Thanks Richard. It would be great if you are ok I can fix it in RTL_SSA. I leverage your LRA patch in RTL_SSA: else { // Record the mode of the largest use. The choice is arbitrary if // the instruction (unusually) references the same register in two // different but equa

[PATCH] RISC-V: Robostify shuffle index used by vrgather and fix regression

Notice there are some regression FAILs: FAIL: gcc.target/riscv/rvv/autovec/pr110950.c -O3 -ftree-vectorize scan-assembler-times vslide1up\\.vx 1 FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c -std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax scan-assembler-times

Re: [PATCH] tree-cfg: Fix misleading error message in verify_gimple_assign_single

Thanks, now I have totally understand! I think it deserves a clearer prompt, but I do not have a better idea currently. So forget it, thanks! 在 2023年12月11日星期一，Richard Biener 写道： > On Mon, Dec 11, 2023 at 12:39 PM xndcn wrote: > > > > Got it, thanks! It is really confusing >,< > > What about the

Re: [PATCH v3] aarch64: Implement the ACLE instruction/data prefetch functions.

Victor Do Nascimento writes: > Key changes in v3: > * Implement the `require_const_argument' function to ensure the nth > argument in EXP represents a const-type argument in the valid range > given by [minval, maxval), forgoing expansion altogether when an > invalid argument is detected ea

Re: [PATCH] RISC-V: Robostify shuffle index used by vrgather and fix regression

> Robostify the gather index to fixe those FAILs. OK. They must have somehow slipped through because I pruned vlmax tests for comparison of different vlens. Regards Robin

Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

"juzhe.zh...@rivai.ai" writes: > Thanks Richard. > > It would be great if you are ok I can fix it in RTL_SSA. > I leverage your LRA patch in RTL_SSA: > > else > { > // Record the mode of the largest use. The choice is arbitrary if > // the instruction (unusually) references the

[COMMITTED V2] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

This patch fixes an ICE on record_use during RTL_SSA initialization RISC-V backend VSETVL PASS. This is the ICE: 0x11a8603 partial_subreg_p(machine_mode, machine_mode) ../../../../gcc/gcc/rtl.h:3187 0x3b695eb rtl_ssa::function_info::record_use(rtl_ssa::function_info::build_info&, rtl_s

Re: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS

Thanks Richard. Committed with V2: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640172.html juzhe.zh...@rivai.ai From: Richard Sandiford Date: 2023-12-11 20:12 To: juzhe.zhong\@rivai.ai CC: Robin Dapp; gcc-patches Subject: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for

[PATCH] i386: Fix missed APX_NDD check for shift/rotate expanders [PR 112943]

Hi, The ashl/lshr/ashr expanders calls ix86_expand_binary_operator, while they will be called for some post-reload split, and TARGET_APX_NDD is required for these calls to avoid force-load to memory at postreload stage. Bootstrapped/regtested on x86-64-pc-linux-gnu{-m32,} Ok for master? gcc/Cha

Re: [PATCH] i386: Fix missed APX_NDD check for shift/rotate expanders [PR 112943]

On Mon, Dec 11, 2023 at 08:20:20PM +0800, Hongyu Wang wrote: LGTM but will defer review of the patch to Hongtao or Uros. > +__int128 u128_2 = (9223372036854775808 << 4) * foo0_u8_0; /* { > dg-warning "integer constant is so large that it is unsigned" "so large" } */ Just you can use (922337

Re: [PATCH] i386: Fix missed APX_NDD check for shift/rotate expanders [PR 112943]

> > +__int128 u128_2 = (9223372036854775808 << 4) * foo0_u8_0; /* { > > dg-warning "integer constant is so large that it is unsigned" "so large" } > > */ > > Just you can use (9223372036854775807LL + (__int128) 1) instead of > 9223372036854775808 > to avoid the warning. > The testcase will I

[PATCH] wrong code on m68k with -mlong-jump-table-offsets and -malign-int (PR target/112413)

On m68k the compiler assumes that the PC-relative jump-via-jump-table instruction and the jump table are adjacent with no padding in between. When -mlong-jump-table-offsets is combined with -malign-int, a 2-byte nop may be inserted before the jump table, causing the jump to add the fetched offset

Re: [PATCH] RISC-V: Add vectorized strcmp.

Hi Pan, > I reduced the SZ size from 10 to 1, and the below case with SZ = 2 > will fail. The failed location is "foo is 50, foo2 is 12800, i,j is > 1, 0". > > #define SZ 2 > > const char *s[SZ] = {"1", > "12345678901234567889012345678901234567890"}; Thanks. I still cannot reproduce but I thi

Re: Backport of "fixincludes: Update darwin_flt_eval_method for macOS 14"

Hi FX, > On 11 Dec 2023, at 11:37, FX Coudert wrote: > I’d like to backport the fixincludes for macOS 14 SDK at > https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=93f803d53b5ccaabded9d7b4512b54da81c1c616 > to the active branches, i.e. 13, 12 and 11 (unless I am mistaken). > > The fix has been th

RE: [PATCH] RISC-V: Add vectorized strcmp.

Yes, I test the patch with all below configurations and there is no failure now. That would be great! riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m1 riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel

Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension

On Mon, Dec 11, 2023 at 5:48 PM Sergei Lewis wrote: > > gcc/ChangeLog > > * config/riscv/riscv-protos.h (riscv_vector::expand_vec_setmem): New > function > declaration. > > * config/riscv/riscv-string.cc (riscv_vector::expand_vec_setmem): New > function: this generates an inline v

[PATCH] RISC-V: testsuite: Fix strcmp-run.c test.

Hi, this fixes expectations in the strcmp-run test which would sometimes fail with newlib. The test expects libc strcmp return values and asserts the vectorized result is similar to those. Therefore hard-code the expected results instead of relying on a strcmp call. Pan has already tested in a

Re: [PATCH] RISC-V: Add vectorized strcmp.

> Yes, I test the patch with all below configurations and there is no failure > now. That would be great! Thank you! I posted it as a patch now: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640182.html Regards Robin

Re: [PATCH] RISC-V: testsuite: Fix strcmp-run.c test.

lgtm. Replied Message FromRobin DappDate12/11/2023 21:40 Togcc-patches,palmer,Kito Cheng,jeffreyalaw,juzhe.zh...@rivai.ai,Li, Pan2 Ccrdapp@gmail.comSubject[PATCH] RISC-V: testsuite: Fix strcmp-run.c test.Hi, this fixes expectations in the strcmp-run test which would sometimes fail with

Re: [PATCH] testsuite: adjust call to abort in excess-precision-12

Hello, > Why wouldn't they have abort and what else does __builtin_abort () expand > to? It expands to abort but works around the "abort is undeclared" error. > There are 2000+ other tests in gcc.target/i386/ which call abort (), > not __builtin_abort (), after including directly or indirectly

[PATCH v2] testsuite: adjust call to abort in excess-precision-12

On non-hosted targets, cstdlib may not be sufficient to have abort defined, but it should be for std::abort. gcc/testsuite/ChangeLog: * g++.target/i386/excess-precision-12.C: call std::abort instead of abort. --- Changed from calling __builtin_abort to std::abort, as advised. Ok for mas

Re: [PATCH v2] testsuite: adjust call to abort in excess-precision-12

On Mon, Dec 11, 2023 at 02:35:52PM +0100, Marc Poulhiès wrote: > On non-hosted targets, cstdlib may not be sufficient to have abort > defined, but it should be for std::abort. > > gcc/testsuite/ChangeLog: > > * g++.target/i386/excess-precision-12.C: call std::abort instead of > abort. > --

Re: [PATCH V3 4/4] OpenMP: Permit additional selector properties

This patch LGTM. Likewise 'LGTM' are patches 1/4 and 2/4, in line with my previous comments. (Those are unchanged to previous round.) Thanks for the patches! I still have to look at 3/4, which is large and did see some changes between v2 and v3. (Overall they seem to be really nice!) Tobias O

Re: [PATCH 1/2] analyzer: Remove check of unsigned_char in maybe_undo_optimize_bit_field_compare.

On Mon, 2023-12-11 at 09:04 +0100, Richard Biener wrote: > On Sun, Dec 10, 2023 at 8:57 PM Andrew Pinski > wrote: > > > > From: Andrew Pinski > > > > The check for the type seems unnecessary and gets in the way > > sometimes. > > Also with a patch I am working on for match.pd, it causes a failu

[PATCH] Add myself to write after approval

Hi, I would like to add myself to write after approval, is it ok for master? Thanks, Paul Iannetta ---8<--- ChangeLog: * MAINTAINERS: Add myself to write after approval Signed-off-by: Paul Iannetta --- MAINTAINERS | 1 + 1 file

Re: [PATCH v2 5/6] libgomp, nvptx: Cuda pinned memory

Hi! On 2023-12-08T17:44:14+0100, Tobias Burnus wrote: > On 08.12.23 15:09, Thomas Schwinge wrote: >>> On 22/11/2023 17:07, Tobias Burnus wrote: Let's start with the patch itself: > --- a/libgomp/target.c > +++ b/libgomp/target.c > ... > +static struct gomp_device_descr *

Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension

The thinking here is that using the largest possible LMUL when we know the operation will fit in fewer registers potentially leaves performance on the table - indirectly, due to the unnecessarily increased register pressure, and also directly, depending on the implementation. On Mon, Dec 11, 2023

Re: Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension

I think we should leave it to user choice. --param=riscv-autovec-lmul=m1/m2/m4/m8/dynamic. So use TARGET_MAX_LMUL should be more reasonable. juzhe.zh...@rivai.ai From: Sergei Lewis Date: 2023-12-11 22:58 To: juzhe.zh...@rivai.ai CC: gcc-patches; Robin Dapp; Kito.cheng; jeffreyalaw Subject: R

Re: Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension

...oh, and keep the current approach if riscv-autovec-lmul=dynamic. Makes perfect sense - thanks! On Mon, Dec 11, 2023 at 3:01 PM 钟居哲 wrote: > I think we should leave it to user choice. > > --param=riscv-autovec-lmul=m1/m2/m4/m8/dynamic. > > So use TARGET_MAX_LMUL should be more reasonable. > >

[PATCH v4] aarch64: SVE/NEON Bridging intrinsics

ACLE has added intrinsics to bridge between SVE and Neon. The NEON_SVE Bridge adds intrinsics that allow conversions between NEON and SVE vectors. This patch adds support to GCC for the following 3 intrinsics: svset_neonq, svget_neonq and svdup_neonq gcc/ChangeLog: * config.gcc: Adds ne

Re: [pushed] configure, libquadmath: Remove unintended AC_CHECK_LIBM [PR111928]

On Mon, Oct 23, 2023 at 02:18:39PM +0100, Iain Sandoe wrote: > This is a partial reversion of r14-4825-g6a6d3817afa02b to remove an > unintended change. > > Tested with x86_64-linux X arm-none-eabi (and x86_64-darwin X arm-non-eabi > and native x86_64-darwin bootstrap. Also reported by the OP to

Ping: [PATCH] Treat "p" in asms as addressing VOIDmode

Ping --- check_asm_operands was inconsistent about how it handled "p" after RA compared to before RA. Before RA it tested the address with a void (unknown) memory mode: case CT_ADDRESS: /* Every address operand can be reloaded to fit. */ result = result

Ping: [PATCH] Add a late-combine pass [PR106594]

Ping --- This patch adds a combine pass that runs late in the pipeline. There are two instances: one between combine and split1, and one after postreload. The pass currently has a single objective: remove definitions by substituting into all uses. The pre-RA version tries to restrict itself to

Re: [PATCH] Treat "p" in asms as addressing VOIDmode

On 11/27/23 05:12, Richard Sandiford wrote: check_asm_operands was inconsistent about how it handled "p" after RA compared to before RA. Before RA it tested the address with a void (unknown) memory mode: case CT_ADDRESS: /* Every address operand can be reloaded to f

Re: [PATCH] wrong code on m68k with -mlong-jump-table-offsets and -malign-int (PR target/112413)

On 12/11/23 05:51, Mikael Pettersson wrote: On m68k the compiler assumes that the PC-relative jump-via-jump-table instruction and the jump table are adjacent with no padding in between. When -mlong-jump-table-offsets is combined with -malign-int, a 2-byte nop may be inserted before the jump t

Re: [PATCH] treat argp-based mem as frame related in dse

On 12/11/23 02:26, Jiufu Guo wrote: Hi, Thanks for your quick reply! Jeff Law writes: On 12/10/23 20:07, Jiufu Guo wrote: I'm having a bit of a hard time convincing myself this is correct though. I can't see how rewriting the load to read the source of the prior store is unsafe. If t

Re: [PATCH] aarch64: Fix wrong code for bfloat when f16 is enabled [PR 111867]

Andrew Pinski writes: > The problem here is when f16 is enabled, movbf_aarch64 accepts `Ufc` > as a constraint: > [ w, Ufc ; fconsts , fp16 ] fmov\t%h0, %1 > But that is for fmov values and in this case fmov represents f16 rather than > bfloat16 values. > This means we would get

Re: [PATCH] untyped calls: enable target switching [PR112334]

On 12/1/23 08:10, Alexandre Oliva wrote: On Dec 1, 2023, Alexandre Oliva wrote: Also tested on arm-eabi, but it's *not* enough (or needed) to fix the PR, there's another bug lurking there, with a separate patch coming up. Here it is. The computation of apply_args_size and apply_re

Re: [PATCH v2 5/6] libgomp, nvptx: Cuda pinned memory

On 11.12.23 15:31, Thomas Schwinge wrote: On 2023-12-08T17:44:14+0100, Tobias Burnus wrote: On 08.12.23 15:09, Thomas Schwinge wrote: On 22/11/2023 17:07, Tobias Burnus wrote: Let's start with the patch itself: --- a/libgomp/target.c +++ b/libgomp/target.c ... +static struct gomp_device_desc

Re: [PATCH] libgccjit Fix a RTL bug for libgccjit

On 11/20/23 16:54, David Malcolm wrote: On Mon, 2023-11-20 at 16:38 -0700, Jeff Law wrote: On 11/20/23 15:46, David Malcolm wrote: On Fri, 2023-11-17 at 14:09 -0700, Jeff Law wrote: On 11/17/23 14:08, Antoni Boucher wrote: In contrast with the other frontends, libgccjit can be executed

Re: [PATCH] Treat "p" in asms as addressing VOIDmode

On Mon, 11 Dec 2023, Jeff Law wrote: > > This happened with the late-combine pass that I posted in October: > > https://gcc.gnu.org/pipermail/gcc-patches/2023-October/634166.html > > which in turn triggered an error from aarch64_print_operand_address. > > > > This patch takes the (hopefully) cons

Re: [RFC PATCH 1/1] nix: add a simple flake nix shell

Hi all, >Are you backing down from that opinion and deciding that this proposal is, indeed, after all specific to NixOS and only NixOS and is neither needed nor used on any other distro? I may be misreading the conversation, so let's restart it. Why should my RFC be inside the distro's repositor

Re: [RFC] RISC-V: Support RISC-V Profiles in -march option.

On 11/20/23 12:14, Jiawei wrote: Supports RISC-V profiles[1] in -march option. Default input set the profile is before other formal extensions. [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc gcc/ChangeLog: * common/config/riscv/riscv-common.cc (struct riscv_pro

Re: Ping: [PATCH] Add a late-combine pass [PR106594]

Hi Richard, I have tested the new pass on riscv64 and while it did exhibit some regressions, none of them are critical. Mostly, test expectations will need to be adjusted - no new execution failures. As mentioned in the initial discussion it does help us get the behavior we want but, as of now,

[pushed] c++: add fixed testcase [PR63378]

We accept this testcase since r12-4453-g79802c5dcc043a. PR c++/63378 gcc/testsuite/ChangeLog: * g++.dg/template/fnspec3.C: New test. --- gcc/testsuite/g++.dg/template/fnspec3.C | 20 1 file changed, 20 insertions(+) create mode 100644 gcc/testsuite/g++.dg/t

[PATCH v3 1/6] libgomp: basic pinned memory on Linux

Implement the OpenMP pinned memory trait on Linux hosts using the mlock syscall. Pinned allocations are performed using mmap, not malloc, to ensure that they can be unpinned safely when freed. This implementation will work OK for page-scale allocations, and finer-grained allocations will be impl

[PATCH v3 0/6] libgomp: OpenMP pinned memory omp_alloc

This patch series is a rework of the v2 series I posted in August: https://patchwork.sourceware.org/project/gcc/list/?series=23763&state=%2A&archive=both This version addresses most of the review comments from Tobias, but after discussion with Tobias and Thomas we've decided to skip the nice-to-h

[PATCH v3 3/6] openmp: Add -foffload-memory

Add a new option. It's inactive until I add some follow-up patches. gcc/ChangeLog: * common.opt: Add -foffload-memory and its enum values. * coretypes.h (enum offload_memory): New. * doc/invoke.texi: Document -foffload-memory. --- gcc/common.opt | 16 ++

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