Oh. I just confirmed. V1SI make perfect sens since we never apply partial vectorization for VLSmode.
Drop this patch and going to refactor reduction pattern to fix this issue. Thanks. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-12-11 17:11 To: juzhe.zh...@rivai.ai; gcc-patches CC: rdapp.gcc; richard.sandiford Subject: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS > Yes. This is the last chance to walk around it here but we will end up with > more patterns. > since reduction dest operand always LMUL = 1 mode. > > So, when -march=rv64gcv, the dest mode should be V4SI, if > -march=rv64gcv_zvl256b, the dest mode should be V8SI. > ...etc. Different TARGET_MIN_VLEN, different M1 mode. It's going to be a big > change in RISC-V backend. Hmm I haven't really thought this through yet (nor checked the spec in detail) but isn't the result always a 1-element thing? I.e. a V1SI regardless of the input vlen? That would also mean various changes of course. Regards Robin
