Re: [PATCH] RISC-V: Fix the illegal operands for the XTheadMemidx extension.

Thanks, pushed :) On Thu, Nov 9, 2023 at 3:40 PM Jin Ma wrote: > > The pattern "*extend2_bitmanip" and > "*zero_extendhi2_bitmanip" in bitmanip.md are similar > to the pattern "*th_memidx_bb_extendqi2" and > "*th_memidx_bb_zero_extendhi2" in thead.md, which will > cause the wrong instruction to b

Re: [PATCH] minimal support for xtheadv

On Thu, Nov 9, 2023 at 8:39 AM Kito Cheng wrote: > > Hi Yi Xuan: > > This patch is trivial, and generally LGTM, but I would require putting > the spec into https://github.com/riscv-non-isa/riscv-toolchain-conventions > before merging this, also don't forget include "RISC-V:" in the title, > it wou

Re: [PATCH] RISC-V: Fix the illegal operands for the XTheadMemidx extension.

On Thu, Nov 9, 2023 at 8:40 AM Jin Ma wrote: > > The pattern "*extend2_bitmanip" and > "*zero_extendhi2_bitmanip" in bitmanip.md are similar > to the pattern "*th_memidx_bb_extendqi2" and > "*th_memidx_bb_zero_extendhi2" in thead.md, which will > cause the wrong instruction to be generated and rep

Re: [PATCH][_Hashtable] Use RAII to restore Rehash state

On Thu, 26 Oct 2023 at 21:52, François Dumont wrote: > > > On 26/10/2023 12:43, Jonathan Wakely wrote: > > On 26/10/23 07:18 +0200, François Dumont wrote: > >> libstdc++: [_Hashtable] Use RAII type to manage rehash functor state > >> > >> Replace usage of __try/__catch with a RAII type to

Re: [PATCH] libsupc++: try cxa_thread_atexit_impl at runtime

On Thu, 9 Nov 2023 at 01:56, Alexandre Oliva wrote: > > > g++.dg/tls/thread_local-order2.C fails when the toolchain is built for > a platform that lacks __cxa_thread_atexit_impl, even if the program is > built and run using that toolchain on a (later) platform that offers > __cxa_thread_atexit_imp

[PATCH] Fix wrong code due to vec_merge + pcmp to blendvb splitter.

Boostrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready push to trunk. Will test and backport to GCC13/GCC12 release branch. gcc/ChangeLog: PR target/112443 * config/i386/sse.md (*avx2_pcmp3_4): Fix swap condition from LT to GE since there's not in the pattern.

[PATCH 1/3] s390: Recognize further vpdi and vmr{l,h} pattern

Deal with cases where vpdi and vmr{l,h} are still applicable if the operands of those instructions are swapped. For example, currently for V2DI foo (V2DI x) { return (V2DI) {x[1], x[0]}; } the assembler sequence vlgvg %r1,%v24,1 vzero %v0 vlvgg %v0,%r1,0 vmrhg %v24,%v0,%v24 is emitte

[PATCH 3/3] s390: Revise vector reverse elements

Replace UNSPEC_VEC_ELTSWAP with a vec_select implementation. Furthermore, for a vector reverse elements operation between registers of mode V8HI perform three rotates instead of a vperm operation since the latter involves loading the permutation vector from the literal pool. Prior z15, instead of

[PATCH] s390: Reduce number of patterns where the condition is false anyway

For patterns which make use of two modes, do not build the cross product and then exclude illegal combinations via conditions but rather do not create those in the first place. Here we are following the idea of the attribute TOINTVEC/tointvec and introduce TOINT/toint. Bootstrapped and regtested

Re: [PATCH 1/3] s390: Recognize further vpdi and vmr{l,h} pattern

On 11/9/23 09:22, Stefan Schulze Frielinghaus wrote: > Deal with cases where vpdi and vmr{l,h} are still applicable if the > operands of those instructions are swapped. For example, currently for > > V2DI foo (V2DI x) > { > return (V2DI) {x[1], x[0]}; > } > > the assembler sequence > > vlgvg

[PATCH 2/3] s390: Add expand_perm_reverse_elements

Replace expand_perm_with_rot, expand_perm_with_vster, and expand_perm_with_vstbrq with a general implementation expand_perm_reverse_elements. Bootstrapped and regtested on s390. Ok for mainline? gcc/ChangeLog: * config/s390/s390.cc (expand_perm_with_rot): Remove. (expand_perm_re

Re: [PATCH 3/3] s390: Revise vector reverse elements

On 11/9/23 09:22, Stefan Schulze Frielinghaus wrote: > Replace UNSPEC_VEC_ELTSWAP with a vec_select implementation. > > Furthermore, for a vector reverse elements operation between registers > of mode V8HI perform three rotates instead of a vperm operation since > the latter involves loading the p

Re: [PATCH 2/3] s390: Add expand_perm_reverse_elements

On 11/9/23 09:22, Stefan Schulze Frielinghaus wrote: > Replace expand_perm_with_rot, expand_perm_with_vster, and > expand_perm_with_vstbrq with a general implementation > expand_perm_reverse_elements. > > Bootstrapped and regtested on s390. Ok for mainline? > > gcc/ChangeLog: > > * config

Re: [PATCH] s390: Reduce number of patterns where the condition is false anyway

On 11/9/23 09:24, Stefan Schulze Frielinghaus wrote: > For patterns which make use of two modes, do not build the cross product > and then exclude illegal combinations via conditions but rather do not > create those in the first place. Here we are following the idea of the > attribute TOINTVEC/toi

Re: [PATCH] minimal support for xtheadv

Hi Kito and Christoph, XYenChi (oriachi...@gmail.com) is my e-mail address too. I didn't notice the git email config have changed, very sorry about that. We want to support other operate system project from our team, so port the XTheadV. If T-Head and VRULL have made great progress, it's pleasure

RE: [PATCH] tree-optimization/111950 - vectorizer loop copying

> guard_bb = LOOP_VINFO_IV_EXIT (loop_vinfo)->dest; > edge epilog_e = LOOP_VINFO_EPILOGUE_IV_EXIT (loop_vinfo); > - guard_to = split_edge (epilog_e); > + guard_to = epilog_e->dest; > guard_e = slpeel_add_loop_guard (guard_bb, guard_cond, guard_to, >

Re: PING^1 [PATCH v3] sched: Change no_real_insns_p to no_real_nondebug_insns_p [PR108273]

Hi Kewen, Below are my comments. I don't want to override Alexander's review, and if the patch looks good to him, it's fine to ignore my concerns. My main concern is that this adds a new entity -- forceful skipping of DEBUG_INSN-only basic blocks -- to the scheduler for a somewhat minor change

Re: [PATCH] RISC-V: Removed unnecessary sign-extend for vsetvl

Should we need a zero-ext version as well? On Wed, Nov 8, 2023 at 9:39 PM Lehua Ding wrote: > > Committed, thanks Juzhe. > > On 2023/11/8 21:29, juzhe.zhong wrote: > > lgtm > > Replied Message > > From Lehua Ding > > Date 11/08/2023 21:27 > > Togcc-pat

RE: [PATCH] tree-optimization/111950 - vectorizer loop copying

On Thu, 9 Nov 2023, Tamar Christina wrote: > > guard_bb = LOOP_VINFO_IV_EXIT (loop_vinfo)->dest; > > edge epilog_e = LOOP_VINFO_EPILOGUE_IV_EXIT (loop_vinfo); > > - guard_to = split_edge (epilog_e); > > + guard_to = epilog_e->dest; > > guard_e = slpeel_add_loop_guard (gua

Re: [PATCH v2] i386 PIE: accept @GOTOFF in load/store multi base address

On Wed, Nov 8, 2023 at 5:37 PM Alexandre Oliva wrote: > > Ping? > https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598872.html > > Looking at the code generated for sse2-{load,store}-multi.c with PIE, > I realized we could use UNSPEC_GOTOFF as a base address, and that this > would enable the te

Re: [PATCH] i386: Fix C99 compatibility issues in the x86-64 AVX ABI test suite

* Jakub Jelinek: > On Wed, Nov 08, 2023 at 03:55:17PM +0100, Florian Weimer wrote: >> * gcc.target/x86_64/abi/avx/avx-check.h (main): Call >> __builtin_printf instead of printf. >> * gcc.target/x86_64/abi/avx/test_passing_m256.c >> (fun_check_passing_m256_8_values): Add missing

Re: [PATCH] i386: Fix C99 compatibility issues in the x86-64 AVX ABI test suite

On Thu, Nov 09, 2023 at 10:33:40AM +0100, Florian Weimer wrote: > * Jakub Jelinek: > > > On Wed, Nov 08, 2023 at 03:55:17PM +0100, Florian Weimer wrote: > >>* gcc.target/x86_64/abi/avx/avx-check.h (main): Call > >>__builtin_printf instead of printf. > >>* gcc.target/x86_64/abi/avx/test

Re: [PATCH] RISC-V: Removed unnecessary sign-extend for vsetvl

Hi Kito, On 2023/11/9 17:21, Kito Cheng wrote: Should we need a zero-ext version as well? It's not needed at the moment, since the sign_extend is currently used for both int32_t and uint32_t. I can't find a case where zero_extend would occur. -- Best, Lehua (RiVAI) lehua.d...@rivai.ai

[PATCH] c++/modules: fix virtual destructors [PR103499]

I'm not sure if this is just papering over a general issue of clones not being exported/imported, or if this is just an exception to the general case of clones being able to be freely regenerated with no other issues. Alternatively, would it be better to override the DECL_VINDEX of the original de

[PATCH] Add a REG_P check for inc and dec for Arm MVE

Hey, This patch tightens mve_vector_mem_operand to reject non-register operands inside {PRE,POST}_{INC,DEC} addresses by introducing a REG_P check. This patch fixes this ICE:https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337 Okay for trunk? I don't have trunk access so could someone please co

RE: [PATCH] tree-optimization/111950 - vectorizer loop copying

> -Original Message- > From: Richard Biener > Sent: Thursday, November 9, 2023 9:24 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org > Subject: RE: [PATCH] tree-optimization/111950 - vectorizer loop copying > > On Thu, 9 Nov 2023, Tamar Christina wrote: > > > > guard_bb = LOOP

[committed] MIPS: Use -mnan value for -mabs if not specified

On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008. Let's use this behaivor by default in GCC, aka gcc -mnan=2008 -c fabs.c will imply `-mabs=2008`. And of course, `gcc -mnan=2008 -mabs=legacy` can continue workable like previous. gcc/ChangeLog * config/mips/m

[committed] MAINTAINERS: Update my email address

ChangeLog: * MAINTAINERS: Update my email address. --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index a182c106bed..30cb530a3b1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -91,7 +91,7 @@ m68k port Andreas Schwab

Re: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154]

Tamar Christina writes: >> >> > + "&& TARGET_SVE && rtx_equal_p (operands[0], operands[1]) >> >> > + && satisfies_constraint_ (operands[2]) >> >> > + && FP_REGNUM_P (REGNO (operands[0]))" >> >> > + [(const_int 0)] >> >> > + { >> >> > +rtx op1 = lowpart_subreg (mode, operands[1], >> mode

[PATCH] tree-optimization/112444 - avoid bougs PHI value-numbering

With .DEFERRED_INIT ssa_undefined_value_p () can return true for values we did not visit (because they proved unreachable) but are not .VN_TOP. Avoid using those as value which, because they are not visited, are assumed to be defined outside of the region. Bootstrapped and tested on x86_64-unknow

[PATCH 0/1] RISC-V: Support CORE-V XCVBITMAIP extension

This patch series presents the comprehensive implementation of the BITMANIP extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invalu

[PATCH 1/1] RISC-V: Add support for XCVbitmanip extension in CV32E40P

Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin gcc/ChangeLog: * common/config/

Re: [PATCH] Fix PR ada/111813 (Inconsistent limit in Ada.Calendar.Formatting)

On 24 Oct 2023, at 10:49, Arnaud Charlet wrote: > > This change is OK, thank you. Can it be committed, then, please? >> The description of the second Value function (returning Duration) (ARM >> 9.6.1(87) >> doesn't place any limitation on the Elapsed_Time parameter's value, beyond >> "Constr

[0/4] aarch64: Fix intrinsic availability [PR112108]

This series of patches fixes issues with some intrinsics being incorrectly gated by global target options, instead of just using function-specific target options. These issues have been present since the +tme, +memtag and +ls64 intrinsics were introduced. Bootstrapped and regression tested on aar

Re: [PATCH] Fix PR ada/111813 (Inconsistent limit in Ada.Calendar.Formatting)

Marc, can you please take care of it when you get a chance? On Thu, Nov 09, 2023 at 11:22:21AM +, Simon Wright wrote: > On 24 Oct 2023, at 10:49, Arnaud Charlet wrote: > > > > This change is OK, thank you. > > Can it be committed, then, please? > > >> The description of the second Value fu

[1/4] aarch64: Refactor check_required_extensions

Move SVE extension checking functionality to aarch64-builtins.cc, so that it can be shared by non-SVE intrinsics. gcc/ChangeLog: * config/aarch64/aarch64-sve-builtins.cc (check_builtin_call) (expand_builtin): Update calls to the below. (report_missing_extension, check_requ

[2/4] aarch64: Fix tme intrinsic availability

The availability of tme intrinsics was previously gated at both initialisation time (using global target options) and usage time (accounting for function-specific target options). This patch removes the check at initialisation time, and also moves the intrinsics out of the header file to allow for

[3/4] aarch64: Fix memtag intrinsic availability

The availability of memtag intrinsics and data types were determined solely by the globally specified architecture features, which did not reflect any changes specified in target pragmas or attributes. This patch removes the initialisation-time guards for the intrinsics, and replaces them with che

[4/4] aarch64: Fix ls64 intrinsic availability

The availability of ls64 intrinsics and data types were determined solely by the globally specified architecture features, which did not reflect any changes specified in target pragmas or attributes. This patch removes the initialisation-time guards for the intrinsics, and replaces them with check

aarch64: Add cpu feature detection to libgcc

This is added to enable function multiversioning, but can also be used directly. The interface is chosen to match that used in LLVM's compiler-rt, to facilitate cross-compiler compatibility. The content of the patch is derived almost entirely from Pavel's prior contributions to compiler-rt/lib/bu

Re: [PATCH] Middle-end: Fix bug of induction variable vectorization for RVV

Bootstrap + regression on X86 passed. Ok for trunk ? juzhe.zh...@rivai.ai From: Juzhe-Zhong Date: 2023-11-08 18:53 To: gcc-patches CC: richard.sandiford; rguenther; kito.cheng; kito.cheng; Juzhe-Zhong Subject: [PATCH] Middle-end: Fix bug of induction variable vectorization for RVV PR: https:/

[PATCH] tree-optimization/112450 - avoid AVX512 style masking for BImode masks

The following avoids running into the AVX512 style masking code for RVV which would theoretically be able to handle it if I were not relying on integer mode maskness in vect_get_loop_mask. While that's easy to fix (patch in PR), the preference is to not have AVX512 style masking for RVV, thus the

Re: [1/4] aarch64: Refactor check_required_extensions

Andrew Carlotti writes: > Move SVE extension checking functionality to aarch64-builtins.cc, so > that it can be shared by non-SVE intrinsics. > > gcc/ChangeLog: > > * config/aarch64/aarch64-sve-builtins.cc (check_builtin_call) > (expand_builtin): Update calls to the below. > (rep

Re: [PATCH, expand] Call misaligned memory reference in expand_builtin_return [PR112417]

On Thu, Nov 9, 2023 at 6:43 AM HAO CHEN GUI wrote: > > Hi, > This patch modifies expand_builtin_return and make it call > expand_misaligned_mem_ref to load unaligned memory. The memory reference > pointed by void* pointer might be unaligned, so expanding it with > unaligned move optabs is safe.

RE: [PATCH] tree-optimization/111950 - vectorizer loop copying

On Thu, 9 Nov 2023, Tamar Christina wrote: > > -Original Message- > > From: Richard Biener > > Sent: Thursday, November 9, 2023 9:24 AM > > To: Tamar Christina > > Cc: gcc-patches@gcc.gnu.org > > Subject: RE: [PATCH] tree-optimization/111950 - vectorizer loop copying > > > > On Thu, 9 N

[PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension

This patch series presents the comprehensive implementation of the SIMD extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable

[Committed] RISC-V: Add PR112450 test to avoid regression

ICE has been fixed by Richard:https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112450. Add test to avoid future regression. Committed. PR target/112450 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112450.c: New test. --- .../gcc.target/riscv/rvv/autovec/pr112450.c

Re: [PATCH] Middle-end: Fix bug of induction variable vectorization for RVV

On Wed, Nov 8, 2023 at 11:53 AM Juzhe-Zhong wrote: > > PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112438 > > SELECT_VL result is not necessary always VF in non-final iteration. > > Current GIMPLE IR is wrong: > > # vect_vec_iv_.21_25 = PHI <_24(4), { 0, 1, 2, ... }(3)> > ... > _24 = vect_vec

Re: [PATCH] openmp: Add support for the 'indirect' clause in C/C++

Hi Kwok! Nice work! A few comments: On 2023-11-03T19:53:28+, Kwok Cheung Yeung wrote: > Subject: [PATCH] openmp: Add support for the 'indirect' clause in C/C++ > > This adds support for the 'indirect' clause in the 'declare target' > directive. Functions declared as indirect may be called

RE: [PATCH v1] RISC-V: Refine frm emit after bb end in succ edges

Committed, thanks Juzhe. Pan From: juzhe.zh...@rivai.ai Sent: Thursday, November 9, 2023 2:54 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Refine frm emit after bb end in succ edges OK。 juzhe.zh...@

Re: Re: [PATCH] Middle-end: Fix bug of induction variable vectorization for RVV

Hi, Richard. >> I think it would be better to split out building a tree from VF from both >> arms and avoid using 'vf' when LOOP_VINFO_USING_SELECT_VL_P. Ok. >> Btw, you are not patching the SLP path here which I believe has the same >> problem but is currently exempt from non-constant VF at lea

[PATCH 0/1] RISC-V: Support CORE-V XCVMEM extension

This patch series presents the comprehensive implementation of the MEM extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable

[PATCH 1/1] RISC-V: Add support for XCVmem extension in CV32E40P

XCVmem adds more loads and stores. To prevent non-XCVmem loads and stores from generating illegal XCVmem specific operands, constraint 'm' was redefined. 'm' does not accept POST_MODIFY or reg + reg addresses. Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Re: [PATCH] tree-ssa-loop-ivopts : Add live analysis in regs used in decision making

On Wed, Nov 8, 2023 at 4:00 PM Ajit Agarwal wrote: > > tree-ssa-loop-ivopts : Add live analysis in regs used in decision making. > > Add live anaysis in regs used calculation in decision making of > selecting ivopts candidates. > > 2023-11-08 Ajit Kumar Agarwal > > gcc/ChangeLog: > > *

Re: [PATCH 4/4] Refactor x86 decl based scatter vectorization, prepare SLP

On Wed, 8 Nov 2023, Richard Biener wrote: > The following refactors the x86 decl based scatter vectorization > similar to what I did to the gather path. This prepares scatters > for SLP as well, mainly single-lane since there are multiple > missing bits to support multi-lane scatters. > > Tested

Re: [PATCH] Do not prepend target triple to -fuse-ld=lld,mold.

On Thu, 9 Nov 2023, Tatsuyuki Ishi wrote: > > On Nov 7, 2023, at 23:37, Richard Biener wrote: > > > > On Tue, 7 Nov 2023, Tatsuyuki Ishi wrote: > > > >>> On Oct 16, 2023, at 18:16, Richard Biener wrote: > >>> > >>> On Mon, 16 Oct 2023, Tatsuyuki Ishi wrote: > >>> > > > > On O

Re: [PATCH] Fix PR ada/111813 (Inconsistent limit in Ada.Calendar.Formatting)

Arnaud Charlet writes: > Marc, can you please take care of it when you get a chance? I'll push the change as soon as the tests are finished. Marc

Re: [PATCH] Fix PR ada/111813 (Inconsistent limit in Ada.Calendar.Formatting)

Marc Poulhiès writes: > Arnaud Charlet writes: > >> Marc, can you please take care of it when you get a chance? > > I'll push the change as soon as the tests are finished. Pushed as r14-5282. Marc

[PATCH 0/5] aarch64: Add ACLE intrinsics codegen support for lrcpc3 instructions

Given the introduction of the third set of Release Consistency processor consistent (RCpc) memory model-compliant instructions in the form of FEAT_LRCPC3 as an optional extension from Armv8.2-a onward, this patch series adds the RCPC3 ACLE Neon intrinsics, thus enabling the use of the architectural

[PATCH 2/5] aarch64: rcpc3: Add relevant iterators to handle Neon intrinsics

The LDAP1 and STL1 Neon ACLE intrinsics, operating on 64-bit data values, operate on single-lane (Vt.1D) or twin-lane (Vt.2D) SIMD register configurations, either in the DI or DF modes. This leads to the need for a mode iterator accounting for the V1DI, V1DF, V2DI and V2DF modes. This patch there

[PATCH 3/5] aarch64: rcpc3: Add Neon ACLE intrinsics

Register the target specific builtins in `aarch64-simd-builtins.def' and implement their associated backend patterns in `aarch64-simd.md'. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (vec_ldap1_lane): New. (vec_stl1_lane): Likewise. * config/aarch64/a

[PATCH 4/5] aarch64: rcpc3: add Neon ACLE wrapper functions to `arm_neon.h'

Create the necessary mappings from the ACLE-defined Neon intrinsics names[1] to the internal builtin function names. [1] https://arm-software.github.io/acle/neon_intrinsics/advsimd.html gcc/ChangeLog: * gcc/config/aarch64/arm_neon.h (vldap1_lane_u64): New. (vldap1q_lane_u64): Lik

[PATCH 1/5] aarch64: rcpc3: Add +rcpc3 extension

Given the optional LRCPC3 target support for Armv8.2-a cores onwards, the +rcpc3 arch feature modifier is added to GCC's command-line options. gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def (rcpc3): New. * config/aarch64/aarch64.h (AARCH64_ISA_RCPC3): Likewise.

[PATCH 5/5] aarch64: rcpc3: Add intrinsics tests

Add unit test to ensure that added intrinsics compile to the correct `LDAP1 {Vt.D}[lane],[Xn]' and `STL1 {Vt.d}[lane],[Xn]' instructions. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/rcpc3.c: New. --- gcc/testsuite/gcc.target/aarch64/acle/rcpc3.c | 47 +++ 1 file ch

[PATCH v1] Internal-fn: Add FLOATN support for l/ll round and rint [PR/112432]

From: Pan Li The defined DEF_EXT_LIB_FLOATN_NX_BUILTINS functions should also have DEF_INTERNAL_FLT_FLOATN_FN instead of DEF_INTERNAL_FLT_FN for the FLOATN support. According to the glibc API and gcc builtin, we have below table for the FLOATN is supported or not. +-+---+

Re: [committed] RISC-V: Fix INSN costing and more zicond tests

On Fri, 29 Sep 2023, Jeff Law wrote: > So this ends up looking a lot like the bits that I had to revert several weeks > ago :-) > > The core issue we have is given an INSN the generic code will cost the SET_SRC > and SET_DEST and sum them. But that's far from ideal on a RISC target. > > For a r

Re: Re: [PATCH] Middle-end: Fix bug of induction variable vectorization for RVV

Hi, Richard. >> I think it would be better to split out building a tree from VF from both >> arms and avoid using 'vf' when LOOP_VINFO_USING_SELECT_VL_P. I am trying to split out building tree from both arms as you suggested.. Could you take a look the following codes ? diff --git a/gcc/tree-vec

[PATCH] Add type-generic clz/ctz/clrsb/ffs/parity/popcount builtins [PR111309]

Hi! The following patch adds 6 new type-generic builtins, __builtin_clzg __builtin_ctzg __builtin_clrsbg __builtin_ffsg __builtin_parityg __builtin_popcountg The g at the end stands for generic because the unsuffixed variant of the builtins already have unsigned int or int arguments. The main rea

Re: [committed] RISC-V: Fix INSN costing and more zicond tests

On 11/9/23 07:33, Maciej W. Rozycki wrote: On Fri, 29 Sep 2023, Jeff Law wrote: So this ends up looking a lot like the bits that I had to revert several weeks ago :-) The core issue we have is given an INSN the generic code will cost the SET_SRC and SET_DEST and sum them. But that's far fr

Re: [PATCH v1] Internal-fn: Add FLOATN support for l/ll round and rint [PR/112432]

> Am 09.11.2023 um 15:34 schrieb pan2...@intel.com: > > From: Pan Li > > The defined DEF_EXT_LIB_FLOATN_NX_BUILTINS functions should also > have DEF_INTERNAL_FLT_FLOATN_FN instead of DEF_INTERNAL_FLT_FN for > the FLOATN support. According to the glibc API and gcc builtin, we > have below tab

[PATCH] RISC-V/testsuite: Fix zvfh tests.

Hi, this fixes some zvfh test oversights as well as adds zfh to the target requirements. It's not strictly necessary to have zfh but it greatly simplifies test handling when we can just calculate the reference value instead of working around it. Regards Robin gcc/testsuite/ChangeLog:

Re: [committed] RISC-V: Fix INSN costing and more zicond tests

On 11/9/23 07:33, Maciej W. Rozycki wrote: On Fri, 29 Sep 2023, Jeff Law wrote: So this ends up looking a lot like the bits that I had to revert several weeks ago :-) The core issue we have is given an INSN the generic code will cost the SET_SRC and SET_DEST and sum them. But that's far fr

Re: RFC (V2) the proposal to resolve the missing dependency issue for counted_by attribute

Is it reasonable to add one option to disable the “counted_by” attribute? (then no insertion of the new .ACCESS_WITH_SIZE into IL). The major reason is: some users might want to ignore all the “counted_by” attribute added in the source code, We need to provide them a way to disable this feature

Re: RFC (V2) the proposal to resolve the missing dependency issue for counted_by attribute

On Thu, Nov 09, 2023 at 03:49:49PM +, Qing Zhao wrote: > Is it reasonable to add one option to disable the “counted_by” attribute? > (then no insertion of the new .ACCESS_WITH_SIZE into IL). > > The major reason is: some users might want to ignore all the “counted_by” > attribute added in t

Re: [PATCH] openmp: Add support for the 'indirect' clause in C/C++

Hi Thomas, hi Kwok, (Skipping some valid (review) comments and bare remarks.) On 09.11.23 13:24, Thomas Schwinge wrote: Also, assuming that the order of appearance of 'IND_FUNC_MAP' does matter as it does for 'FUNC_MAP', ... https://github.com/MentorEmbedded/nvptx-tools/pull/29 ... It should

[PATCH] libstdc++: Fix forwarding in __take/drop_of_repeat_view [PR112453]

Tested on x86_64-pc-linux-gnu, does this look OK for trunk/13? (The && overloads are also missing on earlier branches, but I don't think it makes a difference there since all uses of that operator* are on lvalues before this fix.) -- >8 -- We need to respect the value category of the repeat_view

Re: [PATCH] minimal support for xtheadv

On 11/9/23 01:38, Yixuan Chen wrote: Hi Kito and Christoph, XYenChi (oriachi...@gmail.com ) is my e-mail address too. I didn't notice the git email config have changed, very sorry about that. We want to support other operate system project from our team, so po

[PATCH v3] aarch64: SVE/NEON Bridging intrinsics

ACLE has added intrinsics to bridge between SVE and Neon. The NEON_SVE Bridge adds intrinsics that allow conversions between NEON and SVE vectors. This patch adds support to GCC for the following 3 intrinsics: svset_neonq, svget_neonq and svdup_neonq gcc/ChangeLog: * config.gcc: Adds ne

Re: [PATCH v2] DSE: Allow vector type for get_stored_val when read < store

On 11/8/23 23:08, pan2...@intel.com wrote: From: Pan Li Update in v2: * Move vector type support to get_stored_val. Original log: This patch would like to allow the vector mode in the get_stored_val in the DSE. It is valid for the read rtx if and only if the read bitsize is less than the s

Re: [PATCH] minimal support for xtheadv

Give a few more thought behind my first LGTM: I am OK *IF* binutils bits accepted since it's just kind of bypassing the -march to bintuils to enable those instructions for assembly code. However the situation seems is little more complicated than my expect at beginning...:P Anyway, I still think

RE: [PATCH] tree-optimization/111950 - vectorizer loop copying

> -Original Message- > From: Richard Biener > Sent: Thursday, November 9, 2023 11:54 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org > Subject: RE: [PATCH] tree-optimization/111950 - vectorizer loop copying > > On Thu, 9 Nov 2023, Tamar Christina wrote: > > > > -Original Mess

Re: [PATCH] RISC-V: VECT: Remember to assert any_known_not_updated_vssa

On 11/6/23 06:01, Maxim Blinov wrote: From: Maxim Blinov This patch is based on and intended for the vendors/riscv/gcc-13-with-riscv-opts branch - please apply if looks OK. Fixes the following ICEs that I'm seeing: FAIL: gcc.dg/vect/O3-pr49087.c (internal compiler error: in vect_transfor

Re: RFC (V2) the proposal to resolve the missing dependency issue for counted_by attribute

> On Thu, Nov 09, 2023 at 03:49:49PM +, Qing Zhao wrote: >> Is it reasonable to add one option to disable the “counted_by” attribute? >> (then no insertion of the new .ACCESS_WITH_SIZE into IL). >> >> The major reason is: some users might want to ignore all the “counted_by” >> attribute a

Re: [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

On 11/8/23 04:09, Mary Bennett wrote: +;; XCVELW builtins +(define_insn "riscv_cv_elw_elw_si" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec_volatile [(mem:SI (match_operand:SI 1 "address_operand" "p"))] + UNSPECV_CV_ELW))] + + "TARGET_XCVELW && !TARGET_64BIT" + "cv.elw\t

Re: RFC (V2) the proposal to resolve the missing dependency issue for counted_by attribute

> On Nov 9, 2023, at 11:50 AM, Jose Marchesi wrote: > >> >> On Thu, Nov 09, 2023 at 03:49:49PM +, Qing Zhao wrote: >>> Is it reasonable to add one option to disable the “counted_by” attribute? >>> (then no insertion of the new .ACCESS_WITH_SIZE into IL). >>> >>> The major reason is: som

Re: PING^1 [PATCH v3] sched: Change no_real_insns_p to no_real_nondebug_insns_p [PR108273]

On Thu, 9 Nov 2023, Maxim Kuvyrkov wrote: > Hi Kewen, > > Below are my comments. I don't want to override Alexander's review, and if > the patch looks good to him, it's fine to ignore my concerns. > > My main concern is that this adds a new entity -- forceful skipping of > DEBUG_INSN-only bas

RE: [PATCH v4] [tree-optimization/110279] Consider FMA in get_reassociation_width

> -Original Message- > From: Richard Biener > Sent: Tuesday, October 31, 2023 9:48 PM > To: Di Zhao OS > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH v4] [tree-optimization/110279] Consider FMA in > get_reassociation_width > > On Sun, Oct 8, 2023 at 6:40 PM Di Zhao OS > wrote: > >

Re: [AVR PATCH] Optimize (X>>C)&1 for C in [1,4,8,16,24] in *insv.any_shift..

Am 02.11.23 um 12:50 schrieb Roger Sayle: This patch optimizes a few special cases in avr.md's *insv.any_shift. instruction. This template handles tests for a single bit, where the result has only a (different) single bit set in the result. Usually (currently) this always requires a three-in

[pushed] [IRA]: Fixing conflict calculation from region landing pads.

This is one more patch for https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110215 The patch was successfully tested and bootstrapped on x86-64, aarch64, ppc64le. commit df14f1c0582cd6742a37abf3a97f4c4bf0caf864 Author: Vladimir N. Makarov Date: Thu Nov 9 08:51:15 2023 -0500 [IRA]: Fixing

Re: [PATCH v3 1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609]

On 11/4/23 02:40, waffl3x wrote: I'm unfortunately going down a rabbit hole again. --function.h:608 ``` /* If pointers to member functions use the least significant bit to indicate whether a function is virtual, ensure a pointer to this function will have that bit clear. */ #define MINI

[committed] i386: Improve stack protector patterns and peephole2s even more

Improve stack protector patterns and peephole2s even more: a. Use unrelated register clears with integer mode size <= word mode size to clear stack protector scratch register. b. Use unrelated register initializations in front of stack protector sequence to clear stack protector scratch reg

[PATCH 1/2] libstdc++: declare std::allocator in !HOSTED as an extension

This allows us to add features to freestanding which allow specifying non-default allocators (generators, collections, ...) without having to modify them. libstdc++-v3/ChangeLog: * include/bits/memoryfwd.h: Remove HOSTED check around allocator and its specializations. --- Evening,

[PATCH 2/2] libstdc++: mark 20_util/scoped_allocator/noexcept.cc R-E-T hosted

libstdc++-v3/ChangeLog: * testsuite/20_util/scoped_allocator/noexcept.cc: Mark as requiring hosted. --- libstdc++-v3/testsuite/20_util/scoped_allocator/noexcept.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/libstdc++-v3/testsuite/20_util/scoped_allocator/noexcept.cc b/li

Re: [PATCH] libstdc++: Fix forwarding in __take/drop_of_repeat_view [PR112453]

On Thu, 9 Nov 2023 at 16:01, Patrick Palka wrote: > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk/13? (The > && overloads are also missing on earlier branches, but I don't think > it makes a difference there since all uses of that operator* are on > lvalues before this fix.) OK fo

Re: [PATCH 2/2] libstdc++: mark 20_util/scoped_allocator/noexcept.cc R-E-T hosted

On Thu, 9 Nov 2023 at 19:32, Arsen Arsenović wrote: > > libstdc++-v3/ChangeLog: > > * testsuite/20_util/scoped_allocator/noexcept.cc: Mark as > requiring hosted. OK for trunk, thanks. The test has been backported, but we don't have the hosted et there so this isn't needed on the

[PATCH] c++: fix parsing with auto(x) [PR112410]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- Here we are wrongly parsing int y(auto(42)); which uses the C++23 cast-to-prvalue feature, and initializes y to 42. However, we were treating the auto as an implicit template parameter. Fixing the auto{42} case is easy, but

Re: [PATCH] testsuite/vect: Make check more accurate.

Hi! On 2023-11-07T09:22:16+0100, Robin Dapp wrote: > similar to before this modifies a check so we do only match a > vectorization attempt if it succeeded. On riscv we potentially try > several modes of which some may fail. > > I tested on riscv, aarch64 and x86 but on the cfarm machines > there

[PATCH] Add missing declaration of get_restrict in C++ interface

Hi, This patch adds the `get_restrict` method declaration for the C++ interface as it was forgotten. Thanks in advance for the review. From e819fd01cd3e79bfab28a77f4ce78f34156e7a83 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Thu, 9 Nov 2023 17:53:08 +0100 Subject: [PATCH] Add missing de

Re: [PATCH 0/7] ira/lra: Support subreg coalesce

On 11/7/23 22:47, Lehua Ding wrote: Lehua Ding (7): ira: Refactor the handling of register conflicts to make it more general ira: Add live_subreg problem and apply to ira pass ira: Support subreg live range track ira: Support subreg copy ira: Add all nregs >= 2 pseudos to t

Re: [PATCH] Add missing declaration of get_restrict in C++ interface

On Thu, 2023-11-09 at 21:03 +0100, Guillaume Gomez wrote: > Hi, > > This patch adds the `get_restrict` method declaration for > the C++ interface as it was forgotten. > > Thanks in advance for the review. Looking at my jit.sum results, it looks like the .cc files are indeed FAILing on initial co

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