There are two reasons for removing this macro definition:
1. The default in the assembler is to use the nop instruction for filling.
2. For assembly directives: .align [abs-expr[, abs-expr[, abs-expr]]]
The third expression it is the maximum number of bytes that should be
skipped by this alig
Pushed to r14-4584.
在 2023/10/11 下午5:59, Yang Yujie 写道:
gcc/ChangeLog:
* config.gcc: Add loongarch-driver.h to tm_files.
* config/loongarch/loongarch.h: Do not include loongarch-driver.h.
* config/loongarch/t-loongarch: Append loongarch-multilib.h to $(GTM_H)
ins
Pushed to r14-4585.
在 2023/9/28 下午6:05, Chenghui Pan 写道:
This is the update of:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631379.html
This version does not include changes for codes, but fixes the commit title
format and appends the missing PR info.
Chenghui Pan (2):
LoongArc
Hi!
The following testcase started FAILing recently after the
https://sourceware.org/git/?p=glibc.git;a=commit;h=64b1a44183a3094672ed304532bedb9acc707554
glibc change which marked vfscanf with nonnull (1) attribute.
While vfwscanf hasn't been marked similarly (strangely), the patch changes
that to
Richard Biener writes:
> On Tue, Aug 22, 2023 at 12:42 PM Szabolcs Nagy via Gcc-patches
> wrote:
>>
>> From: Richard Sandiford
>>
>> The prologue/epilogue pass allows the prologue sequence
>> to contain jumps. The sequence is then partitioned into
>> basic blocks using find_many_sub_basic_block
The following removes a misguided attempt to allow x + x in a reduction
path, also allowing x * x which isn't valid. x + x actually never
arrives this way but instead is canonicalized to 2 * x. This makes
reduction path handling consistent with how we handle the single-stmt
reduction case.
Boots
I was building a cross compiler to PowerPC on my x86_86 workstation with the
latest version of GCC on October 11th. I could not build the compiler on the
x86_64 system as it died in building libgcc. I looked into it, and I
discovered the compiler was recursing until it ran out of stack space. If
This patch improves code sinking pass to sink statements before call to reduce
register pressure.
Review comments are incorporated. Synced and modified with latest trunk sources.
For example :
void bar();
int j;
void foo(int a, int b, int c, int d, int e, int f)
{
int l;
l = a + b + c + d +e
On Wed, Oct 11, 2023 at 12:48:12AM +1100, Nathaniel Shead wrote:
> On Mon, Oct 09, 2023 at 04:46:46PM -0400, Jason Merrill wrote:
> > On 10/8/23 21:03, Nathaniel Shead wrote:
> > > Ping for
> > > https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631203.html
> > >
> > > + && (TREE_CODE (t
From: Pan Li
This patch would like to support the FP lround/lroundf auto vectorization.
* long lround (double) for rv64
* long lroundf (float) for rv32
Due to the limitation that only the same size of data type are allowed
in the vectorier, the standard name lroundmn2 only act on DF => DI for
r
The support to elide calls to allocation functions in DCE runs into
the issue that when implementations are discovered noreturn we end
up DCEing the calls anyway, leaving blocks without termination and
without outgoing edges which is both invalid IL and wrong-code when
as in the example the noretur
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-12 16:59
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP lround/lroundf auto vectorization
From: Pan Li
This patch would like to support the FP lround/lroundf auto vectorization.
Hi,
The description of the REG_NOALIAS note in reg-notes.def isn't quite
right. It describes it as being attached to call insns, but it is
instead attached to a move insn receiving the return value from a call.
This can be seen by looking at the code in calls.cc:expand_call which
attaches the not
On Thu, 12 Oct 2023, ??? wrote:
> Thanks Richi point it out.
>
> I found this patch can't make conditional gather load succeed on SLP.
>
> I am considering change MASK_LEN_GATHER_LOAD in pattern recognization:
>
> If no condition mask, in tree-vect-patterns.cc, I build MASK_LEN_GATHER_LOAD
>
I tree-vect-slp.cc:
vect_get_and_check_slp_defs
711:
tree type = TREE_TYPE (oprnd);
dt = dts[i];
if ((dt == vect_constant_def
|| dt == vect_external_def)
&& !GET_MODE_SIZE (vinfo->vector_mode).is_constant ()
&& (TREE_CODE (t
On Wed, 11 Oct 2023 at 16:57, Prathamesh Kulkarni
wrote:
>
> On Wed, 11 Oct 2023 at 16:42, Prathamesh Kulkarni
> wrote:
> >
> > On Mon, 9 Oct 2023 at 17:05, Richard Sandiford
> > wrote:
> > >
> > > Prathamesh Kulkarni writes:
> > > > Hi,
> > > > The attached patch attempts to fix PR111648.
> >
On Thu, 12 Oct 2023, juzhe.zh...@rivai.ai wrote:
> I tree-vect-slp.cc:
> vect_get_and_check_slp_defs
> 711:
>
> tree type = TREE_TYPE (oprnd);
> dt = dts[i];
> if ((dt == vect_constant_def
>|| dt == vect_external_def)
> && !GET_MODE_SIZ
gcc/ChangeLog:
* doc/extend.texi: Change subsubsection to subsection for
CORE-V built-ins.
---
gcc/doc/extend.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index ffe8532ad91..e8180945ab4 100644
--- a/gcc/doc/extend.texi
Hi, Richi.
I restrict as you said into vect_external_def.
Then this condition made SLP failed:
- if (mask_index >= 0
+ if (mask_index >= 0 && internal_fn_len_index (ifn) < 0
&& !vect_check_scalar_mask (vinfo, stmt_info, slp_node, mask_index,
Oh. I see.
Here make vect_constant_def failed to SLP:
tree-vect-slp.cc:
vect_build_slp_tree_2
line 2354:
if (oprnd_info->first_dt == vect_external_def
|| oprnd_info->first_dt == vect_constant_def)
{
slp_tree invnode = vect_create_new_slp_node (oprnd_info->ops);
"Richard Earnshaw (lists)" writes:
> On 09/10/2023 14:12, Victor Do Nascimento wrote:
>>
>>
>> On 10/7/23 12:53, Richard Sandiford wrote:
>>> Richard Earnshaw writes:
On 03/10/2023 16:18, Victor Do Nascimento wrote:
> In implementing the ACLE read/write system register builtins it was
The following handles byte-aligned, power-of-two and byte-multiple
sized BIT_FIELD_REF reads in SRA. In particular this should cover
BIT_FIELD_REFs created by optimize_bit_field_compare.
For gcc.dg/tree-ssa/ssa-dse-26.c we now SRA the BIT_FIELD_REF
appearing there leading to more DSE, fully elidi
Robin Dapp writes:
>> It wasn't very clear, sorry, but it was the last sentence I was asking
>> for clarification on, not the other bits. Why do we want to avoid
>> generating a COND_ADD when the operand is a vectorisable call?
>
> Ah, I see, apologies. Upon thinking about it a bit more (thanks)
This patch improves the documentation by completing the description of
the remaining so far undocumented OpenMP Memory-Management Routines
(except for the two function added in TR11, which are also unimplmeneted).
Current online version:
https://gcc.gnu.org/onlinedocs/libgomp/Memory-Management-Ro
Jakub Jelinek writes:
> @@ -2036,11 +2075,20 @@ wi::lrshift_large (HOST_WIDE_INT *val, c
> unsigned int xlen, unsigned int xprecision,
> unsigned int precision, unsigned int shift)
> {
> - unsigned int len = rshift_large_common (val, xval, xlen, xprecision,
> s
In tree-vect-stmts.cc
vect_check_scalar_mask
Failed here:
/* If the caller is not prepared for adjusting an external/constant
SLP mask vector type fail. */
if (slp_node
&& !mask_node
&& SLP_TREE_DEF_TYPE (mask_node_1) != vect_internal_def)
{
if (dump_enabled_p ())
On Thu, Oct 12, 2023 at 11:54:14AM +0100, Richard Sandiford wrote:
> Jakub Jelinek writes:
> > @@ -2036,11 +2075,20 @@ wi::lrshift_large (HOST_WIDE_INT *val, c
> >unsigned int xlen, unsigned int xprecision,
> >unsigned int precision, unsigned int shift)
> > {
> > -
On Wed, 11 Oct 2023, Robin Dapp wrote:
> > It wasn't very clear, sorry, but it was the last sentence I was asking
> > for clarification on, not the other bits. Why do we want to avoid
> > generating a COND_ADD when the operand is a vectorisable call?
>
> Ah, I see, apologies. Upon thinking abou
On Thu, 12 Oct 2023, juzhe.zh...@rivai.ai wrote:
> Hi, Richi.
>
> I restrict as you said into vect_external_def.
>
> Then this condition made SLP failed:
>
> - if (mask_index >= 0
> + if (mask_index >= 0 && internal_fn_len_index (ifn) < 0
> && !vect_check_scalar_mask (vinfo,
On Thu, 12 Oct 2023, juzhe.zh...@rivai.ai wrote:
> Oh. I see.
>
> Here make vect_constant_def failed to SLP:
>
> tree-vect-slp.cc:
> vect_build_slp_tree_2
> line 2354:
>
> if (oprnd_info->first_dt == vect_external_def
> || oprnd_info->first_dt == vect_constant_def)
> {
>
On Thu, 12 Oct 2023, juzhe.zh...@rivai.ai wrote:
> In tree-vect-stmts.cc
>
> vect_check_scalar_mask
>
> Failed here:
>
> /* If the caller is not prepared for adjusting an external/constant
> SLP mask vector type fail. */
> if (slp_node
> && !mask_node
^^^
where's the mask_node
Hi,
Thanks for your quick fix!
Michael Meissner writes:
> I was building a cross compiler to PowerPC on my x86_86 workstation with the
> latest version of GCC on October 11th. I could not build the compiler on the
> x86_64 system as it died in building libgcc. I looked into it, and I
> disc
The mask node is NULL since the caller :
if (mask_index >= 0
&& !vect_check_scalar_mask (vinfo, stmt_info, slp_node, mask_index,
&mask, NULL, &mask_dt, &mask_vectype))
return false;
pass NULL to mask_node.
juzhe.zh...@rivai.ai
From
On Thu, Oct 12, 2023 at 4:24 AM Michael Meissner
wrote:
> I was building a cross compiler to PowerPC on my x86_86 workstation with
> the
> latest version of GCC on October 11th. I could not build the compiler on
> the
> x86_64 system as it died in building libgcc. I looked into it, and I
> disc
HAO CHEN GUI writes:
> Hi,
> Vector mode instructions are efficient on some targets (e.g. ppc64).
> This patch enables vector mode for compare_by_pieces. The non-member
> function widest_fixed_size_mode_for_size takes by_pieces_operation
> as the second argument and decide whether vector mode is
Jakub Jelinek writes:
> On Thu, Oct 12, 2023 at 11:54:14AM +0100, Richard Sandiford wrote:
>> Jakub Jelinek writes:
>> > @@ -2036,11 +2075,20 @@ wi::lrshift_large (HOST_WIDE_INT *val, c
>> > unsigned int xlen, unsigned int xprecision,
>> > unsigned int precision, unsig
Hi Richard.
Thanks for looking at this! :)
> "Jose E. Marchesi" writes:
>> ping
>
> I don't know this code very well, and have AFAIR haven't worked
> with an assembler that requires external declarations, but since
> it's at a second ping :)
>
>>
>>> ping
>>>
[Differences from V1:
-
On Thu, 12 Oct 2023, Richard Biener wrote:
> The following handles byte-aligned, power-of-two and byte-multiple
> sized BIT_FIELD_REF reads in SRA. In particular this should cover
> BIT_FIELD_REFs created by optimize_bit_field_compare.
>
> For gcc.dg/tree-ssa/ssa-dse-26.c we now SRA the BIT_FIEL
Hi Richard,
being the one who wrote the surrounding code:
The fortran part looks good to me.
Ok for merge from the fortran side.
- Andre
On Thu, 12 Oct 2023 11:44:01 + (UTC)
Richard Biener wrote:
> On Thu, 12 Oct 2023, Richard Biener wrote:
>
> > The following handles byte-aligned, power-
On Thursday, 12 October 2023, Jakub Jelinek wrote:
> Hi!
>
> The following testcase started FAILing recently after the
>
https://sourceware.org/git/?p=glibc.git;a=commit;h=64b1a44183a3094672ed304532bedb9acc707554
> glibc change which marked vfscanf with nonnull (1) attribute.
> While vfwscanf hasn
This patch improves code sinking pass to sink statements before call to reduce
register pressure.
Review comments are incorporated. Synced with latest sources and modify the
code changes
accordingly.
For example :
void bar();
int j;
void foo(int a, int b, int c, int d, int e, int f)
{
int l;
This patch improves code sinking pass to sink statements before call to reduce
register pressure.
Review comments are incorporated.
Synced with latest trunk sources and modify the sinking pass accordingly.
For example :
void bar();
int j;
void foo(int a, int b, int c, int d, int e, int f)
{
int
"Jose E. Marchesi" writes:
> Hi Richard.
> Thanks for looking at this! :)
>
>
>> "Jose E. Marchesi" writes:
>>> ping
>>
>> I don't know this code very well, and have AFAIR haven't worked
>> with an assembler that requires external declarations, but since
>> it's at a second ping :)
>>
>>>
pi
From: Christoph Müllner
Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
A recent change broke the xtheadcondmov-indirect tests, because the order of
emitted instructions changed. Since the test is too strict when testing for
a fixed instruction order, let's change the tests
This implements atan2 which was missing from LibF7.
Johann
--
LibF7: Implement atan2.
libgcc/config/avr/libf7/
* libf7.c (F7MOD_atan2_, f7_atan2): New module and function.
* libf7.h: Adjust comments.
* libf7-common.mk (CALL_PROLOGUES): Add atan2.
diff --git a/libgcc/c
Robin Dapp via Gcc-patches writes:
> Hi,
>
> as Juzhe noticed in gcc.dg/pr92301.c there was still something missing in
> the last patch. The attached v2 makes sure we always have a COND_LEN
> operation
> before returning true and initializes len and bias even if they are unused.
>
> Bootstrapped
> "Jose E. Marchesi" writes:
>> Hi Richard.
>> Thanks for looking at this! :)
>>
>>
>>> "Jose E. Marchesi" writes:
ping
>>>
>>> I don't know this code very well, and have AFAIR haven't worked
>>> with an assembler that requires external declarations, but since
>>> it's at a second ping :)
On 10/12/23 04:05, Mary Bennett wrote:
gcc/ChangeLog:
* doc/extend.texi: Change subsubsection to subsection for
CORE-V built-ins.
This is OK. I'll commit it shortly it.
jeff
"Jose E. Marchesi" writes:
>> "Jose E. Marchesi" writes:
>>> Hi Richard.
>>> Thanks for looking at this! :)
>>>
>>>
"Jose E. Marchesi" writes:
> ping
I don't know this code very well, and have AFAIR haven't worked
with an assembler that requires external declarations, but
From: Pan Li
This patch would like to support the FP lceil/lceilf auto vectorization.
* long lceil (double) for rv64
* long lceilf (float) for rv32
Due to the limitation that only the same size of data type are allowed
in the vectorier, the standard name lceilmn2 only act on DF => DI for
rv64,
Richard Sandiford writes:
> Robin Dapp via Gcc-patches writes:
>> [...]
>> @@ -386,9 +390,29 @@ try_conditional_simplification (internal_fn ifn,
>> gimple_match_op *res_op,
>> default:
>>gcc_unreachable ();
>> }
>> - *res_op = cond_op;
>> - maybe_resimplify_conditional_op (se
Hi All,
At the moment, trying to use -march=armv9-a with any ACLE header such as
arm_neon.h results in rows and rows of warnings saying:
: warning: "__ARM_ARCH" redefined
: note: this is the location of the previous definition
This is obviously not useful and happens because the header was defin
Tamar Christina writes:
> Hi All,
>
> At the moment, trying to use -march=armv9-a with any ACLE header such as
> arm_neon.h results in rows and rows of warnings saying:
>
> : warning: "__ARM_ARCH" redefined
> : note: this is the location of the previous definition
>
> This is obviously not useful
LGTM but I'm not a maintainer ;-)
On Thu, 12 Oct 2023 at 04:21, Hans-Peter Nilsson wrote:
>
> Ping.
>
> > From: Hans-Peter Nilsson
> > Date: Wed, 4 Oct 2023 19:04:55 +0200
> >
> > > From: Hans-Peter Nilsson
> > > Date: Wed, 4 Oct 2023 17:15:28 +0200
> >
> > > New version coming up.
> >
> > Usin
LGTM but I'm not a maintainer ;-)
On Thu, 12 Oct 2023 at 04:22, Hans-Peter Nilsson wrote:
>
> Ping.
>
> > From: Hans-Peter Nilsson
> > Date: Wed, 4 Oct 2023 19:08:16 +0200
> >
> > s/atomic-exchange/atomic-cmpxchg-word/g.
> > Tested as v1.
> >
> > Ok to commit?
> > -- >8 --
> > These tests actual
I would prefer first approach since it no changes other than adding
testcase, that might confusing other people.
Li, Pan2 於 2023年10月11日 週三 23:12 寫道：
> Sorry for misleading here.
>
> When implement the llrint after lrint, I realize llrint (DF => SF) are
> supported by the lrint already in the pr
On 10/12/23 04:05, Mary Bennett wrote:
gcc/ChangeLog:
* doc/extend.texi: Change subsubsection to subsection for
CORE-V built-ins.
Thanks for jumping on it quickly. I added the PR marker to the
ChangeLog entry (bugzilla integration) and pushed this to the trunk.
jeff
Hi!
While my wide_int patch bootstrapped/regtested fine when I used GCC 12
as system gcc, apparently it doesn't with GCC 11 and older or clang++.
For GCC before PR96555 C++ DR1315 implementation the compiler complains
about template argument involving template parameters, for clang++ the
same + co
On 10/12/23 03:41, Alex Coplan wrote:
Hi,
The description of the REG_NOALIAS note in reg-notes.def isn't quite
right. It describes it as being attached to call insns, but it is
instead attached to a move insn receiving the return value from a call.
This can be seen by looking at the code in
On 10/12/23 08:38, Christophe Lyon wrote:
LGTM but I'm not a maintainer ;-)
LGTM to as well -- I usually try to stay out of libstdc++, but this
looks simple enough. Both patches in this series are OK.
jeff
On 10/11/23 19:37, Hans-Peter Nilsson wrote:
```
foo2:
sext.w a6,a1 <-- this goes away
beq a1,zero,.L4
li a5,0
li a0,0
.L3:
addwa4,a2,a5
addwa5,a3,a5
addwa0,a4,a0
bltua5,a6,.L3
re
On 10/12/23 07:06, Christoph Muellner wrote:
From: Christoph Müllner
Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
A recent change broke the xtheadcondmov-indirect tests, because the order of
emitted instructions changed. Since the test is too strict when testing for
On 10/11/23 17:17, Kito Cheng wrote:
Yeah, I'll take you suggestion and go ahead, Robin's suggestion is
great but it's just a little too magic :P
So there'll be a V2 of this patch, right? Just want to make sure state
is correct in patchwork.
jeff
Yeah, will send v2 today
Jeff Law 於 2023年10月12日 週四 09:15 寫道：
>
>
> On 10/11/23 17:17, Kito Cheng wrote:
> > Yeah, I'll take you suggestion and go ahead, Robin's suggestion is
> > great but it's just a little too magic :P
> So there'll be a V2 of this patch, right? Just want to make sure state
>
On 10/11/23 10:42, Florian Weimer wrote:
Add -std=gnu89 to some tests which evidently target C89-only language
features.
gcc/testsuite/
* gcc.c-torture/compile/920501-11.c: Compile with -std=gnu89.
* gcc.c-torture/compile/920501-23.c: Likewise.
* gcc.c-torture/compile
On 10/11/23 10:53, Florian Weimer wrote:
These changes are assumed not to interfere with the test objective,
but it was not possible to reproduce the historic test case failures
(with or without the modification here).
gcc/testsuite/
* gcc.c-torture/compile/2105-1.c: Add missing
On 10/11/23 10:55, Florian Weimer wrote:
The updated test cases still reproduce the bugs with old compilers.
gcc/testsuite/
* gcc.c-torture/compile/pc44485.c (func_21): Add missing cast.
* gcc.c-torture/compile/pr106101.c: Use builtins to avoid
calls to undeclared fun
I noticed that while OMP_DEFAULT_DEVICE was updated a ref to
OMP_TARGET_OFFLOAD (→ mandatory case) was missing. And
OMP_TARGET_OFFLOAD wasn't updated at all for those changes.
I hope the new version is clearer.
Current versions:
https://gcc.gnu.org/onlinedocs/libgomp/OMP_005fDEFAULT_005fDEVICE.h
On 10/9/23 08:59, Juzhe-Zhong wrote:
These cases won't check SLP for load_lanes support target.
Add vectorization check for situations.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr97832-2.c: Add vectorization check.
* gcc.dg/vect/pr97832-3.c: Ditto.
* gcc.dg/vect/pr9783
Now that abi breakage is fixed and hoping that Friday is review day :-)
Ping !
On 17/09/2023 22:41, François Dumont wrote:
libstdc++: [_Hashtable] Avoid redundant usage of rehash policy
Bypass usage of __detail::__distance_fwd and check for need to rehash
when assigning an initializer_list to
On Wed, 11 Oct 2023, Ken Matsui wrote:
> Since RID_MAX soon reaches 255 and all traits are used approximately once in
> a C++ translation unit, this patch instead uses only RID_TRAIT_EXPR and
> RID_TRAIT_TYPE for all traits and uses gperf to look up the specific trait.
>
> gcc/c-family/ChangeLog:
> The support to elide calls to allocation functions in DCE runs into
> the issue that when implementations are discovered noreturn we end
> up DCEing the calls anyway, leaving blocks without termination and
> without outgoing edges which is both invalid IL and wrong-code when
> as in the example t
Sorry for the late comment after Jeff say ok, but I guess we may
consider add "-fno-schedule-insns -fno-schedule-insns2" to avoid
disturbing from schedule like some of our test case in
gcc/testsuite/gcc.target/riscv/rvv?
On Thu, Oct 12, 2023 at 9:12 AM Jeff Law wrote:
>
>
>
> On 10/12/23 07:06, C
but anyway, I don't have a strong opinion for either way, just go
ahead no matter which one you choose.
On Thu, Oct 12, 2023 at 11:28 AM Kito Cheng wrote:
>
> Sorry for the late comment after Jeff say ok, but I guess we may
> consider add "-fno-schedule-insns -fno-schedule-insns2" to avoid
> dist
riscv_legitimize_poly_move was expected to ensure the poly value is at most 32
times smaller than the minimal VLEN (32 being derived from '4096 / 128').
This assumption held when our mode modeling was not so precisely defined.
However, now that we have modeled the mode size according to the correct
On Thu, Oct 12, 2023 at 06:37:00PM +0200, Tobias Burnus wrote:
> libgomp.texi: Clarify OMP_TARGET_OFFLOAD=mandatory
>
> In OpenMP 5.0/5.1, the semantic of OMP_TARGET_OFFLOAD=mandatory was
> insufficiently specified; 5.2 clarified this with extensions/clarifications
> (omp_initial_device, omp_inval
On Tue, 26 Sep 2023, Patrick Palka wrote:
> Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK
> for trunk?
>
> -- >8 --
>
> This follow-up patch removes some more repetition of the type-dependent
On second thought there's no good reason to split these patches into a two
part
On 10/12/23 04:53, Nathaniel Shead wrote:
On Wed, Oct 11, 2023 at 12:48:12AM +1100, Nathaniel Shead wrote:
On Mon, Oct 09, 2023 at 04:46:46PM -0400, Jason Merrill wrote:
On 10/8/23 21:03, Nathaniel Shead wrote:
Ping for https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631203.html
+
Hi,
on riscv insn-emit.cc has grown to over 1.2 mio lines of code and
compiling it takes considerable time.
Therefore, this patch adjust genemit to create ten files insn-emit-1.cc
to insn-emit-10.cc. In order to do so it first counts the number of
available patterns, calculates the number of patt
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?
-- >8 --
My recent patch introducing cp_fold_immediate_r caused exponential
compile time with nested COND_EXPRs. The problem is that the COND_EXPR
case recursively walks the arms of a COND_EXPR, but after processing
both arms it doesn't
On Thu, Oct 12, 2023 at 04:24:00PM -0400, Jason Merrill wrote:
> On 10/12/23 04:53, Nathaniel Shead wrote:
> > On Wed, Oct 11, 2023 at 12:48:12AM +1100, Nathaniel Shead wrote:
> > > On Mon, Oct 09, 2023 at 04:46:46PM -0400, Jason Merrill wrote:
> > > > On 10/8/23 21:03, Nathaniel Shead wrote:
> > >
On Thu, 12 Oct 2023, 17:11 Jeff Law, wrote:
>
>
> On 10/12/23 08:38, Christophe Lyon wrote:
> > LGTM but I'm not a maintainer ;-)
> LGTM to as well -- I usually try to stay out of libstdc++, but this
> looks simple enough. Both patches in this series are OK.
>
Thanks for stepping in, Jeff. The
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-12 22:17
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP lceil/lceilf auto vectorization
From: Pan Li
This patch would like to support the FP lceil/lceilf auto vectorization.
LGTM
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-10-13 02:40
To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong
CC: Kito Cheng
Subject: [PATCH v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets
where the minimal VLEN exceeds 512.
riscv_legitimize_poly_move
Sure thing, thanks a lot and will follow the guidance.
Pan
From: Kito Cheng
Sent: Thursday, October 12, 2023 10:42 PM
To: Li, Pan2
Cc: 钟居哲 ; gcc-patches ; Wang,
Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support FP llrint auto vectorization
I would prefer first approach since it no changes ot
From: Pan Li
This patch would like to support the FP lfloor/lfloorf auto vectorization.
* long lfloor (double) for rv64
* long lfloorf (float) for rv32
Due to the limitation that only the same size of data type are allowed
in the vectorier, the standard name lfloormn2 only act on DF => DI for
r
On 10/12/23 17:04, Marek Polacek wrote:
Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?
-- >8 --
My recent patch introducing cp_fold_immediate_r caused exponential
compile time with nested COND_EXPRs. The problem is that the COND_EXPR
case recursively walks the arms of a COND_EXPR,
OK.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 09:38
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP lfloor/lfloorf auto vectorization
From: Pan Li
This patch would like to support the FP lfloor/lfloorf auto vectorization.
From: Pan Li
Leverage stdint-gcc.h for the int64_t types instead of typedef.
Or we may have conflict with stdint-gcc.h in somewhere else.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c: Include
stdint-gcc.h for int types.
* gcc.target/riscv/
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-13 10:22
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Leverage stdint-gcc.h for RVV test cases
From: Pan Li
Leverage stdint-gcc.h for the int64_t types instead of typedef.
Or we may hav
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, October 13, 2023 10:26 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Leverage stdint-gcc.h for RVV test cases
LGTM。
juzhe.zh...@r
On Thu, Jul 6, 2023 at 1:53 PM Uros Bizjak via Gcc-patches
wrote:
>
> On Thu, Jul 6, 2023 at 3:14 AM liuhongt wrote:
> >
> > For testcase
> >
> > void __cond_swap(double* __x, double* __y) {
> > bool __r = (*__x < *__y);
> > auto __tmp = __r ? *__x : *__y;
> > *__y = __r ? *__y : *__x;
> >
Committed with few changelog tweak :P
On Thu, Oct 12, 2023 at 3:37 PM 钟居哲 wrote:
>
> LGTM
>
>
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-10-13 02:40
> To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong
> CC: Kito Cheng
> Subject:
> Date: Fri, 29 Sep 2023 16:37:21 -0600
> From: Jeff Law
> So this ends up looking a lot like the bits that I had to revert several
> weeks ago :-)
>
> The core issue we have is given an INSN the generic code will cost the
> SET_SRC and SET_DEST and sum them. But that's far from ideal on a RI
This patch fixes this following FAILs in RISC-V regression:
FAIL: gcc.dg/vect/vect-gather-1.c -flto -ffat-lto-objects scan-tree-dump vect
"Loop contains only SLP stmts"
FAIL: gcc.dg/vect/vect-gather-1.c scan-tree-dump vect "Loop contains only SLP
stmts"
FAIL: gcc.dg/vect/vect-gather-3.c -flto -
Hi, Richi.
As you suggest, I keep MAK_LEN_GATHER_LOAD (...,-1) format and support SLP for
that in V3:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632846.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-12 19:14
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richar
From: Pan Li
The below FP API are supported already by sharing the same standard
name, as well as the machine mode.
int iroundf (float);
This patch would like to add the test cases for ensuring the
correctness.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/math-iround-0
lgtm Replied Message Frompan2...@intel.comDate10/13/2023 13:33 Togcc-patches@gcc.gnu.org Ccjuzhe.zh...@rivai.ai,pan2...@intel.com,yanzhang.w...@intel.com,kito.ch...@gmail.comSubject[PATCH v1] RISC-V: Add test for FP iroundf auto vectorization
Committed, thanks Juzhe.
Pan
From: juzhe.zhong
Sent: Friday, October 13, 2023 1:39 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; Li, Pan2 ; Wang, Yanzhang
; kito.ch...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Add test for FP iroundf auto vectorization
lgtm
Replied Message
From
pan2.
Like ARM SVE and GCN, add RVV.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
---
gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
b/gcc/testsuite/gcc.dg/vect
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