Sorry for the late comment after Jeff say ok, but I guess we may
consider add "-fno-schedule-insns -fno-schedule-insns2" to avoid
disturbing from schedule like some of our test case in
gcc/testsuite/gcc.target/riscv/rvv?
On Thu, Oct 12, 2023 at 9:12 AM Jeff Law <jeffreya...@gmail.com> wrote:
>
>
>
> On 10/12/23 07:06, Christoph Muellner wrote:
> > From: Christoph Müllner <christoph.muell...@vrull.eu>
> >
> > Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
> >
> > A recent change broke the xtheadcondmov-indirect tests, because the order of
> > emitted instructions changed. Since the test is too strict when testing for
> > a fixed instruction order, let's change the tests to simply count
> > instruction,
> > like it is done for similar tests.
> >
> > Reported-by: Patrick O'Neill <patr...@rivosinc.com>
> > Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against
> > instruction reordering.
> OK for the trunk.
>
> jeff
