Now that every insn is guaranteed a type, we want to ensure the types are
handled by the existing scheduling descriptions.
There are 2 approaches I see:
1. Create a new pipeline intended to eventually abort (sifive-7.md)
2. Add the types to an existing pipeline (generic.md)
Which approach do w
So currently we have a simplification for `a | ~(a ^ b)` but
that does not match the case where we had originally `(~a) | (a ^ b)`
so we need to add a new pattern that matches that and uses
bitwise_inverted_equal_p
that also catches comparisons too.
OK? Bootstrapped and tested on x86_64-linux-gnu
Despite not defining `vec_pack_trunc_' standard named patterns the
backend provides vector pack operations via its own `@pred_trunc'
set of patterns and they do trigger in vectorization producing narrowing
VNCVT.X.X.W assembly instructions as expected.
Enable the `vect_pack_trunc' setting for R
&& [check_effective_target_arm_little_endian])
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
+|| [istarget riscv*-*-*]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])
Btw, could you rebase to the trunk and run regression again?
I saw your report 670 FAILs:
# of expected passes 187616
# of unexpected failures 672
# of unexpected successes 14
# of expected failures 1436
# of unresolved testcases 615
# of unsupported tests
On Tue, 10 Oct 2023, 钟居哲 wrote:
>&& [check_effective_target_arm_little_endian])
>|| ([istarget mips*-*-*]
>&& [et-is-effective-target mips_msa])
> + || [istarget riscv*-*-*]
>|| ([istarget s390*-*-*]
>&& [check_effect
I know you want vect_int to block the test for rv64gc.
But unfortunately it failed.
And I have changed everything to run vect testsuite with "riscv_v".
[PATCH] RISC-V: Enable more tests of "vect" for RVV (gnu.org)
So to be consistent, plz add "riscv_v".
juzhe.zh...@rivai.ai
From: Maciej W.
On Tue, 10 Oct 2023, 钟居哲 wrote:
> Btw, could you rebase to the trunk and run regression again?
Full regression-testing takes roughly 40 hours here and I do not normally
update the tree midway through my work so as not to add variables and end
up chasing a moving target, especially with such an
From: Christoph Müllner
Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
A recent change broke the xtheadcondmov-indirect tests, because the order of
emitted instructions changed. Since the test is too strict when testing for
a fixed instruction order, let's change the tests
On Mon, Oct 9, 2023 at 10:48 PM Vineet Gupta wrote:
>
> On 10/9/23 13:46, Christoph Müllner wrote:
> > Given that this causes repeated issues, I think that a fall-back to
> > counting occurrences is the right thing to do. I can do that if that's ok.
>
> Thanks Christoph.
Tested patch on list:
h
For RVV, we have VLS modes enable according to TARGET_MIN_VLEN
from M1 to M8.
For example, when TARGET_MIN_VLEN = 128 bits, we enable
128/256/512/1024 bits VLS modes.
This patch fixes following FAIL:
FAIL: gcc.dg/vect/bb-slp-subgroups-2.c -flto -ffat-lto-objects
scan-tree-dump-times slp2 "optim
Oh. I realize this patch increase FAIL that I recently fixed:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632247.html
This fail because RVV doesn't have vec_pack_trunc_optab (Loop vectorizer will
failed at first time but succeed at 2nd time),
then RVV will dump 4 times FOLD_EXTRACT_L
Like GCN, RVV also has 64 bytes vectors (512 bits) which cause FAIL in this
test.
It's more reasonable to use "vect512" instead of AMDGCN.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-68.c: Use vect512.
---
gcc/testsuite/gcc.dg/vect/bb-slp-68.c | 2 +-
1 file changed, 1 insertion(+),
Here is the reference comparing dump IR between ARM SVE and RVV.
https://godbolt.org/z/zqess8Gss
We can see RVV has one more dump IR:
optimized: basic block part vectorized using 128 byte vectors
since RVV has 1024 bit vectors.
The codegen is reasonable good.
However, I saw GCN also has 1024 bi
Hi,
There are a few PRs (meta-bug PR101926) on various targets.
The root causes of them are similar: the aggeragte param/
returns are passed by multi-registers, but they are stored
to stack from registers first; and then, access the
parameter through stack slot.
A general idea to enhance this: a
This patch fixes following 2 FAILs in RVV regression since the check is not
accurate.
It's inspired by Robin's previous patch:
https://patchwork.sourceware.org/project/gcc/patch/dde89b9e-49a0-d70b-0906-fb3022cac...@gmail.com/
gcc/testsuite/ChangeLog:
* gcc.dg/vect/no-scevccp-outer-7.c:
Hi,
For "get_global_range_query" SSA_NAME_RANGE_INFO can be queried.
For "get_range_query", it could get more context-aware range info.
And look at the implementation of "get_range_query", it returns
global range if no local fun info.
So, if not quering for SSA_NAME, it would be ok to use get_ra
Like GCN, add -fno-tree-vectorize.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/predcom-2.c: Add riscv.
---
gcc/testsuite/gcc.dg/tree-ssa/predcom-2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/predcom-2.c
b/gcc/testsuite/gcc.dg/tree-
I guess you may also want to clean up those bodies for "check-function-bodies"?
On Mon, Oct 9, 2023 at 3:47 PM Christoph Muellner
wrote:
>
> From: Christoph Müllner
>
> Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
>
> A recent change broke the xtheadcondmov-indirect test
LGTM
On Mon, Oct 9, 2023 at 4:23 PM Juzhe-Zhong wrote:
>
> For RVV, we have VLS modes enable according to TARGET_MIN_VLEN
> from M1 to M8.
>
> For example, when TARGET_MIN_VLEN = 128 bits, we enable
> 128/256/512/1024 bits VLS modes.
>
> This patch fixes following FAIL:
> FAIL: gcc.dg/vect/bb-slp
This patch:
* changes splice_viable to move the non-viable candidates to the end
of the list instead of removing them outright
* makes tourney move the best candidate to the front of the candidate
list
* adjusts print_z_candidates to preserve our behavior of printing only
viable
With the previous improvements in place, we can easily extend our
deletedness diagnostic to note the other candidates:
deleted16.C: In function ‘int main()’:
deleted16.C:10:4: error: use of deleted function ‘void f(int)’
10 | f(0);
| ~^~~
deleted16.C:5:6: note: declared here
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, October 10, 2023 11:20 AM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Add available vector size for RVV
LGTM
This patch set implement target attribute for RISC-V target, which is similar
to other target like x86 or ARM, let user able to set some local setting per
function without changing global settings.
We support arch, tune and cpu first, and we will support other target attribute
later, this versi
We TARGET__P marcro to test a Mask and InverseMask with user
specified target_variable, however we may want to test with specific
gcc_options variable rather than target_variable.
Like RISC-V has defined lots of Mask with TargetVariable, which is not
easy to use, because that means we need to know
Allow those funciton apply from a local gcc_options rather than the
global options.
Preparatory for target attribute, sperate this change for eaiser reivew
since it's a NFC.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_convert_vector_bits): Get setting
from argument rather than
The target attribute which proposed in [1], target attribute allow user
to specify a local setting per-function basis.
The syntax of target attribute is `__attribute__((target("")))`.
and the syntax of `` describes below:
```
ATTR-STRING := ATTR-STRING ';' ATTR
| ATTR
ATTR:=
riscv_subset_list only accept a full arch string before, but we need to
parse single extension when supporting target attribute, also we may set
a riscv_subset_list directly rather than re-parsing the ISA string
again.
gcc/ChangeLog:
* config/riscv/riscv-subset.h (riscv_subset_list::parse
From: "Zhang, Jun"
By test, we find in hybrid platform spincount 1 is better.
Use '-march=native -Ofast -funroll-loops -flto',
results as follows:
spec2017 speed RPL ADL
657.xz_s 0.00% 0.50%
603.bwaves_s 10.90% 26.20%
607.cactuBSSN_s 5.50% 72.50%
619.lbm_s2.40%
From: "Mo, Zewei"
Hi,
Intel APX PUSH2POP2 feature has been released in [1].
This feature requires stack to be aligned at 16byte, therefore in
prologue/epilogue, a standalone push/pop will be emitted before any
push2/pop2 if the stack was not aligned to 16byte.
Also for current implementation w
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