> Maybe I should pretend RVV support vect_pack/vect_unpack and enable
> all the tests in target-supports.exp?
The problem is that vect_pack/unpack is an overloaded term in the
moment meaning "vector conversion" (promotion/demotion) or so. This
test does not require pack/unpack for successful vect
Hi, Richi and Robin.
Turns out COND(_LEN)?_ADD can't work.
Is this patch Ok ? Or do you have another solution to change the dump check for
RVV?
Thanks.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-10-08 09:33
To: gcc-patches
CC: rguenther; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject:
On Sat, 7 Oct 2023, Richard Sandiford wrote:
> Richard Biener writes:
> >> Am 07.10.2023 um 11:23 schrieb Richard Sandiford
> >> >> Richard Biener writes:
> >>> On Thu, 5 Oct 2023, Tamar Christina wrote:
> >>>
> > I suppose the idea is that -abs(x) might be easier to optimize with
>
On Mon, 9 Oct 2023, juzhe.zh...@rivai.ai wrote:
> Hi, Richi and Robin.
>
> Turns out COND(_LEN)?_ADD can't work.
Did you try quoting? Try (_LEN|) maybe.
> Is this patch Ok ? Or do you have another solution to change the dump check
> for RVV?
>
> Thanks.
>
>
>
> juzhe.zh...@rivai.ai
>
>
On Sun, 8 Oct 2023, Jeff Law wrote:
>
>
> On 10/8/23 05:35, Juzhe-Zhong wrote:
> > RVV (RISC-V Vector) doesn't enable vect_unpack, but we still vectorize this
> > case well.
> > So, adjust dump check for RVV.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.dg/vect/vect-multitypes-16.c: Fix dum
On Okt 09 2023, juzhe.zh...@rivai.ai wrote:
> Turns out COND(_LEN)?_ADD can't work.
It should work though. Tcl regexps are a superset of POSIX EREs.
--
Andreas Schwab, SUSE Labs, sch...@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something comp
Yes. We do have && enable char -> long conversion (vsext.vf8/vzext.vf8)
Thanks for the comment, I will adapt test as you suggested.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-09 15:31
To: Jeff Law
CC: Juzhe-Zhong; gcc-patches; richard.sandiford
Subject: Re: [PATCH] TEST: Fix dump
On Mon, Oct 9, 2023 at 12:20 AM Richard Biener wrote:
>
> On Sat, 7 Oct 2023, Richard Sandiford wrote:
>
> > Richard Biener writes:
> > >> Am 07.10.2023 um 11:23 schrieb Richard Sandiford
> > >> >> Richard Biener writes:
> > >>> On Thu, 5 Oct 2023, Tamar Christina wrote:
> > >>>
> > > I su
On Mon, 9 Oct 2023, Robin Dapp wrote:
> > Maybe I should pretend RVV support vect_pack/vect_unpack and enable
> > all the tests in target-supports.exp?
>
> The problem is that vect_pack/unpack is an overloaded term in the
> moment meaning "vector conversion" (promotion/demotion) or so. This
> te
On Sun, Oct 8, 2023 at 9:22 AM Juzhe-Zhong wrote:
>
> Previously, I removed the movmisalign pattern to fix the execution FAILs in
> this commit:
> https://github.com/gcc-mirror/gcc/commit/f7bff24905a6959f85f866390db2fff1d6f95520
>
> I was thinking that RVV doesn't allow misaligned at the beginnin
>> But you gobble the "or .." into an existing -mstrict-align flag - are
>> you sure all implementations are
>> self-consistent with handling non-vector memory instructions and
>> vector memory instructions here?
>> At least the above wording doesn't seem to impose such requirement.
RVV ISA：
"Sup
On Sun, 8 Oct 2023, Juzhe-Zhong wrote:
> As this showed: https://godbolt.org/z/3K9oK7fx3
>
> ARM SVE 2 times for FOLD_EXTRACT_LAST wheras RVV 4 times.
>
> This is because RISC-V doesn't enable vec_pack_trunc so we will failed
> conversion and fold_extract_last at the first time analysis.
> Then
On Sun, 8 Oct 2023, Juzhe-Zhong wrote:
> gcc/testsuite/ChangeLog:
OK
>
> * gcc.dg/vect/bb-slp-cond-1.c: Fix dump FAIL for RVV.
> * gcc.dg/vect/pr57705.c: Ditto.
>
> ---
> gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c | 4 ++--
> gcc/testsuite/gcc.dg/vect/pr57705.c | 4 ++--
> 2
On Sun, 8 Oct 2023, Juzhe-Zhong wrote:
> Even though RVV doesn't enable vec_unpack/vec_pack, it succeed on outer loop
> vectorizations.
How so? I think this maybe goes with the other similar change.
That is, when we already have specific target checks adding riscv-*-*
looks sensible but when
On Fri, 6 Oct 2023, Robin Dapp wrote:
> > So if you think you got everything correct the patch is OK as-is,
> > I just wasn't sure - maybe the neutral_element change deserves
> > a comment as to how MINUS_EXPR is handled.
>
> Heh, I never think I got everything correct ;)
>
> Added this now:
>
Thanks Richi.
I will try to figure out a better way to adapt the tests without adding riscv*
specific targets variant.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-10-09 16:17
To: Juzhe-Zhong
CC: gcc-patches; jeffreyalaw
Subject: Re: [PATCH] TEST: Fix XPASS of outer loop vectorizatio
From: Pan Li
This patch would like to refine the code gen for the bswap16.
We will have VEC_PERM_EXPR after rtl expand when invoking
__builtin_bswap. It will generate about 9 instructions in
loop as below, no matter it is bswap16, bswap32 or bswap64.
.L2:
1 vle16.v v4,0(a0)
2 vmv.v.x v2,a7
3
Remove these functions:
+static void
+emit_vec_sll_scalar (rtx op_0, rtx op_1, rtx op_2, machine_mode vec_mode)
+{
+ rtx sll_ops[] = {op_0, op_1, op_2};
+ insn_code icode = code_for_pred_scalar (ASHIFT, vec_mode);
+
+ emit_vlmax_insn (icode, BINARY_OP, sll_ops);
+}
+
+static void
+emit_vec_srl_
On Mon, 9 Oct 2023, Andrew Pinski wrote:
> On Mon, Oct 9, 2023 at 12:20?AM Richard Biener wrote:
> >
> > On Sat, 7 Oct 2023, Richard Sandiford wrote:
> >
> > > Richard Biener writes:
> > > >> Am 07.10.2023 um 11:23 schrieb Richard Sandiford
> > > >> >> Richard Biener
> > > >> writes:
> > > >
Hi Juzhe,
I think an extra param might be too intrusive. I would expect normal
hardware implementations to support unaligned accesses (but they might
be slow which should be covered by costs) and only rarely have hardware
that doesn't support it and raises exceptions.
Therefore I would suggest t
On Fri, Oct 6, 2023 at 3:59 PM Roger Sayle wrote:
>
>
> Grr! I've done it again. ENOPATCH.
>
> > -Original Message-
> > From: Roger Sayle
> > Sent: 06 October 2023 14:58
> > To: 'gcc-patches@gcc.gnu.org'
> > Cc: 'Uros Bizjak'
> > Subject: [X86 PATCH] Implement doubleword right shifts
> On 9 Oct 2023, at 06:06, François Dumont wrote:
>
> I think we can do the same without the symbol alias feature. It's even
> simpler cause do not require any maintenance when version symbol bump.
>
> Here is what I'm testing, at least exported symbol is fine.
Thanks; works for me, (g++ te
On 07/10/2023 02:04, juzhe.zh...@rivai.ai wrote:
Thanks for reporting it.
I think we may need to change it into:
+ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 4
"vect" { target {! vect_load_lanes } } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SL
> -Original Message-
> From: Richard Sandiford
> Sent: Saturday, October 7, 2023 10:58 AM
> To: Richard Biener
> Cc: Tamar Christina ; gcc-patches@gcc.gnu.org;
> nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Kyrylo Tkachov
>
> Subject: Re: [PATCH]AArch64 Add SVE implementation for cond_co
On Mon, Oct 9, 2023 at 11:39 AM Tamar Christina wrote:
>
> > -Original Message-
> > From: Richard Sandiford
> > Sent: Saturday, October 7, 2023 10:58 AM
> > To: Richard Biener
> > Cc: Tamar Christina ; gcc-patches@gcc.gnu.org;
> > nd ; Richard Earnshaw ;
> > Marcus Shawcroft ; Kyrylo Tka
> -Original Message-
> From: Richard Biener
> Sent: Monday, October 9, 2023 10:45 AM
> To: Tamar Christina
> Cc: Richard Sandiford ; gcc-
> patc...@gcc.gnu.org; nd ; Richard Earnshaw
> ; Marcus Shawcroft
> ; Kyrylo Tkachov
> Subject: Re: [PATCH]AArch64 Add SVE implementation for cond_cop
Tamar Christina writes:
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Saturday, October 7, 2023 10:58 AM
>> To: Richard Biener
>> Cc: Tamar Christina ; gcc-patches@gcc.gnu.org;
>> nd ; Richard Earnshaw ;
>> Marcus Shawcroft ; Kyrylo Tkachov
>>
>> Subject: Re: [PATCH]AArch64
Bootstrapped and regtested on x86_64-pc-linux-gnu with
GXX_TESTSUITE_STDS=98,11,14,17,20,23,26,impcx.
-- >8 --
This patch improves the errors given when casting from void* in C++26 to
include the expected type if the type of the pointed-to object was
not similar to the casted-to type.
It also
Hi David,
your commit breaks compilation with GCC < 6, here with GCC 5.2:
gcc/analyzer/access-diagram.cc: In member function 'void ana::boundaries::add(const
ana::access_range&, ana::boundaries::kind)':
gcc/analyzer/access-diagram.cc:655:20: error: 'kind' is not a class, namespace,
or enumerat
> -Original Message-
> From: Richard Sandiford
> Sent: Monday, October 9, 2023 10:56 AM
> To: Tamar Christina
> Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
> nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Kyrylo Tkachov
>
> Subject: Re: [PATCH]AArch64 Add SVE implementation for cond_copy
Tamar Christina writes:
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Monday, October 9, 2023 10:56 AM
>> To: Tamar Christina
>> Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
>> nd ; Richard Earnshaw ;
>> Marcus Shawcroft ; Kyrylo Tkachov
>>
>> Subject: Re: [PATCH]AArch64 Ad
On 10/9/23 09:32, Andreas Schwab wrote:
> On Okt 09 2023, juzhe.zh...@rivai.ai wrote:
>
>> Turns out COND(_LEN)?_ADD can't work.
>
> It should work though. Tcl regexps are a superset of POSIX EREs.
>
The problem is that COND(_LEN)?_ADD matches two times against
COND_LEN_ADD and a scan-tree-dum
Thanks Robin. Could you send V3 to Richi ? And commit it if Richi is ok with
that.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-10-09 18:26
To: Andreas Schwab; juzhe.zhong
CC: rdapp.gcc; gcc-patches; rguenther; jeffreyalaw
Subject: Re: [PATCH V2] TEST: Fix vect_cond_arith_* dump checks fo
Sure thing, will send V2 for this change.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, October 9, 2023 5:04 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Refine bswap16 auto vectorization code gen
Remove these functions:
+static vo
The following improves basic TBAA for access paths formed by
C++ abstraction where we are able to combine a path from an
address-taking operation with a path based on that access using
a pun to avoid memory access semantics on the address-taking part.
The trick is to identify the point the semanti
On Mon, 9 Oct 2023, Robin Dapp wrote:
> On 10/9/23 09:32, Andreas Schwab wrote:
> > On Okt 09 2023, juzhe.zh...@rivai.ai wrote:
> >
> >> Turns out COND(_LEN)?_ADD can't work.
> >
> > It should work though. Tcl regexps are a superset of POSIX EREs.
> >
>
> The problem is that COND(_LEN)?_ADD m
On Mon, Oct 9, 2023 at 12:17 PM Richard Sandiford
wrote:
>
> Tamar Christina writes:
> >> -Original Message-
> >> From: Richard Sandiford
> >> Sent: Monday, October 9, 2023 10:56 AM
> >> To: Tamar Christina
> >> Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
> >> nd ; Richard Earnshaw ;
Prathamesh Kulkarni writes:
> Hi,
> The attached patch attempts to fix PR111648.
> As mentioned in PR, the issue is when a1 is a multiple of vector
> length, we end up creating following encoding in result: { base_elem,
> arg[0], arg[1], ... } (assuming S = 1),
> where arg is chosen input vector,
> It'd be good to expand on this comment a bit. What kind of COND are you
> anticipating? A COND with the neutral op as the else value, so that the
> PLUS_EXPR (or whatever) can remain unconditional? If so, it would be
> good to sketch briefly how that happens, and why it's better than using
> t
This patch fixed these following FAILs in regressions:
FAIL: gcc.dg/vect/slp-perm-11.c -flto -ffat-lto-objects scan-tree-dump-times
vect "vectorizing stmts using SLP" 1
FAIL: gcc.dg/vect/slp-perm-11.c scan-tree-dump-times vect "vectorizing stmts
using SLP" 1
FAIL: gcc.dg/vect/vect-bitfield-read-
Reference: https://godbolt.org/z/G9jzf5Grh
RVV is able to vectorize this case using SLP. However, with
-fno-vect-cost-model,
RVV vectorize it by vec_load_lanes with stride 6.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/fast-math-slp-38.c: Add ! vect_strided6.
---
gcc/testsuite/gcc.dg/vect/
On Mon, 9 Oct 2023, Juzhe-Zhong wrote:
> Reference: https://godbolt.org/z/G9jzf5Grh
>
> RVV is able to vectorize this case using SLP. However, with
> -fno-vect-cost-model, RVV vectorize it by vec_load_lanes with stride 6.
OK. Note load/store-lanes is specifically pre-empting SLP if all
loads/s
>> OK.
Thanks. Committed.
>> Note load/store-lanes is specifically pre-empting SLP if all
>> loads/stores of a SLP intance can support that. Not sure if this
>> heuristic is good for load/store lanes with high stride?
Yeah, I understand your concern.
Em, I am sure too.
But RVV ISA define
On 10/9/23 01:02, Ramana Radhakrishnan wrote:
On 5 Oct 2023, at 14:04, Victor Do Nascimento
wrote:
External email: Use caution opening links or attachments
On 10/5/23 12:42, Richard Earnshaw wrote:
On 03/10/2023 16:18, Victor Do Nascimento wrote:
This patch adds the `aarch64-sys-re
> Hmm, the function is called at transform time so this shouldn't help
> avoiding the ICE. I expected we refuse to vectorize _any_ reduction
> when sign dependent rounding is in effect? OTOH maybe sign-dependent
> rounding is OK but only when we use a unconditional fold-left
> (so a loop mask fro
Jakub Jelinek writes:
> Hi!
>
> As mentioned in the _BitInt support thread, _BitInt(N) is currently limited
> by the wide_int/widest_int maximum precision limitation, which is depending
> on target 191, 319, 575 or 703 bits (one less than WIDE_INT_MAX_PRECISION).
> That is fairly low limit for _Bi
RVV use load_lanes with stride = 5 vectorize this case with -fno-vect-cost-model
instead of SLP.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr45752.c: Adapt dump check for target supports
load_lanes with stride = 5.
---
gcc/testsuite/gcc.dg/vect/pr45752.c | 2 +-
1 file changed, 1 insertio
On Mon, 9 Oct 2023, Robin Dapp wrote:
> > Hmm, the function is called at transform time so this shouldn't help
> > avoiding the ICE. I expected we refuse to vectorize _any_ reduction
> > when sign dependent rounding is in effect? OTOH maybe sign-dependent
> > rounding is OK but only when we use
On Mon, 9 Oct 2023, Juzhe-Zhong wrote:
> RVV use load_lanes with stride = 5 vectorize this case with
> -fno-vect-cost-model
> instead of SLP.
OK
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/vect/pr45752.c: Adapt dump check for target supports
> load_lanes with stride = 5.
>
> ---
> gcc/tes
From: Pan Li
Update in v2
* Remove emit helper functions.
* Take expand_binop instead.
Original log:
This patch would like to refine the code gen for the bswap16.
We will have VEC_PERM_EXPR after rtl expand when invoking
__builtin_bswap. It will generate about 9 instructions in
loop as below,
LGTM now.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-10-09 21:09
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Refine bswap16 auto vectorization code gen
From: Pan Li
Update in v2
* Remove emit helper functions.
* Take expand_b
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, October 9, 2023 9:07 PM
To: Juzhe-Zhong
Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V Regression test: Fix FAIL of pr45752.c for RVV
On Mon, 9 Oct 2023, Juzhe-Zhong wr
On 10/7/23 12:53, Richard Sandiford wrote:
Richard Earnshaw writes:
On 03/10/2023 16:18, Victor Do Nascimento wrote:
In implementing the ACLE read/write system register builtins it was
observed that leaving argument type checking to be done at expand-time
meant that poorly-formed function c
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, October 9, 2023 9:11 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v2] RISC-V: Refine bswap16 auto vectorization code gen
LGTM now.
Thanks.
These cases are vectorized by vec_load_lanes with strided = 8 instead of SLP
with -fno-vect-cost-model.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr97832-2.c: Adapt dump check for target supports
load_lanes with stride = 8.
* gcc.dg/vect/pr97832-3.c: Ditto.
* gcc.dg/vect/pr9
On Mon, 9 Oct 2023, Richard Biener wrote:
> The following improves basic TBAA for access paths formed by
> C++ abstraction where we are able to combine a path from an
> address-taking operation with a path based on that access using
> a pun to avoid memory access semantics on the address-taking pa
On 10/4/23 01:49, Xianmiao Qu wrote:
From: quxm
When generating CFI directives for the store-pair instruction,
if we add two parallel REG_FRAME_RELATED_EXPR expr_lists like
(expr_list:REG_FRAME_RELATED_EXPR (set (mem/c:DI (plus:DI (reg/f:DI 2 sp)
(const_int 8 [0x8])) [1 S8 A64])
This case is vectorized by stride8 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-12a.c: Adapt for stride 8 load_lanes.
---
gcc/testsuite/gcc.dg/vect/slp-12a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/slp-12a.c
b/gcc/testsuit
On Mon, 2 Oct 2023, Tamar Christina wrote:
> Hi All,
>
> This is extracted out of the patch series to support early break vectorization
> in order to simplify the review of that patch series.
>
> The goal of this one is to separate out the refactoring from the new
> functionality.
>
> This firs
Like ARM SVE, RVV is vectorizing these 2 cases in the same way.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-23.c: Add RVV like ARM SVE.
* gcc.dg/vect/slp-perm-10.c: Ditto.
---
gcc/testsuite/gcc.dg/vect/slp-23.c | 2 +-
gcc/testsuite/gcc.dg/vect/slp-perm-10.c | 2 +-
2 files
RVV vectorize it with stride5 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-perm-4.c: Adapt test for stride5 load_lanes.
---
gcc/testsuite/gcc.dg/vect/slp-perm-4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-4.c
b/gcc/
RVV vectortizes this case with stride8 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-reduc-4.c: Adapt test for stride8 load_lanes.
---
gcc/testsuite/gcc.dg/vect/slp-reduc-4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc
On Mon, Oct 09, 2023 at 01:54:19PM +0100, Richard Sandiford wrote:
> > I've additionally built it with the incremental attached patch and
> > on make -C gcc check-gcc check-g++ -j32 -k it didn't show any
> > wide_int/widest_int heap allocations unless a > 128-bit _BitInt or wb/uwb
> > constant need
On 10/9/23 07:37, Juzhe-Zhong wrote:
Like ARM SVE, RVV is vectorizing these 2 cases in the same way.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-23.c: Add RVV like ARM SVE.
* gcc.dg/vect/slp-perm-10.c: Ditto.
OK
jeff
On 10/9/23 07:39, Juzhe-Zhong wrote:
RVV vectorize it with stride5 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-perm-4.c: Adapt test for stride5 load_lanes.
OK.
As a follow-up, would it make sense to test the .vect dump for something
else in the ! {vec_load_lanes && vect
On 10/9/23 07:41, Juzhe-Zhong wrote:
RVV vectortizes this case with stride8 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-reduc-4.c: Adapt test for stride8 load_lanes.
OK. Similar question as my last ack. Do we want a follow-up here which
tests the .vect dump for the ! {
On 10/9/23 07:35, Juzhe-Zhong wrote:
This case is vectorized by stride8 load_lanes.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-12a.c: Adapt for stride 8 load_lanes.
OK. Same question as last two ACKs.
jeff
On 10/9/23 07:15, Juzhe-Zhong wrote:
These cases are vectorized by vec_load_lanes with strided = 8 instead of SLP
with -fno-vect-cost-model.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr97832-2.c: Adapt dump check for target supports
load_lanes with stride = 8.
* gcc.dg/vect/pr9
Thanks, for now this LGTM.
Regards
Robin
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, October 9, 2023 9:54 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; kito.ch...@gmail.com; kito.ch...@sifive.com;
jeffreya...@gmail.com
Subject: Re: [PATCH V2] RISC-V: Support movmisali
On Mon, 2023-10-09 at 12:09 +0200, Tobias Burnus wrote:
> Hi David,
>
> your commit breaks compilation with GCC < 6, here with GCC 5.2:
>
> gcc/analyzer/access-diagram.cc: In member function 'void
> ana::boundaries::add(const ana::access_range&,
> ana::boundaries::kind)':
> gcc/analyzer/access-di
On 10/3/23 03:09, Kito Cheng wrote:
We TARGET__P marcro to test a Mask and InverseMask with user
specified target_variable, however we may want to test with specific
gcc_options variable rather than target_variable.
Like RISC-V has defined lots of Mask with TargetVariable, which is not
easy t
On 10/3/23 03:09, Kito Cheng wrote:
Allow those funciton apply from a local gcc_options rather than the
global options.
Preparatory for target attribute, sperate this change for eaiser reivew
since it's a NFC.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_convert_vector_bits): Get s
Do you mean add a check whether it is vectorized or not？Sounds reasonable， I can add that in another patch. Replied Message FromJeff LawDate10/09/2023 21:51 ToJuzhe-Zhong,gcc-patches@gcc.gnu.org Ccrguent...@suse.deSubjectRe: [PATCH] RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV
On
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, October 9, 2023 9:49 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression test: Adapt SLP tests like ARM SVE
On 10/9/23 07:37, Juzhe-Zhong wrote:
> Like AR
On 10/9/23 08:21, juzhe.zhong wrote:
Do you mean add a check whether it is vectorized or not？
Yes.
Sounds reasonable， I can add that in another patch.
Sounds good. Thanks.
jeff
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, October 9, 2023 9:52 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression test: Fix FAIL of slp-reduc-4.c for RVV
On 10/9/23 07:41, Juzhe-Zhong wrote:
> RV
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, October 9, 2023 9:53 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression test: Fix FAIL of slp-12a.c
On 10/9/23 07:35, Juzhe-Zhong wrote:
> This case is v
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, October 9, 2023 9:53 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression tests: Fix FAIL of pr97832* for RVV
On 10/9/23 07:15, Juzhe-Zhong wrote:
> These
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, October 9, 2023 10:28 PM
To: juzhe.zhong
Cc: gcc-patches@gcc.gnu.org; rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV
On 10/9/23 08:21, juzhe.zhong wrote:
> Do yo
Hi François,
> On 7 Oct 2023, at 20:32, François Dumont wrote:
>
> I've been told that previous patch generated with 'git diff -b' was not
> applying properly so here is the same patch again with a simple 'git diff'.
Thanks, that did fix it - There are some training whitespaces in the config
Robin Dapp writes:
>> It'd be good to expand on this comment a bit. What kind of COND are you
>> anticipating? A COND with the neutral op as the else value, so that the
>> PLUS_EXPR (or whatever) can remain unconditional? If so, it would be
>> good to sketch briefly how that happens, and why it
On Mon, Oct 09, 2023 at 12:55:02PM +0200, Jakub Jelinek wrote:
> This makes wide_int unusable in GC structures, so for dwarf2out
> which was the only place which needed it there is a new rwide_int type
> (restricted wide_int) which supports only up to RWIDE_INT_MAX_ELTS limbs
> inline and is trivia
These cases won't check SLP for load_lanes support target.
Add vectorization check for situations.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr97832-2.c: Add vectorization check.
* gcc.dg/vect/pr97832-3.c: Ditto.
* gcc.dg/vect/pr97832-4.c: Ditto.
---
gcc/testsuite/gcc.dg/v
Hi David,
On 09.10.23 16:08, David Malcolm wrote:
On Mon, 2023-10-09 at 12:09 +0200, Tobias Burnus wrote:
The following works:
(A) Using "kind == boundaries::kind::HARD" - i.e. adding
"boundaries::"
(B) Renaming the parameter name "kind" to something else - like "k"
as used
in the other f
On Sun, Oct 8, 2023 at 10:30 PM HAO CHEN GUI wrote:
> Hi,
> This patch enables vector mode for memory equality compare by adding
> a new expand cbranchv16qi4 and implementing it. Also the corresponding
> CC reg and compare code is set in rs6000_generate_compare. With the
> patch, 16-byte equali
> On 9 Oct 2023, at 15:42, Iain Sandoe wrote:
>> On 7 Oct 2023, at 20:32, François Dumont wrote:
>>
>> I've been told that previous patch generated with 'git diff -b' was not
>> applying properly so here is the same patch again with a simple 'git diff'.
>
> Thanks, that did fix it - There
I added this routine for Aldy when he thought we were going to have to
add explicit versions for unordered relations.
It seems that with accurate tracking of NANs, we do not need the
explicit versions in the oracle, so we will not need this identity
routine to pick the appropriate version of V
When ranger propagates ranges in the on-entry cache, it also check for
equivalences and incorporates the equivalence into the range for a name
if it is known.
With floating point values, the equivalence that is generated by
comparison must also take into account that if the equivalence contain
On 09/10/2023 16:42, Iain Sandoe wrote:
Hi François,
On 7 Oct 2023, at 20:32, François Dumont wrote:
I've been told that previous patch generated with 'git diff -b' was not
applying properly so here is the same patch again with a simple 'git diff'.
Thanks, that did fix it - There are some
On Mon, Oct 09, 2023 at 03:44:10PM +0200, Jakub Jelinek wrote:
> Thanks, just quick answers, will work on patch adjustments after trying to
> get rid of rwide_int (seems dwarf2out has very limited needs from it, just
> some routine to construct it in GCed memory (and never change afterwards)
> from
On Mon, 2023-10-09 at 17:01 +0200, Tobias Burnus wrote:
> Hi David,
>
> On 09.10.23 16:08, David Malcolm wrote:
> > On Mon, 2023-10-09 at 12:09 +0200, Tobias Burnus wrote:
> > > The following works:
> > > (A) Using "kind == boundaries::kind::HARD" - i.e. adding
> > > "boundaries::"
> > > (B) Renam
On 10/9/23 00:18, Jin Ma wrote:
+;; The conversion of DF to BF needs to be done with SF if there is a
+;; chance to generate at least one instruction, otherwise just using
+;; libfunc __truncdfbf2.
+(define_expand "truncdfbf2"
+ [(set (match_operand:BF 0 "register_operand" "=f")
+
> Doesn't this need to be updated to avoid multi-dimensional arrays in awk
> and rebased?
Oh, yeah, I should update that, it's post before that issue reported,
let me send v2 sn :P
On 10/9/23 06:03, Nathaniel Shead wrote:
Bootstrapped and regtested on x86_64-pc-linux-gnu with
GXX_TESTSUITE_STDS=98,11,14,17,20,23,26,impcx.
-- >8 --
This patch improves the errors given when casting from void* in C++26 to
include the expected type if the type of the pointed-to object was
not
Hi Christoph,
On 10/9/23 12:06, Patrick O'Neill wrote:
Hi Vineet,
We're seeing a regression on all riscv targets after this patch:|
FAIL: gcc.target/riscv/xtheadcondmov-indirect.c -O2
check-function-bodies ConNmv_imm_imm_reg||
FAIL: gcc.target/riscv/xtheadcondmov-indirect.c -O3 -g
check-fun
On 10/9/23 14:36, Vineet Gupta wrote:
Hi Christoph,
On 10/9/23 12:06, Patrick O'Neill wrote:
Hi Vineet,
We're seeing a regression on all riscv targets after this patch:|
FAIL: gcc.target/riscv/xtheadcondmov-indirect.c -O2
check-function-bodies ConNmv_imm_imm_reg||
FAIL: gcc.target/riscv/
On 10/8/23 21:03, Nathaniel Shead wrote:
Ping for https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631203.html
+ && (TREE_CODE (t) == MODIFY_EXPR
+ /* Also check if initializations have implicit change of active
+member earlier up the access chain. */
On Mon, Oct 9, 2023 at 10:36 PM Vineet Gupta wrote:
>
> Hi Christoph,
>
> On 10/9/23 12:06, Patrick O'Neill wrote:
> >
> > Hi Vineet,
> >
> > We're seeing a regression on all riscv targets after this patch:|
> >
> > FAIL: gcc.target/riscv/xtheadcondmov-indirect.c -O2
> > check-function-bodies ConN
On 10/9/23 13:46, Christoph Müllner wrote:
Given that this causes repeated issues, I think that a fall-back to
counting occurrences is the right thing to do. I can do that if that's ok.
Thanks Christoph.
-Vineet
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