From: Pan Li
This patch would like to fix one bug to align below items of spec.
1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.
When mode switching the function entry and exit, it will take DYN as
the frm mode.
Signed-off-by:
LGTM, thanks :)
On Wed, Jul 5, 2023 at 3:03 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch would like to fix one bug to align below items of spec.
>
> 1. By default, the RVV floating-point will take dyn mode.
> 2. DYN is invalid in FRM register for RVV floating-point.
>
> When
> LGTM, thanks :)
just a moment please, I still wanted to reply ;)
Regards
Robin
On Wed, Jul 5, 2023 at 3:12 PM Robin Dapp via Gcc-patches
wrote:
>
> > LGTM, thanks :)
>
> just a moment please, I still wanted to reply ;)
Sure :)
>
> Regards
> Robin
>
Thanks Robin, it passed all tests of riscv.exp and rvv.exp from my side. Could
you please help to double confirm the issue you meet is resolved or not?
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, July 5, 2023 3:11 PM
To: Kito Cheng ; Li, Pan2
Cc: rdapp@gmail.com; gcc-
LGTM
On Wed, Jul 5, 2023 at 10:08 AM juzhe.zh...@rivai.ai
wrote:
>
> LGTM.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-07-04 20:26
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v1] RISC-V: Use FRM_DYN when add the
Richard Biener via Gcc-patches writes:
> The following adjusts the tree.def documentation about VEC_PERM_EXPR
> which wasn't adjusted when the restrictions of permutes with constant
> mask were relaxed.
I was going to complain about having two copies of the documentation,
but then I realised that
On Wed, 5 Jul 2023, Richard Sandiford wrote:
> Richard Biener via Gcc-patches writes:
> > The following adjusts the tree.def documentation about VEC_PERM_EXPR
> > which wasn't adjusted when the restrictions of permutes with constant
> > mask were relaxed.
>
> I was going to complain about having
Hi!
On 2022-10-18T18:14:54-0400, Lewis Hyatt via Gcc-patches
wrote:
> [...] add a new
> GTY option "string_length" so that gt_pch_note_object can be informed the
> actual length it ought to use, [...]
> --- a/gcc/doc/gty.texi
> +++ b/gcc/doc/gty.texi
> @@ -196,7 +196,26 @@ static GTY((length("r
The test installed by "x86: make VPTERNLOG* usable on less than 512-bit
operands with just AVX512F" won't succeed on 32-bit, for floating point
operations being done there (by default) without using SIMD insns.
gcc/testsuite/
* gcc.target/i386/avx512f-copysign.c: Suppress for 32-bit.
---
C
Hi!
On 2023-07-04T15:56:23-0400, Lewis Hyatt via Gcc-patches
wrote:
> On Tue, Jul 4, 2023 at 11:50 AM Thomas Schwinge
> wrote:
>> I came across this one here on my way working through another (somewhat
>> related) GTY issue. I generally do understand the issue here, but do
>> have a question
1: correct / simplify @vec_extract_hi_ and vec_extract_hi_v32qi
2: slightly correct / simplify *vec_extractv2ti
Jan
The middle alternative each was unusable without enabling AVX512DQ (in
addition to AVX512VL), which is entirely unrelated here. The last
alternative is usable with AVX512VL only (due to type restrictions on
what may be put in the upper 16 YMM registers), and hence is pointlessly
forcing 512-bit mod
V2TImode values cannot appear in the upper 16 YMM registers without
AVX512VL being enabled. Therefore forcing 512-bit mode (also not
reflected in the "mode" attribute) is pointless.
gcc/
* config/i386/sse.md (*vec_extractv2ti): Drop g modifiers.
--- a/gcc/config/i386/sse.md
+++ b/gcc/con
Hi Pan,
yes, the problem is fixed for me. Still some comments ;) Sorry
it took a while.
> 1. By default, the RVV floating-point will take dyn mode.
> 2. DYN is invalid in FRM register for RVV floating-point.
>
> When mode switching the function entry and exit, it will take DYN as
> the frm mod
gcc.dg/vect/slp-perm-9.c is reported to FAIL with -march=cascadelake
now which is because we now vectorize the epilogue with V2HImode
vectors after the recent change to not scrap too large vector
epilogues during transform but during analysis time.
The following adjusts the testcase to always use
On Tue, 4 Jul 2023, Robin Dapp wrote:
> Hi Richard,
>
> changed the patch according to your comments and I agree that
> it is more readable that way. I hope using lhs as target for
> the extract directly is possible the way I did it. Richard's
> patch for aarch64 is already, therefore testsuite
Hi!
On 2014-11-23T23:11:36-0500, tsaund...@mozilla.com wrote:
> gcc/
>
> * plugin.c, plugin.def, ggc.h, ggc-common.c, gengtype.h, gengtype.c,
> gengtype-state.c, gengtype-parse.c, gentype-lex.l, gcc-plugin.h,
> doc/plugins.texi, doc/gty.texi: Remove support for if_marked and
>
Zfinx has provide fcsr like F, so rouding mode should use fcsr instead
of `soft` fenv.
libgcc/ChangeLog:
* config/riscv/sfp-machine.h (FP_INIT_ROUNDMODE): Check zfinx.
(FP_HANDLE_EXCEPTIONS): Ditto.
---
libgcc/config/riscv/sfp-machine.h | 2 +-
1 file changed, 1 insertion(+), 1 d
>> + _4 = vD.2208;
>> + _5 = .VEC_EXTRACT (_4, idx_2(D));
>> + _3 = _5; */
>
> I think you are doing
>
> _3 = .VEC_EXTRACT (_4, idx_2(D));
>
> and avoiding the SSA name copy correctly. Can you double-check?
>
> OK with the comment adjusted.
Argh, yes, thanks.
Regards
Hi!
On 2014-11-23T23:11:36-0500, tsaund...@mozilla.com wrote:
> gcc/
>
> * plugin.c, plugin.def, ggc.h, ggc-common.c, gengtype.h, gengtype.c,
> gengtype-state.c, gengtype-parse.c, gentype-lex.l, gcc-plugin.h,
> doc/plugins.texi, doc/gty.texi: Remove support for if_marked and
>
On Wed, Jul 5, 2023 at 9:51 AM Thomas Schwinge wrote:
>
> Hi!
>
> On 2022-10-18T18:14:54-0400, Lewis Hyatt via Gcc-patches
> wrote:
> > [...] add a new
> > GTY option "string_length" so that gt_pch_note_object can be informed the
> > actual length it ought to use, [...]
>
> > --- a/gcc/doc/gty.t
On Wed, Jul 5, 2023 at 9:57 AM Thomas Schwinge wrote:
>
> Hi!
>
> On 2023-07-04T15:56:23-0400, Lewis Hyatt via Gcc-patches
> wrote:
> > On Tue, Jul 4, 2023 at 11:50 AM Thomas Schwinge
> > wrote:
> >> I came across this one here on my way working through another (somewhat
> >> related) GTY issu
On Wed, Jul 5, 2023 at 4:00 PM Jan Beulich via Gcc-patches
wrote:
>
> The middle alternative each was unusable without enabling AVX512DQ (in
> addition to AVX512VL), which is entirely unrelated here. The last
> alternative is usable with AVX512VL only (due to type restrictions on
> what may be put
On Wed, Jul 5, 2023 at 4:01 PM Jan Beulich via Gcc-patches
wrote:
>
> V2TImode values cannot appear in the upper 16 YMM registers without
> AVX512VL being enabled. Therefore forcing 512-bit mode (also not
> reflected in the "mode" attribute) is pointless.
Please set isa attribute for alternative 1
Hi,
If a loop is unrolled during vectorization (i.e. suggested_unroll_factor > 1),
the VFs of both main and epilog loop are enlarged. The epilog vect loop is
specific for a loop with small iteration counts, so a large VF may hurt
performance.
This patch unscales the main loop VF by suggested_unr
On 05.07.2023 10:40, Hongtao Liu wrote:
> On Wed, Jul 5, 2023 at 4:00 PM Jan Beulich via Gcc-patches
> wrote:
>>
>> The middle alternative each was unusable without enabling AVX512DQ (in
>> addition to AVX512VL), which is entirely unrelated here. The last
>> alternative is usable with AVX512VL onl
On 05.07.2023 10:47, Hongtao Liu wrote:
> On Wed, Jul 5, 2023 at 4:01 PM Jan Beulich via Gcc-patches
> wrote:
>>
>> V2TImode values cannot appear in the upper 16 YMM registers without
>> AVX512VL being enabled. Therefore forcing 512-bit mode (also not
>> reflected in the "mode" attribute) is point
Hi,
this patch enables a variable index for vec_set and
adjusts/cleans up the tests.
Regards
Robin
gcc/ChangeLog:
* config/riscv/autovec.md: Allow register index operand.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Adjust
test.
Hi,
this patch adds a gen_lowpart in the vec_extract expander so it properly
works with a variable index and adds tests.
Regards
Robin
gcc/ChangeLog:
* config/riscv/autovec.md: Add gen_lowpart.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c:
Thanks Robin for reviewing, will address the comments with PATCH v5 later as I
am in the middle of sth.
> In riscv_mode_after the default mode is again FRM_MODE_NONE. Wouldn't
> we also want FRM_MODE_DYN here?
All of FRM should be aligned to DYN in PATCH v4, will double check about it
when prep
On Wed, Jul 5, 2023 at 4:55 PM Jan Beulich wrote:
>
> On 05.07.2023 10:40, Hongtao Liu wrote:
> > On Wed, Jul 5, 2023 at 4:00 PM Jan Beulich via Gcc-patches
> > wrote:
> >>
> >> The middle alternative each was unusable without enabling AVX512DQ (in
> >> addition to AVX512VL), which is entirely un
On Wed, Jul 5, 2023 at 5:03 PM Jan Beulich wrote:
>
> On 05.07.2023 10:47, Hongtao Liu wrote:
> > On Wed, Jul 5, 2023 at 4:01 PM Jan Beulich via Gcc-patches
> > wrote:
> >>
> >> V2TImode values cannot appear in the upper 16 YMM registers without
> >> AVX512VL being enabled. Therefore forcing 512-
Hi!
On 2012-08-10T11:06:46-0400, Diego Novillo wrote:
> * gengtype-lex.l (USER_GTY): Add pattern for "user".
> * gengtype-parse.c (option): Handle USER_GTY.
> (opts_have): New.
> (type): Call it.
> If the keyword 'user' is used, do not walk the fields
On Wed, Jul 5, 2023 at 6:22 PM Hongtao Liu wrote:
>
> On Wed, Jul 5, 2023 at 5:03 PM Jan Beulich wrote:
> >
> > On 05.07.2023 10:47, Hongtao Liu wrote:
> > > On Wed, Jul 5, 2023 at 4:01 PM Jan Beulich via Gcc-patches
> > > wrote:
> > >>
> > >> V2TImode values cannot appear in the upper 16 YMM re
Passed both the bootstrap and regression tests in X86.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of juzhe.zh...@rivai.ai
Sent: Tuesday, July 4, 2023 9:10 PM
To: gcc-patches@gcc.gnu.org
Cc: richard.sandif...@arm.com; rguent...@suse.de; Ju-Zhe Zhong
Subject: [PATCH V5] VECT: Ap
Thank you for using intel's machines test it for me.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-07-05 19:15
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
CC: richard.sandif...@arm.com; rguent...@suse.de
Subject: RE: [PATCH V5] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into
vector
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
while generating vector pairs of load & store instruction, the src address
was treated as an altivec type and that type of address is invalid for
lxvp and stxvp insns. The solution for this is to avoid altivec
A question: is vld/vst guaranteed to be atomic if the accessed address
is aligned? If true we can use them to implement lock-free 128-bit
atomic load and store. See https://gcc.gnu.org/bugzilla/PR104688 for
the background, and some people really hate using a lock for atomics.
On Fri, 2023-06-30
Hi,
Juzhe noticed that several floating-point conversion tests
FAIL on 32 bit. This is due to the autovect FP narrowing patterns
using a truncate instead of a float_truncate which results in
a combine ICE. It would try to e.g. simplify a unary operation by
simplify_const_unary_operation which ob
LGTM. Thanks for fixing this.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-05 21:00
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Change truncate to float_truncate in narrowing
Hi,
Juzhe noticed that several floating-poin
On Tue, 4 Jul 2023, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> Hi, Richard and Richi.
>
> Address comments from Richi.
>
> Make gs_info.ifn = LEN_MASK_GATHER_LOAD/LEN_MASK_SCATTER_STORE.
>
> I have fully tested these 4 format:
>
> length = vf is a dummpy length,
> mask = {-1,-1, ..
On Tue, 4 Jul 2023, Richard Sandiford wrote:
> Richard Biener writes:
> > On Thu, 29 Jun 2023, Richard Biener wrote:
> >
> >> On Thu, 29 Jun 2023, Richard Sandiford wrote:
> >>
> >> > Richard Biener writes:
> >> > > With applying loop masking to epilogues on x86_64 AVX512 we see
> >> > > some s
Committed, thanks Richard.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Richard Biener via Gcc-patches
Sent: Wednesday, July 5, 2023 9:21 PM
To: Ju-Zhe Zhong
Cc: gcc-patches@gcc.gnu.org; richard.sandif...@arm.com
Subject: Re: [PATCH V5] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER
Adds a simplification for (~X | Y) ^ X to be folded into ~(X & Y).
Tested successfully on x86_64 and x86 targets.
PR middle-end/109986
gcc/ChangeLog:
* match.pd ((~X | Y) ^ X -> ~(X & Y)): New simplification.
gcc/testsuite/ChangeLog:
* gcc.c-
Lgtm
juzhe.zh...@rivai.ai 於 2023年7月5日 週三，21:04寫道：
> LGTM. Thanks for fixing this.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Robin Dapp
> Date: 2023-07-05 21:00
> To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
> CC: rdapp.gcc
> Subject: [PATCH] RISC-V: Change truncate to float
Ping?
On Tue, Jun 13 2023 at 09:05:29 AM -04:00:00, Hamza Mahfooz
wrote:
Resolves:
PR c/65213 - Extend -Wmissing-declarations to variables [i.e. add
-Wmissing-variable-declarations]
gcc/c-family/ChangeLog:
PR c/65213
* c.opt (-Wmissing-variable-declarations): New option.
gcc
Richard Biener writes:
> On Tue, 4 Jul 2023, Richard Sandiford wrote:
>
>> Richard Biener writes:
>> > On Thu, 29 Jun 2023, Richard Biener wrote:
>> >
>> >> On Thu, 29 Jun 2023, Richard Sandiford wrote:
>> >>
>> >> > Richard Biener writes:
>> >> > > With applying loop masking to epilogues on x8
On 7/5/23 03:13, Robin Dapp wrote:
Hi,
this patch adds a gen_lowpart in the vec_extract expander so it properly
works with a variable index and adds tests.
Regards
Robin
gcc/ChangeLog:
* config/riscv/autovec.md: Add gen_lowpart.
gcc/testsuite/ChangeLog:
* gcc.target/ris
On 7/5/23 02:11, Kito Cheng wrote:
Zfinx has provide fcsr like F, so rouding mode should use fcsr instead
of `soft` fenv.
libgcc/ChangeLog:
* config/riscv/sfp-machine.h (FP_INIT_ROUNDMODE): Check zfinx.
(FP_HANDLE_EXCEPTIONS): Ditto.
OK
jeff
On 7/5/23 03:12, Robin Dapp wrote:
Hi,
this patch enables a variable index for vec_set and
adjusts/cleans up the tests.
Regards
Robin
gcc/ChangeLog:
* config/riscv/autovec.md: Allow register index operand.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlma
Committed, thanks Juzhe and Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, July 5, 2023 3:16 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; Robin
Dapp ; jeffreyalaw ; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode opera
Le 04/07/2023 à 21:37, Mikael Morin a écrit :
Le 04/07/2023 à 21:00, Harald Anlauf a écrit :
Hi Mikael, all,
I think I've found it: there is a call to gfc_conv_class_to_class
that - according to a comment - does a repackaging to a class array.
Deferring that repackaging along with the deallocat
Also change some internal variables to bool.
gcc/ChangeLog:
* sched-int.h (struct haifa_sched_info): Change can_schedule_ready_p,
scehdule_more_p and contributes_to_priority indirect frunction
type from int to bool.
(no_real_insns_p): Change return type from int to bool.
(cont
the first parameter of fwrite should be the const char* __s which want write to
FILE *__file,
rather than the FILE *__file write to the FILE *__file.
0001-Fix-fwrite-error-parameter.txt
Description: Binary data
the first parameter of fwrite should be the const char* __s which want write to
FILE *__file,
rather than the FILE *__file write to the FILE *__file.
0001-Fix-fwrite-error-parameter.txt
Description: Binary data
the first parameter of fwrite should be the const char* __s which want write to
FILE *__file,
rather than the FILE *__file write to the FILE *__file.
0001-Fix-fwrite-error-parameter.txt
Description: Binary data
On Wed, 5 Jul 2023 at 16:54, shuaitq via Libstdc++
wrote:
>
> the first parameter of fwrite should be the const char* __s which want write
> to FILE *__file,
> rather than the FILE *__file write to the FILE *__file.
Thank you. The patch is correct and small enough to not require a
copyright assi
Thank you Andre for reviewing! I'll attach the updated version of the
patch to the third review email (your final one thus far ;)
On 22/06/2023 16:54, Andre Vieira (lists) wrote:
Some comments below, all quite minor. I'll continue to review
tomorrow, I need a fresher brain for
arm_mve_check_df
Hi!
On 2023-07-05T10:16:09+0200, I wrote:
> On 2014-11-23T23:11:36-0500, tsaund...@mozilla.com wrote:
>> gcc/
>>
>> * plugin.c, plugin.def, ggc.h, ggc-common.c, gengtype.h, gengtype.c,
>> gengtype-state.c, gengtype-parse.c, gentype-lex.l, gcc-plugin.h,
>> doc/plugins.texi, doc/gt
On 23/06/2023 11:23, Andre Vieira (lists) wrote:
+ if (insn != arm_mve_get_loop_vctp (body))
+ {
probably a good idea to invert the condition here and return false,
helps reducing the indenting in this function.
Done, thanks
+ /* Starting from the current insn, scan backwards th
Hi!
OK to push the attached
"GGC, GTY: Tighten up a few things re 'reorder' option and strings"?
Grüße
Thomas
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas
Heurung, Fran
Gerald suggested I update this. Pushed to trunk.
-- >8 --
gcc/ChangeLog:
* doc/contrib.texi (Contributors): Update my entry.
---
gcc/doc/contrib.texi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi
index 758805dc5db..fa55
Hi!
My original motivation for the following exercise what that, for example,
for: 'const unsigned char * GTY((atomic)) mode_table', we currently run
into 'const' mismatches, 'error: invalid conversion':
[...]
gtype-desc.cc: In function 'void gt_pch_nx_lto_file_decl_data(void*)':
gtyp
So the problem is vector generic decided to do comparisons in signed-boolean:32
types but the rest of the middle-end was not ready for that. Since we are
building
the comparison which will feed into a cond_expr here, using boolean_type_node is
better and also correct. The rest of the compiler thin
Hi Christophe,
> -Original Message-
> From: Christophe Lyon
> Sent: Monday, June 26, 2023 4:03 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Sandiford
> Cc: Christophe Lyon
> Subject: [PATCH] arm: Fix MVE intrinsics support with LTO (PR target/110268)
>
> After the recen
ping
From: Wilco Dijkstra
Sent: 02 June 2023 18:28
To: GCC Patches
Cc: Richard Sandiford ; Kyrylo Tkachov
Subject: [PATCH] libatomic: Enable lock-free 128-bit atomics on AArch64
[PR110061]
Enable lock-free 128-bit atomics on AArch64. This is backwards compatible with
existing binaries, g
Thanks a lot.
Hao Liu OS via Gcc-patches writes:
> Hi,
>
> If a loop is unrolled during vectorization (i.e. suggested_unroll_factor > 1),
> the VFs of both main and epilog loop are enlarged. The epilog vect loop is
> specific for a loop with small iteration counts, so a large VF may hurt
> performance.
>
> Thi
Hi Mikael,
Am 05.07.23 um 16:54 schrieb Mikael Morin:
Here is an example, admittedly artificial. Fails with the above change,
but fails with master as well.
program p
implicit none
type t
integer :: i
end type t
type u
class(t), allocatable :: ta(:)
end type u
type(
On Tue, 2023-07-04 at 18:25 +0200, priour...@gmail.com wrote:
> From: benjamin priour
>
> Script contrib/check_GNU_style.sh complains about there being a space
> before a left square bracket ("operator new []").
> Though, it is actually within a literal string, and the space
> is required to co
There is no warning and perf /uk succeeds when kptr_restrict is set to 1 and
perf_event_paranoid set to 2. However, create_gcov may fail since it won't be
able to understand kernel addresses and it requires at least 95% of events to
be successfully mapped.
If I set both kptr_restrict and perf_e
Running
$ make check-c++ RUNTESTFLAGS='--target_board=unix\{-gdwarf-5,-gdwarf-4\}
dwarf2.exp=utf-1.C'
shows
FAIL: g++.dg/debug/dwarf2/utf-1.C -std=gnu++20 scan-assembler-times
DW_AT_encoding \\(0x10\\) 3
because with -gdwarf-4 the output is:
.byte 0x10# DW_AT_encoding
but with -gdwarf
Hi David,
On 05/07/2023 22:59, David Malcolm wrote:
diff --git a/gcc/analyzer/kf-lang-cp.cc b/gcc/analyzer/kf-lang-cp.cc
index 393b4f25e79..258d92919d7 100644
--- a/gcc/analyzer/kf-lang-cp.cc
+++ b/gcc/analyzer/kf-lang-cp.cc
@@ -35,6 +35,34 @@ along with GCC; see the file COPYING3. If not see
Comment added to each file.
Tested x86_64-linux. Pushed to trunk.
On Mon, Jul 3, 2023 at 4:16 PM Jonathan Wakely wrote:
> On Mon, 3 Jul 2023 at 23:14, Thomas Rodgers via Libstdc++
> wrote:
> >
> > This testcase is causing some timeout issues. This patch splits the
> > testcase up by individual
This is a set of 5 patches which cleans up GORIs compute_operand routines.
This is the mechanism GORI uses to calculate ranges from the bottom of
the routine back thru definitions in the block to the name that is
requested.
Currently, compute_operand_range() is called on a stmt, and it divide
This patch simplifies compute_operand1_and_operand2() such that it only
calls each routine one. This will simplify the next couple of patches.
It also allows moves the determination that op1 and op2 have an
interdependence to compute_operand_range().
Bootstraps on x86_64-pc-linux-gnu with
now operand1 alone is resolved, and returned as the result. much
cleaner, and removes it from the recursion stack.
compute_operand_range() will decide if further evaluation is required.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 912b5ac49677160aada7a2d86227
now operand2 alone is resolved, and returned as the result. much
cleaner, and removes it from the recursion stack.
compute_operand_range() will decide if further evaluation is required.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
From 298952bcf05d298892e99adba1f4a
This simply tweaks cmpute_operand_range a little so the recursion is a
tail call.
With this, the patchset produces a modest speedup of 0.2% in VRP and
0.4% in threading. It will also have a much smaller stack profile.
Bootstraps on x86_64-pc-linux-gnu with no regressions. Pushed.
Andrew
Don't assume that stack slots can only be accessed by stack or frame
registers. Also check memory accesses from registers defined by
stack or frame registers.
gcc/
PR target/109780
* config/i386/i386.cc (ix86_set_with_register_source): New.
(ix86_find_all_stack_access): L
Thanks, this is the updated patch I'm going to check in.
Uros Bizjak 于2023年7月4日周二 16:57写道：
>
> On Tue, Jul 4, 2023 at 10:32 AM Hongyu Wang wrote:
> >
> > > In a follow-up patch, can you please document inlining rules involving
> > > -march and -mtune to "x86 Function Attributes" section? Current
For testcase
void __cond_swap(double* __x, double* __y) {
bool __r = (*__x < *__y);
auto __tmp = __r ? *__x : *__y;
*__y = __r ? *__y : *__x;
*__x = __tmp;
}
GCC-14 with -O2 and -march=x86-64 options generates the following code:
__cond_swap(double*, double*):
movsd xmm1, QWORD
They should have same cost as vector mode since both generate
pand/pandn/pxor/por instruction.
Bootstrapped and regtested on x86_64-pc-linu-gnu{-m32,}.
Ok for trunk?
gcc/ChangeLog:
* config/i386/i386.cc (ix86_rtx_costs): Adjust rtx_cost for
DF/SFmode AND/IOR/XOR/ANDN operations.
We have ix86_expand_sse_fp_minmax to detect min/max sematics, but
it requires rtx_equal_p for cmp_op0/cmp_op1 and if_true/if_false, for
the testcase in the PR, there's an extra move from cmp_op0 to if_true,
and it failed ix86_expand_sse_fp_minmax.
This patch adds pre_reload splitter to detect the
From: Pan Li
This patch would like to fix one bug to align below items of spec.
RVV floating-point instructions always (implicitly) use the dynamic
rounding mode. This implies that rounding is performed according to the
rounding mode set in the FRM register. The FRM register itself
only holds
On Thu, Jul 6, 2023 at 3:14 AM liuhongt wrote:
>
> For testcase
>
> void __cond_swap(double* __x, double* __y) {
> bool __r = (*__x < *__y);
> auto __tmp = __r ? *__x : *__y;
> *__y = __r ? *__y : *__x;
> *__x = __tmp;
> }
>
> GCC-14 with -O2 and -march=x86-64 options generates the followi
On Thu, Jul 6, 2023 at 3:20 AM liuhongt wrote:
>
> They should have same cost as vector mode since both generate
> pand/pandn/pxor/por instruction.
>
> Bootstrapped and regtested on x86_64-pc-linu-gnu{-m32,}.
> Ok for trunk?
>
> gcc/ChangeLog:
>
> * config/i386/i386.cc (ix86_rtx_costs): Ad
On Wed, Jul 5, 2023 at 12:21 PM Thomas Schwinge wrote:
>
> Hi!
>
> On 2012-08-10T11:06:46-0400, Diego Novillo wrote:
> > * gengtype-lex.l (USER_GTY): Add pattern for "user".
> > * gengtype-parse.c (option): Handle USER_GTY.
> > (opts_have): New.
> > (type): Cal
On Wed, Jul 5, 2023 at 6:13 PM Thomas Schwinge wrote:
>
> Hi!
>
> On 2023-07-05T10:16:09+0200, I wrote:
> > On 2014-11-23T23:11:36-0500, tsaund...@mozilla.com wrote:
> >> gcc/
> >>
> >> * plugin.c, plugin.def, ggc.h, ggc-common.c, gengtype.h, gengtype.c,
> >> gengtype-state.c, gengtype
On Wed, Jul 5, 2023 at 6:16 PM Thomas Schwinge wrote:
>
> Hi!
>
> OK to push the attached
> "GGC, GTY: Tighten up a few things re 'reorder' option and strings"?
OK.
>
> Grüße
> Thomas
>
>
> -
> Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634
> Münc
On Wed, Jul 5, 2023 at 6:25 PM Thomas Schwinge wrote:
>
> Hi!
>
> My original motivation for the following exercise what that, for example,
> for: 'const unsigned char * GTY((atomic)) mode_table', we currently run
> into 'const' mismatches, 'error: invalid conversion':
>
> [...]
> gtype-de
On Wed, Jul 5, 2023 at 7:02 PM Andrew Pinski via Gcc-patches
wrote:
>
> So the problem is vector generic decided to do comparisons in
> signed-boolean:32
> types but the rest of the middle-end was not ready for that. Since we are
> building
> the comparison which will feed into a cond_expr here,
From: Ju-Zhe Zhong
Hi, Richi.
Sorry for making mistake on LEN_MASK_GATHER_LOAD/LEN_MASK_SCATTER_STORE
with SELECT_VL loop control.
Consider this following case:
#define TEST_LOOP(DATA_TYPE, BITS) \
void __attribute__ ((noinline, noclone))
On Thu, Jul 6, 2023 at 3:20 AM liuhongt wrote:
>
> We have ix86_expand_sse_fp_minmax to detect min/max sematics, but
> it requires rtx_equal_p for cmp_op0/cmp_op1 and if_true/if_false, for
> the testcase in the PR, there's an extra move from cmp_op0 to if_true,
> and it failed ix86_expand_sse_fp_m
On Wed, Jul 5, 2023 at 11:15 PM Eugene Rozenfeld
wrote:
>
> There is no warning and perf /uk succeeds when kptr_restrict is set to 1 and
> perf_event_paranoid set to 2. However, create_gcov may fail since it won't be
> able to understand kernel addresses and it requires at least 95% of events to
Committed to trunk, and plan to back port to GCC 13 branch 1 week later :)
On Wed, Jul 5, 2023 at 10:15 PM Jeff Law wrote:
>
>
>
> On 7/5/23 02:11, Kito Cheng wrote:
> > Zfinx has provide fcsr like F, so rouding mode should use fcsr instead
> > of `soft` fenv.
> >
> > libgcc/ChangeLog:
> >
> >
On Thu, Jul 6, 2023 at 1:28 AM H.J. Lu via Gcc-patches
wrote:
>
> Don't assume that stack slots can only be accessed by stack or frame
> registers. Also check memory accesses from registers defined by
> stack or frame registers.
>
> gcc/
>
> PR target/109780
> * config/i386/i386.c
Hi,
This is a follow-up patch for
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/623525.html
that updates document about x86 inlining rules.
Ok for trunk?
gcc/ChangeLog:
* doc/extend.texi: Move x86 inlining rule to a new subsubsection
and add description for inling of funct
Hi all,
This patch is to add initial support for Granite Rapids D for GCC.
The link of related information is listed below:
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Also, the patch of removing AMX-COMPLEX fro
1 - 100 of 105 matches
Mail list logo
