[PATCH] PoC: add -Wunused-result=strict

As requested in , this is a proof-of-concept patch to change -Wunused-result to not warn about return values explicitly discarded by casting to void, and add -Wunused-result=strict for the current behavior (warn even on void casts). The core b

[COMMITTED] Handle NANs in frange::operator== [PR109593]

This patch... commit 10e481b154c5fc63e6ce4b449ce86cecb87a6015 Return true from operator== for two identical ranges containing NAN. removed the check for NANs, which caused us to read from m_min and m_max which are undefined for NANs. gcc/ChangeLog: PR tree-optimization/10

RE: [xstormy16] Add extendhisi2 and zero_extendhisi2 patterns to stormy16.md

On 4/33/23, Jeff Law wrote: > On 4/22/23 14:57, Roger Sayle wrote: > > Whilst there, I also fixed the instruction lengths and formatting of > > the zero_extendqihi2 pattern. Then, mostly for documentation purposes > > as the 'T' constraint isn't yet implemented, I've added a "and Rx,#255" > > alte

[PATCH V2] RISC-V: Optimize fault only first load

From: Juzhe-Zhong V2 patch for: https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zh...@rivai.ai/ which has been reviewed. This patch address Jeff's comment, refine ChangeLog to give more clear information. gcc/ChangeLog: * config/riscv/vector-iterators.

[PATCH] RISC-V: Add function comment for cleanup_insns.

From: Juzhe-Zhong Address Jeff's comment: https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zh...@rivai.ai/ Add a function comment. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pass_vsetvl::pre_vsetvl): Add function comment for cleanup_insns. --- gcc

[PATCH] RISC-V: Eliminate redundant vsetvli for duplicate AVL def

From: Juzhe-Zhong This patch is the V2 patch:https://patchwork.sourceware.org/project/gcc/patch/20230328010124.235703-1-juzhe.zh...@rivai.ai/ Address comments from Jeff. Add comments for all_avail_in_compatible_p and refine comments of codes. gcc/ChangeLog: * config/riscv/riscv-vset

[PATCH V2] RISC-V: Eliminate redundant vsetvli for duplicate AVL def

From: Juzhe-Zhong This patch is the V2 patch:https://patchwork.sourceware.org/project/gcc/patch/20230328010124.235703-1-juzhe.zh...@rivai.ai/ Address comments from Jeff. Add comments for all_avail_in_compatible_p and refine comments of codes. gcc/ChangeLog: * config/riscv/riscv-vset

[PATCH] LoongArch: Enable shrink wrapping

This commit implements the target macros for shrink wrapping of function prologues/epilogues shrink wrapping on LoongArch. Bootstrapped and regtested on loongarch64-linux-gnu. I don't have an access to SPEC CPU so I hope the reviewer can perform a benchmark to see if there is real benefit. gcc/C

[PATCH][committed] aarch64: Add vect_concat with zeroes annotation to addp pattern

Hi all, Similar to others, the addp pattern can be safely annotated with to create the implicit vec_concat-with-zero variants. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. Pushing to trunk. Thanks, Kyrill gcc/ChangeLog: PR target/99195 * config/aa

[PATCH][committed] aarch64: Annotate fcvtn pattern for vec_concat with zeroes

Hi all, Using the define_substs in aarch64-simd.md this is a straightforward annotation to remove a redundant fmov insn. So the codegen goes from: foo_d: fcvtn v0.2s, v0.2d fmovd0, d0 ret to the simple: foo_d: fcvtn v0.2s, v0.2d ret Bootstrapped

[PATCH] Turn on LRA on all targets

This minimal patch enables LRA for all targets. It does not clean up the target code, nor does it do anything to generic code: it just deletes all target definitions of TARGET_LRA_P. There are three kinds of changes: 1) Targets that already always have LRA, but that redefine the hook anyway. Th

Re: [PATCH] Turn on LRA on all targets

On 4/23/23 10:47, Segher Boessenkool wrote: 3) Targets that as of yet never used LRA. Many of those will be fine, but some others will need a little tuning, and a few might need some actual improvements to LRA itself. These are cris, epiphany, fr30, frv, h8300, ia64, iq2000, lm32, m32c, m32r

Re: [PATCH] Turn on LRA on all targets

> On Apr 23, 2023, at 12:47 PM, Segher Boessenkool > wrote: > > This minimal patch enables LRA for all targets. It does not clean up > the target code, nor does it do anything to generic code: it just > deletes all target definitions of TARGET_LRA_P. > > There are three kinds of changes: >

Re: [PATCH] Turn on LRA on all targets

On Sun, 23 Apr 2023, Segher Boessenkool wrote: > 1) Targets that already always have LRA, but that redefine the hook > anyway. These are gcn, pdp11, rx, sparc, vax, and xtensa. Nothing > really changes for these targets with this patch (but later patches > will delete the superfluous hook implem

[r14-162 Regression] FAIL: gcc.dg/guality/pr90716.c -Os -DPREVENT_OPTIMIZATION line 23 j + 1 == 9 on Linux/x86_64

On Linux/x86_64, cda246f8b421ba855a9e5f9d7bfcd0fc49b7bd4b is the first bad commit commit cda246f8b421ba855a9e5f9d7bfcd0fc49b7bd4b Author: Jan Hubicka Date: Sat Apr 22 09:20:45 2023 +0200 Update loop estimate after header duplication caused FAIL: gcc.dg/guality/pr43051-1.c -O2 -DPREVEN

[PATCH] PR rtl-optimization/109476: Use ZERO_EXTEND instead of zeroing a SUBREG.

This patch fixes PR rtl-optimization/109476, which is a code quality regression affecting AVR. The cause is that the lower-subreg pass is sometimes overly aggressive, lowering the LSHIFTRT below: (insn 7 4 8 2 (set (reg:HI 51) (lshiftrt:HI (reg/v:HI 49 [ b ]) (const_int 8 [0x

Re: [PATCH] Turn on LRA on all targets

Hi! On Sun, Apr 23, 2023 at 02:36:05PM -0400, Paul Koning wrote: > > On Apr 23, 2023, at 12:47 PM, Segher Boessenkool > > wrote: > > 1) Targets that already always have LRA, but that redefine the hook > > anyway. These are gcn, pdp11, rx, sparc, vax, and xtensa. Nothing > > really changes for

Re: [PATCH] Turn on LRA on all targets

(You didn't leave me in Cc: on the reply. Maybe you did a reply-to-only-one-person?) On Sun, Apr 23, 2023 at 11:01:05AM -0600, Jeff Law via Gcc-patches wrote: > On 4/23/23 10:47, Segher Boessenkool wrote: > >3) Targets that as of yet never used LRA. Many of those will be fine, > >but some others

Re: [PATCH] Turn on LRA on all targets

On Sun, Apr 23, 2023 at 07:56:56PM +0100, Maciej W. Rozycki wrote: > On Sun, 23 Apr 2023, Segher Boessenkool wrote: > > 1) Targets that already always have LRA, but that redefine the hook > > anyway. These are gcn, pdp11, rx, sparc, vax, and xtensa. Nothing > > really changes for these targets wi

Re: [PATCH] Turn on LRA on all targets

On Sun, Apr 23, 2023 at 6:48 PM Segher Boessenkool wrote: > > This minimal patch enables LRA for all targets. It does not clean up > the target code, nor does it do anything to generic code: it just > deletes all target definitions of TARGET_LRA_P. > > There are three kinds of changes: > > 1) Tar

Re: [Patch, fortran] PRs 105152, 100193, 87946, 103389, 104429 and 82774

Hi Paul, Am 22.04.23 um 10:32 schrieb Paul Richard Thomas via Gcc-patches: Hi All, As usual, I received a string of emails on retargeting for PRs for which I was either responsible or was on the cc list. This time I decided to take a look at them all, in order to reward the tireless efforts of

Re: Re: [GCC14 QUEUE PATCH] RISC-V: Optimize fault only first load

Hi, Jeff. I have fixed patches as you suggested: https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616515.html https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616518.html https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616516.html Can you merge these patches? juzhe.zh...@rivai.ai

Re: Re: [PATCH] RISC-V: Fine tune gather load RA constraint

Adding earlyclobber is to make dest operand do not overlap with source operand. For example: for gather load, vluxei.v v8,(a5),v8 is illegal according to RVV ISA. GCC is using same way as LLVM which is also adding earlyclobber for modeling disabling overlap between dest and source operand. juz

Re: Re: [PATCH] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx codegen

I can push codes yet. Can you push them for me? juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-04-22 04:42 To: juzhe.zhong; gcc-patches CC: kito.cheng; palmer Subject: Re: [PATCH] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx codegen On 3/22/23 06:15, juzhe.zh...@rivai.ai wrote: >

PING^2 [PATCH, rs6000] Splat vector small V2DI constants with ISA 2.07 instructions [PR104124]

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601909.html Thanks Gui Haochen 在 2022/12/14 13:30, HAO CHEN GUI 写道: > Hi, >Gentle ping this: > https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601909.html > > Thanks > Gui Haochen > > 在 2022/9/21 13:1

Ping [PATCH-1, rs6000] Change mode and insn condition for scalar extract exp instruction

Hi, Gently ping this. https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609369.html Thanks Gui Haochen 在 2023/1/4 14:16, HAO CHEN GUI 写道: > Hi, > This patch changes the return type of __builtin_vsx_scalar_extract_exp > from const signed long to const signed int, as the exponent can be pu

Ping [PATCH-2, rs6000] Change mode and insn condition for scalar extract sig instruction

Hi, Gently ping this. https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609370.html Thanks Gui Haochen 在 2023/1/4 14:16, HAO CHEN GUI 写道: > Hi, > This patch changes the return type of __builtin_vsx_scalar_extract_sig > from const signed long to const signed long long, so that it can be c

Re: [PATCH-3, rs6000] Change mode and insn condition for scalar insert exp instruction

Hi, Gently ping this. https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609371.html Thanks Gui Haochen 在 2023/1/4 14:17, HAO CHEN GUI 写道: > Hi, > This patch changes the mode of exponent to GPR in scalar insert exp > pattern, as the exponent can be put into a 32-bit register. Also the > c

Re: [PATCH-4, rs6000] Change ilp32 target check for some scalar-extract-sig and scalar-insert-exp test cases

Hi, Gently ping this. https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609372.html Thanks Gui Haochen 在 2023/1/4 14:17, HAO CHEN GUI 写道: > Hi, > "ilp32" is used in these test cases to make sure test cases only run on a > 32-bit environment. Unfortunately, these cases also run with > "-m

Ping^2 [PATCH, rs6000] Split TImode for logical operations in expand pass [PR100694]

Hi, Gently ping this: https://gcc.gnu.org/pipermail/gcc-patches/2023-February/611550.html Thanks Gui Haochen 在 2023/2/20 10:10, HAO CHEN GUI 写道: > Hi, > Gently ping this: > https://gcc.gnu.org/pipermail/gcc-patches/2023-February/611550.html > > Gui Haochen > Thanks > > 在 2023/2/8 13:08, H

Ping [PATCHv2, rs6000] Merge two vector shift when their sources are the same

Hi Gently ping this. https://gcc.gnu.org/pipermail/gcc-patches/2023-February/612944.html Thanks Gui Haochen 在 2023/2/28 10:31, HAO CHEN GUI 写道: > Hi, > This patch merges two "vsldoi" insns when their sources are the > same. Particularly, it is simplified to be one move if the total > shift is

Re: [PATCH V2] RISC-V: Optimize fault only first load

Committed, thanks :) On Sun, Apr 23, 2023 at 7:18 PM wrote: > > From: Juzhe-Zhong > > V2 patch for: > https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zh...@rivai.ai/ > which has been reviewed. > > This patch address Jeff's comment, refine ChangeLog to give more

Re: [PATCH] RISC-V: Add function comment for cleanup_insns.

Pushed On Sun, Apr 23, 2023 at 7:34 PM wrote: > > From: Juzhe-Zhong > > Address Jeff's comment: > https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zh...@rivai.ai/ > Add a function comment. > > gcc/ChangeLog: > > * config/riscv/riscv-vsetvl.cc (pass_vsetvl

Re: [PATCH V2] RISC-V: Eliminate redundant vsetvli for duplicate AVL def

Committed, thanks :) On Sun, Apr 23, 2023 at 8:19 PM wrote: > > From: Juzhe-Zhong > > This patch is the V2 > patch:https://patchwork.sourceware.org/project/gcc/patch/20230328010124.235703-1-juzhe.zh...@rivai.ai/ > > Address comments from Jeff. Add comments for all_avail_in_compatible_p and > r