I can push codes yet. Can you push them for me?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-22 04:42
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx
codegen
On 3/22/23 06:15, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
>
> Current expansion of vmsge will make RA produce redundant vmv1r.v.
>
> testcase:
> void f1 (void * in, void *out, int32_t x)
> {
> vbool32_t mask = *(vbool32_t*)in;
> asm volatile ("":::"memory");
> vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
> vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4);
> vbool32_t m3 = __riscv_vmsge_vx_i32m1_b32 (v, x, 4);
> vbool32_t m4 = __riscv_vmsge_vx_i32m1_b32_mu (mask, m3, v, x, 4);
> m4 = __riscv_vmsge_vv_i32m1_b32_m (m4, v2, v2, 4);
> __riscv_vsm_v_b32 (out, m4, 4);
> }
>
> Before this patch:
> f1:
> vsetvli a5,zero,e8,mf4,ta,ma
> vlm.v v0,0(a0)
> vsetivli zero,4,e32,m1,ta,mu
> vle32.v v3,0(a0)
> vle32.v v2,0(a0),v0.t
> vmslt.vx v1,v3,a2
> vmnot.m v1,v1
> vmslt.vx v1,v3,a2,v0.t
> vmxor.mm v1,v1,v0
> vmv1r.v v0,v1
> vmsge.vv v2,v2,v2,v0.t
> vsm.v v2,0(a1)
> ret
>
> After this patch:
> f1:
> vsetvli a5,zero,e8,mf4,ta,ma
> vlm.v v0,0(a0)
> vsetivli zero,4,e32,m1,ta,mu
> vle32.v v3,0(a0)
> vle32.v v2,0(a0),v0.t
> vmslt.vx v1,v3,a2
> vmnot.m v1,v1
> vmslt.vx v1,v3,a2,v0.t
> vmxor.mm v0,v1,v0
> vmsge.vv v2,v2,v2,v0.t
> vsm.v v2,0(a1)
> ret
>
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Fix redundant vmv1r.v.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/binop_vx_constraint-150.c: Adapt
> assembly check.
OK. Please push this to the trunk.
jeff
