Tested on x86_64-gnu-linux with -m32 and -m64. It was discussed on
#gfortran IRC and tested with MinGW64 with/by nightstrike.
Committed to mainline.
Tobias
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634
München; Gesellschaft mit beschränkter Haft
On Fri, Jan 27, 2023 at 07:42:39AM +, Richard Biener wrote:
> > BTW, wonder if tree_code_type couldn't be an array of unsigned char
> > elements rather than enum tree_code_class and we'd then cast it
> > to the enum in the macro, that would shrink that array from 1496 bytes
> > to 374. Of cour
Hi!
IPA passes redirect some calls in what it determines to be unreachable code
to builtin_decl_unreachable. But that function returns sometimes
builtin_decl_explicit (BUILT_IN_UNREACHABLE) (which was what GCC 12
and earlier did always), or builtin_decl_explicit (BUILT_IN_TRAP)
(e.g. for -funreac
Hi!
__builtin_va_arg_pack_len as implemented returned int since its introduction
in 2007. The initial documentation didn't mention any return type,
which changed in 2010 in r0-103077-gab940b73bfabe2cec4 during some
documentation formatting cleanups
https://gcc.gnu.org/legacy-ml/gcc-patches/2010-0
Rather obvious fix. Hence, I intent to commit it later as obvious,
unless there are any comments.
Tobias
PS: Thanks goes to Thomas for finding + reporting the issue.
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634
München; Gesellschaft mit beschrä
On Fri, Jan 27, 2023 at 10:19:42AM +0100, Tobias Burnus wrote:
> Rather obvious fix. Hence, I intent to commit it later as obvious,
> unless there are any comments.
Yeah, this is obviously correct.
Have you checked the function if we don't miss other clauses in there
(e.g. compared to the C imple
Hi!
On gcc112 which has glibc 2.17 I've noticed
FAIL: 17_intro/names.cc (test for excess errors)
FAIL: experimental/names.cc (test for excess errors)
These are because glibc < 2.19 used __unused as field member of various structs,
including mcontext_t in sys/ucontext.h on ppc64le.
This was changed
committed, thanks!
On Wed, Jan 4, 2023 at 9:51 PM wrote:
> From: Ju-Zhe Zhong
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: New test.
> * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: New test.
> * gcc.target/riscv/rvv/vsetvl/imm_bb_prop
committed, thanks!
On Wed, Jan 18, 2023 at 10:44 AM wrote:
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Fix incorrect attributes.
>
> ---
> gcc/config/riscv/vector.md | 27 ---
> 1 file changed, 12 insertions(+), 15 deletions(-)
>
> diff
committed, thanks
On Mon, Jan 23, 2023 at 3:39 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
> On 1/17/23 19:50, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > Since LCM will destroy CFG, we are going to reorder the location of
> VSETVL PASS
> > at least before bb
Added more comments and committed, thanks!
On Mon, Jan 23, 2023 at 3:36 AM Jeff Law wrote:
>
>
> On 1/17/23 20:03, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Reorder
> VSETVL PASS.
> It'd be us
committed, thanks!
On Mon, Jan 23, 2023 at 3:32 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
> On 1/17/23 20:06, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-vsetvl.h: Change it into public.
> OK.
> jeff
>
On Fri, 27 Jan 2023, Jakub Jelinek wrote:
> On Fri, Jan 27, 2023 at 07:42:39AM +, Richard Biener wrote:
> > > BTW, wonder if tree_code_type couldn't be an array of unsigned char
> > > elements rather than enum tree_code_class and we'd then cast it
> > > to the enum in the macro, that would shr
On 26/01/2023 15:02, Kyrylo Tkachov wrote:
Hi Andre,
-Original Message-
From: Andre Vieira (lists)
Sent: Tuesday, January 24, 2023 1:41 PM
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
Subject: [PATCH 1/3] arm: Fix sign of MVE predicate mve_pred16_t [PR
107674]
> -Original Message-
> From: Andre Vieira (lists)
> Sent: Friday, January 27, 2023 9:54 AM
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw
> Subject: Re: [PATCH 1/3] arm: Fix sign of MVE predicate mve_pred16_t [PR
> 107674]
>
>
>
> On 26/01/2023 15:02, Kyrylo Tk
On 26/01/2023 15:06, Kyrylo Tkachov wrote:
Hi Andre,
-Original Message-
From: Andre Vieira (lists)
Sent: Tuesday, January 24, 2023 1:54 PM
To: gcc-patches@gcc.gnu.org
Cc: Richard Sandiford ; Richard Earnshaw
; Richard Biener ;
Kyrylo Tkachov
Subject: [PATCH 2/3] arm: Remove unneces
On Fri, 27 Jan 2023, Jakub Jelinek wrote:
> Hi!
>
> IPA passes redirect some calls in what it determines to be unreachable code
> to builtin_decl_unreachable. But that function returns sometimes
> builtin_decl_explicit (BUILT_IN_UNREACHABLE) (which was what GCC 12
> and earlier did always), or b
> -Original Message-
> From: Andre Vieira (lists)
> Sent: Friday, January 27, 2023 9:58 AM
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford ; Richard Earnshaw
> ; Richard Biener
> Subject: Re: [PATCH 2/3] arm: Remove unnecessary zero-extending of MVE
> predicates b
committed, thanks :)
On Mon, Jan 23, 2023 at 3:29 AM Jeff Law via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
>
>
> On 1/20/23 02:33, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong
> >
> > According to RVV ISA, RVV doesn't support EEW == 64 vector type for
> zve32x
> > and zve32f. So it ma
On Fri, 27 Jan 2023, Jakub Jelinek wrote:
> Hi!
>
> __builtin_va_arg_pack_len as implemented returned int since its introduction
> in 2007. The initial documentation didn't mention any return type,
> which changed in 2010 in r0-103077-gab940b73bfabe2cec4 during some
> documentation formatting cl
Committed, thanks!
On Thu, Jan 19, 2023 at 3:03 PM wrote:
> From: Ju-Zhe Zhong
>
> The original constraint is incorrect in pred_mov pattern.
> Take a look at Alternative 2, the operands[0] is "vr",
> operands[1] which is mask operand can be "vm".
> Such alternative matching will give the wrong
committed, thanks!
On Wed, Jan 18, 2023 at 11:13 AM wrote:
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Refine function
> args.
> (emit_vsetvl_insn): Ditto.
>
> ---
> gcc/config/riscv/riscv-vsetvl.cc | 6 +++---
> 1 file changed,
Committed with more comments to describe why this should be fixed.
On Wed, Jan 18, 2023 at 11:10 AM wrote:
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (before_p): Fix bug.
>
> ---
> gcc/config/riscv/riscv-vsetvl.cc | 2 +-
> 1 file changed, 1 insertion(+)
Hi All,
aarch64-option-extensions.def explicitly defines the semantics for an empty midr
field as being:
In that case this field
should contain a space (" ") separated list of the strings in 'Features'
that are required. Their order is not important. An empty string means
do
Hi All,
We were analyzing code quality after recent changes and have noticed that the
tbz support somehow managed to increase the number of branches overall rather
than decreased them.
While investigating this we figured out that the problem is that when an
existing & exists in gimple and the in
Excerpts from Arsen Arsenović via Gcc-patches's message of Januar 27, 2023 1:18
am:
>
> gcc/d/ChangeLog:
>
> * implement-d.texi: Reorder index entries around @items.
>
> ---
> gcc/d/implement-d.texi | 66 ++---
>
> diff --git a/gcc/d/implement-d.texi b/gcc/d/implement-d.texi
>
On Fri, 27 Jan 2023 at 09:29, Jakub Jelinek wrote:
>
> Hi!
>
> On gcc112 which has glibc 2.17 I've noticed
> FAIL: 17_intro/names.cc (test for excess errors)
> FAIL: experimental/names.cc (test for excess errors)
> These are because glibc < 2.19 used __unused as field member of various
> structs,
> OK. PLACEHOLDER_EXPR are only relevant pre simplification.
I presume you mean "pre gimplification" here?
--
Eric Botcazou
This patch is an optimisation, but it's also a prerequisite for
fixing PR96373 without regressing vect-xorsign_exec.c.
Currently the vectoriser vectorises:
for (i = 0; i < N; i++)
r[i] = a[i] * __builtin_copysignf (1.0f, b[i]);
as two unconditional operations (copysign and mult).
tree-ssa-
PR96373 points out that a predicated SVE loop currently converts
trapping unconditional ops into unpredicated vector ops. Doing
the operation on inactive lanes can then raise an exception.
As discussed in the PR trail, we aren't 100% consistent about
whether we preserve traps or not. But the dir
On Fri, 27 Jan 2023, Richard Sandiford wrote:
> PR96373 points out that a predicated SVE loop currently converts
> trapping unconditional ops into unpredicated vector ops. Doing
> the operation on inactive lanes can then raise an exception.
>
> As discussed in the PR trail, we aren't 100% consis
On Fri, 27 Jan 2023, Richard Sandiford wrote:
> This patch is an optimisation, but it's also a prerequisite for
> fixing PR96373 without regressing vect-xorsign_exec.c.
>
> Currently the vectoriser vectorises:
>
> for (i = 0; i < N; i++)
> r[i] = a[i] * __builtin_copysignf (1.0f, b[i]);
>
They prevent the compiler from deeming the NaN result "unused" and
remove the calculation raising INVALID exception. See the discussion
in PR107608 for details.
Tested on x86_64-linux-gnu where the change fixes the test failure.
Ok for trunk?
gcc/testsuite/ChangeLog:
* gcc.dg/pr95115.c (
On Fri, Jan 27, 2023 at 12:05 PM Eric Botcazou wrote:
>
> > OK. PLACEHOLDER_EXPR are only relevant pre simplification.
>
> I presume you mean "pre gimplification" here?
Eh, yes. Spell-checkers ...
> --
> Eric Botcazou
>
>
>
On Fri, Jan 27, 2023 at 07:46:27PM +0800, Xi Ruoyao wrote:
> They prevent the compiler from deeming the NaN result "unused" and
> remove the calculation raising INVALID exception. See the discussion
> in PR107608 for details.
>
> Tested on x86_64-linux-gnu where the change fixes the test failure.
This applies cleanly to gcc-12 and regressions for arm-none-eabi look clean.
OK to apply to gcc-12?
On 06/12/2022 11:23, Kyrylo Tkachov wrote:
-Original Message-
From: Andre Simoes Dias Vieira
Sent: Tuesday, December 6, 2022 11:19 AM
To: 'gcc-patches@gcc.gnu.org'
Cc: Kyrylo Tkach
> -Original Message-
> From: Andre Vieira (lists)
> Sent: Friday, January 27, 2023 12:07 PM
> To: Kyrylo Tkachov ; 'gcc-patches@gcc.gnu.org'
>
> Cc: Richard Earnshaw
> Subject: Re: [PATCH] arm: Fix MVE's vcmp vector-scalar patterns [PR107987]
>
> This applies cleanly to gcc-12 and reg
On Fri, 2023-01-27 at 12:50 +0100, Jakub Jelinek wrote:
> On Fri, Jan 27, 2023 at 07:46:27PM +0800, Xi Ruoyao wrote:
> > They prevent the compiler from deeming the NaN result "unused" and
> > remove the calculation raising INVALID exception. See the discussion
> > in PR107608 for details.
> >
> >
Tamar Christina writes:
> Hi All,
>
> aarch64-option-extensions.def explicitly defines the semantics for an empty
> midr
> field as being:
>
> In that case this field
> should contain a space (" ") separated list of the strings in 'Features'
> that are required. Their order is not
On Fri, Jan 27, 2023 at 08:08:26PM +0800, Xi Ruoyao via Gcc-patches wrote:
> On Fri, 2023-01-27 at 12:50 +0100, Jakub Jelinek wrote:
> > On Fri, Jan 27, 2023 at 07:46:27PM +0800, Xi Ruoyao wrote:
> > > They prevent the compiler from deeming the NaN result "unused" and
> > > remove the calculation r
Thanks for fixing this Richard.
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Richard
> Biener via Gcc-patches
> Sent: Friday, January 13, 2023 8:05 AM
> To: gcc-patches@gcc.gnu.org
> Cc: hongtao@intel.com; ubiz...@gmail.com
> Subjec
On 27/01/23 01:16 +0100, Gerald Pfeifer wrote:
Jonathan (or some other libstdc++ developer), would you mind having a
look at that section of https://gcc.gnu.org/codingconventions.html to
see whether we should do further changes?
Oh wow, it's all wrong. I've pushed the patch below, thanks for
po
On Fri, 27 Jan 2023, Kyrylo Tkachov wrote:
> Thanks for fixing this Richard.
>
> > -Original Message-
> > From: Gcc-patches > bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Richard
> > Biener via Gcc-patches
> > Sent: Friday, January 13, 2023 8:05 AM
> > To: gcc-patches@gcc.gnu
Tamar Christina writes:
> Hi All,
>
> We were analyzing code quality after recent changes and have noticed that the
> tbz support somehow managed to increase the number of branches overall rather
> than decreased them.
>
> While investigating this we figured out that the problem is that when an
>
Richard Biener via Gcc-patches writes:
> On Fri, 27 Jan 2023, Kyrylo Tkachov wrote:
>
>> Thanks for fixing this Richard.
>>
>> > -Original Message-
>> > From: Gcc-patches > > bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Richard
>> > Biener via Gcc-patches
>> > Sent: Friday, Ja
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Fix testcase check.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Ditto.
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_mul
committed, thanks!
On Wed, Jan 18, 2023 at 11:25 AM wrote:
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (vsetvl_insn_p): Add condition to
> avoid ICE.
> (vsetvl_discard_result_insn_p): New function.
> (reg_killed_by_bb_p): rename to find_reg
On Thu, 26 Jan 2023, Patrick Palka wrote:
> On Thu, 26 Jan 2023, Jakub Jelinek wrote:
>
> > On Thu, Jan 26, 2023 at 09:45:35AM -0500, Patrick Palka via Gcc-patches
> > wrote:
> > > > +#define DEFTREECODE(SYM, NAME, TYPE, LENGTH) TYPE,
> > > > +#define END_OF_BASE_TREE_CODES tcc_exceptional,
> >
committed, thanks!
On Fri, Jan 27, 2023 at 8:30 PM wrote:
> From: Ju-Zhe Zhong
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Fix testcase check.
> * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Ditto.
> * gcc.target/riscv/rvv/vsetvl/vs
committed, thanks!
On Thu, Jan 19, 2023 at 2:08 PM wrote:
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc (BASE): Add vlm/vsm
> support.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtin
committed, thanks!
On Fri, Jan 20, 2023 at 10:21 AM wrote:
> From: Ju-Zhe Zhong
>
> According to
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/
> For "vop_m" intrinsics, C++ overloaded API does not have "_m" suffix.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-b
committed, thanks!
On Fri, Jan 20, 2023 at 10:26 AM wrote:
> From: Ju-Zhe Zhong
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/base/vle-1.C: New test.
> * g++.target/riscv/rvv/base/vle_tu-1.C: New test.
> * g++.target/riscv/rvv/base/vle_tum-1.C: New test.
>
> Am 27.01.2023 um 13:41 schrieb Patrick Palka via Gcc-patches
> :
>
> On Thu, 26 Jan 2023, Patrick Palka wrote:
>
>>> On Thu, 26 Jan 2023, Jakub Jelinek wrote:
>>>
>>> On Thu, Jan 26, 2023 at 09:45:35AM -0500, Patrick Palka via Gcc-patches
>>> wrote:
> +#define DEFTREECODE(SYM, NAME,
We wrongly report:
$ echo "int main () {}" | gcc -xc -gz=none -
gcc: error: -gz=zstd is not supported in this configuration
if zstd compression is not supported by binutils. We should emit the
error message only if -gz=zstd.
PR driver/108572
Ready to be installed?
Thanks,
Martin
gcc/Ch
Hi Richard,
> > + /* The smallest set of feature bits to toggle to enable this
> > + option. */
> >aarch64_feature_flags flag_canonical;
> > - aarch64_feature_flags flags_on;
> > - aarch64_feature_flags flags_off;
> > + /* If this feature is turned on, these bits also need to be turned
>
gcc/
* config/arm/arm.cc (arm_valid_target_attribute_rec): Add ARM function
attribute 'branch-protection' and parse its options.
* doc/extend.texi: Document ARM Function attribute 'branch-protection'.
gcc/testsuite/
* gcc.target/arm/acle/pacbti-m-predef-13.c: New
On Fri, 27 Jan 2023, Richard Sandiford wrote:
> Richard Biener via Gcc-patches writes:
> > On Fri, 27 Jan 2023, Kyrylo Tkachov wrote:
> >
> >> Thanks for fixing this Richard.
> >>
> >> > -Original Message-
> >> > From: Gcc-patches >> > bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Beha
I messed up my first attempt to use dg-bogus with a typo, so didn't
include it in this new test. But it works if I fix the typo.
Tested x86_64-linux. Pushed to trunk.
-- >8 --
libstdc++-v3/ChangeLog:
PR libstdc++/108554
* testsuite/23_containers/map/modifiers/108554.cc: Use dg-b
Thanks to Michael Welsh Duggan for pointing this out.
Tested x86_64-linux. Pushed to trunk.
-- >8 --
There's a string_view with this filename, which should have been used
instead of a string literal.
libstdc++-v3/ChangeLog:
* src/c++20/tzdb.cc (tzdata_stream): Use constant instead of
Tamar Christina writes:
> Hi Richard,
>
>> > + /* The smallest set of feature bits to toggle to enable this
>> > + option. */
>> >aarch64_feature_flags flag_canonical;
>> > - aarch64_feature_flags flags_on;
>> > - aarch64_feature_flags flags_off;
>> > + /* If this feature is turned on, th
On Fri, Jan 27, 2023 at 4:12 AM Richard Sandiford via Gcc-patches
wrote:
>
> Tamar Christina writes:
> > Hi All,
> >
> > aarch64-option-extensions.def explicitly defines the semantics for an empty
> > midr
> > field as being:
> >
> > In that case this field
> > should contain a space (
The vqdml[as]l[hs]_laneq_* tests were folded at compile time, meaning
that we didn't have any Advanced SIMD instructions in the assembly.
Kyrill's preference was to use wrapper functions, so this patch does
that for the failing tests and for others that had scan-assemblers
with inline intrinsics ca
fast-math-bb-slp-complex-add-pattern-half-float.c no longer fails.
The scans in (loop test) fast-math-complex-add-half-float.c were
marked UNRESOLVED because they scanned slp1 rather than vect.
Tested on aarch64-linux-gnu & pushed as obvious.
Richard
gcc/testsuite/
* gcc.dg/vect/complex
Hello,
I have committed a fix [1] into gcc trunk for a build issue mentioned in
pr108505 and
latter received few upstream comments proposing more robust fix for this issue.
In this patch I'm addressing those comments and sending this as a followup
patch.
Regression tested on arm-none-eabi targ
Hi!
On Wed, Nov 09, 2022 at 09:43:16PM -0500, Michael Meissner wrote:
> This patch is very preliminary support for a potential new feature to the
> PowerPC that extends the current power10 MMA architecture. This feature may
> or
> may not be present in any specific future PowerPC processor.
MMA
On Fri, Jan 20, 2023 at 04:05:58PM -0500, Michael Meissner wrote:
> Ping patch. We really would like the patches to enable the possible future
> MMA+ instructions into GCC 13.
Please send a version with Peter's comments taken into account?
Segher
Hi,
you can emulate C++17 inline variables in C++11 with either of the two ways:
1) via a template helper
template
struct Helper
{
static constexpr unsigned value[4] = {1, 2, 3, 4};
};
template
constexpr unsigned Helper::value[4];
static constexpr auto& arr = Helper<>::value;
2) extern c
On Fri, 27 Jan 2023, Martin Liška wrote:
> We wrongly report:
>
> $ echo "int main () {}" | gcc -xc -gz=none -
> gcc: error: -gz=zstd is not supported in this configuration
>
> if zstd compression is not supported by binutils. We should emit the
> error message only if -gz=zstd.
>
> PR dr
WG14 agreed at this week's meeting to remove support for braces around
auto scalar initializers, as incompatible with C++ auto handling of
braced initializers; thus remove that support in GCC.
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
gcc/c/
* c-parser.cc (c_parser_declara
This PR illustrates that __builtin_is_constant_evaluated currently acts
as an optimization barrier for our speculative constexpr evaluation,
since we don't want to prematurely fold the builtin to false if the
expression in question would be later manifestly constant evaluated (in
which case it must
This patch turns the manifestly_const_eval flag used by the constexpr
machinery into a tri-state enum so that we're able to express wanting
to fold __builtin_is_constant_evaluated to false via late speculative
constexpr evaluation. Of all the entry points to constexpr evaluation
only maybe_constan
On Fri, 27 Jan 2023, Patrick Palka wrote:
> This PR illustrates that __builtin_is_constant_evaluated currently acts
> as an optimization barrier for our speculative constexpr evaluation,
> since we don't want to prematurely fold the builtin to false if the
> expression in question would be later m
On Thu, 26 Jan 2023, Marek Polacek via Gcc-patches wrote:
> Here we crash because a CAST_EXPR, representing T(), doesn't have
> its operand, and operand_equal_p's STRIP_ANY_LOCATION_WRAPPER doesn't
> expect that. (o_e_p is called from warn_duplicated_cond_add_or_warn.)
>
> In the past we've adju
On 1/27/23 17:15, Patrick Palka wrote:
On Thu, 26 Jan 2023, Marek Polacek via Gcc-patches wrote:
Here we crash because a CAST_EXPR, representing T(), doesn't have
its operand, and operand_equal_p's STRIP_ANY_LOCATION_WRAPPER doesn't
expect that. (o_e_p is called from warn_duplicated_cond_add_o
On Fri, Jan 27, 2023 at 05:15:00PM -0500, Patrick Palka wrote:
> On Thu, 26 Jan 2023, Marek Polacek via Gcc-patches wrote:
>
> > Here we crash because a CAST_EXPR, representing T(), doesn't have
> > its operand, and operand_equal_p's STRIP_ANY_LOCATION_WRAPPER doesn't
> > expect that. (o_e_p is c
From: Ju-Zhe Zhong
---
gcc/config/riscv/vector.md | 20
1 file changed, 20 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 8c60eb20d72..4319266974d 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -208,26 +2
On Fri, 27 Jan 2023, Marek Polacek wrote:
> On Fri, Jan 27, 2023 at 05:15:00PM -0500, Patrick Palka wrote:
> > On Thu, 26 Jan 2023, Marek Polacek via Gcc-patches wrote:
> >
> > > Here we crash because a CAST_EXPR, representing T(), doesn't have
> > > its operand, and operand_equal_p's STRIP_ANY_L
On Fri, 27 Jan 2023, Patrick Palka wrote:
> On Fri, 27 Jan 2023, Marek Polacek wrote:
>
> > On Fri, Jan 27, 2023 at 05:15:00PM -0500, Patrick Palka wrote:
> > > On Thu, 26 Jan 2023, Marek Polacek via Gcc-patches wrote:
> > >
> > > > Here we crash because a CAST_EXPR, representing T(), doesn't ha
Hi!
On Sat, Jan 14, 2023 at 08:26:00AM -0300, Alexandre Oliva via Gcc-patches wrote:
> The testcase used to get scheduled differently depending on the
> presence of debug insns with MEMs. It's not clear to me why those
> MEMs affected scheduling, but the cselib pre-canonicalization of the
> MEM a
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/predicates.md (pmode_reg_or_0_operand): New predicate.
* config/riscv/riscv-vector-builtins-bases.cc (class loadstore):
Support vlse/vsse.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
We added the concept of a relation trio this release. Basically its a
group of relations for a range-op statement indicating the relation
between LHS & OP1, LHS & OP2, and OP1 & OP2.
This is primarily used in GORI so we can use relations during range
calculation on outgoing edges, although It
If there exists an equivalence relationship between op1 and op2,any
binary operation can be broken into individual operations and unioned if
there are sufficiently few elements in the set.
This depends on the first patch as we need to get the relation op1 ==
op2 correct in to the relation_trio
A small refinement. (Too bad the w3 validator isn't automatically usable
for us any more, though I'm checking manually these days.)
Pushed.
Gerald
---
htdocs/codingconventions.html | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/htdocs/codingconventions.html b/htdocs/codingc
Back in 2021 http/https were not supported by ftp.fu-berlin.de, now
they are, so switch over.
Thank you, f...@fu-berlin.de! (And please advise if you'd like to see
things changed.)
Pushed.
Gerald
---
htdocs/mirrors.html | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/htdoc
Committed:
It is not apparent to me that the testsuite/ChangeLog was updated. Maybe
there is a time delay on that?
Please be patient with me as I figure out how all this works.
ommit f963705752e9d0b79a340788166269af417e344e (HEAD -> master,
origin/master, origin/HEAD)
Author: Jerry DeLisle
committed, thanks!
On Sat, Jan 28, 2023 at 6:58 AM wrote:
> From: Ju-Zhe Zhong
>
> ---
> gcc/config/riscv/vector.md | 20
> 1 file changed, 20 deletions(-)
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 8c60eb20d72..4319266974d 100644
> --
committed, thanks!
On Sat, Jan 28, 2023 at 7:26 AM wrote:
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/predicates.md (pmode_reg_or_0_operand): New
> predicate.
> * config/riscv/riscv-vector-builtins-bases.cc (class loadstore):
> Support vlse/vsse.
> (BASE):
committed, thanks!
On Fri, Jan 27, 2023 at 01:59:00PM -0600, Segher Boessenkool wrote:
> > There is one bug that I noticed. When you use the full DMR instruction the
> > constant copy propagation patch issues internal errors. I believe this is
> > due
> > to the CCP pass not handling opaque types cleanly enough, a
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