. the number of passed arguments was varying...)
>
> Testcase cross-checked with NAG 7.1.
>
> Regtested on x86_64-pc-linux-gnu. OK for mainline?
This breaks aarch64:
$ /opt/gcc/gcc-20221113/Build/./gcc/xgcc -B/opt/gcc/gcc-20221113/Build/./gcc/
-B/usr/aarch64-suse-linux/bin/ -B/usr/aarch64-s
expand_builtin_longjmp and expand_builtin_nonlocal_goto both
emit nonlocal gotos. They first try to use a target-provided
pattern and fall back to generic code otherwise. These pieces
of generic code are almost identical, and having them inline
like this makes it difficult to define a nonlocal_go
This series adds support for the Armv9-A Scalable Matrix Extension (SME).
Details about the extension are available here:
https://developer.arm.com/documentation/ddi0616/aa/?lang=en
The ABI and ACLE documentation is available on github:
https://github.com/ARM-software/abi-aa/blob/main/aapcs6
This patch adds support for recognising the SME arm_streaming
and arm_streaming_compatible attributes. These attributes
respectively describe whether the processor is definitely in
"streaming mode" (PSTATE.SM==1), whether the processor is
definitely not in streaming mode (PSTATE.SM==0), or whether
This patch adds the +sme ISA feature and requires it to be present
when compiling arm_streaming code. (arm_streaming_compatible code
does not necessarily assume the presence of SME. It just has to
work when SME is present and streaming mode is enabled.)
gcc/
*
doc/gcc/gcc-command-option
The vast majority of Advanced SIMD instructions are not
available in streaming mode, but some of the load/store/move
instructions are. This patch adds a new target feature macro
called TARGET_BASE_SIMD for this streaming-compatible subset.
The vector-to-vector move instructions are not streaming-
Although TI isn't really a native SVE element mode, it's convenient
for SME if we define VNx1TI anyway, so that it can be used to
distinguish .Q ZA operations from others. It's purely an RTL
convenience and isn't (yet) a valid storage mode.
gcc/
* config/aarch64/aarch64-modes.def: Add VNx
Some SME instructions use w12-w15 to index ZA. This patch
adds a register class for that range.
gcc/
* config/aarch64/aarch64.h (ZA_INDEX_REGNUM_P): New macro.
(ZA_INDEX_REGS): New register class.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add entries for it.
* config/
This patch adds support for switching to the appropriate SME mode
for each call. Switching to streaming mode requires an SMSTART SM
instruction and switching to non-streaming mode requires an SMSTOP SM
instruction. If the call is being made from streaming-compatible code,
these switches are condi
This patch adds support for the arm_locally_streaming attribute,
which allows a function to use SME internally without changing
the function's ABI. The attribute is valid but redundant for
arm_streaming functions.
gcc/
* config/aarch64/aarch64.cc (aarch64_attribute_table): Add
arm
Until now, SVE intrinsics that map directly to unspecs
have always used type suffix 0 to distinguish between signed
integers, unsigned integers, and floating-point values.
SME adds functions that need to use type suffix 1 instead.
This patch generalises the classes accordingly.
gcc/
* conf
We only support tail calls between functions with the same PSTATE.ZA
setting ("private-ZA" to "private-ZA" and "shared-ZA" to "shared-ZA").
Only a normal non-streaming function can tail-call another non-streaming
function, and only a streaming function can tail-call another streaming
function. An
SME has an array called ZA that can be enabled and disabled separately
from streaming mode. A status bit called PSTATE.ZA indicates whether
ZA is currently enabled or not.
In C and C++, the state of PSTATE.ZA is controlled using function
attributes. If a function's type has an arm_shared_za attr
In SVE there was a simple rule that unary merging (_m) intrinsics
had a separate initial argument to specify the values of inactive
lanes, whereas other merging functions took inactive lanes from
the first operand to the operation.
That rule began to break down in SVE2, and it continues to do
so i
So far, all intrinsics covered by the aarch64-sve-builtins*
framework have (naturally enough) required at least SVE.
However, arm_sme.h defines a couple of intrinsics that can
be called by any code. It's therefore necessary to make
the implicit SVE requirement explicit.
gcc/
* config/aarc
A function that has local ZA state cannot be inlined into its caller,
since we only support managing ZA switches at function scope.
A function whose body requires a particular PSTATE.SM setting can only
be inlined into a function body that guarantees that PSTATE.SM setting.
(The callee's function
This patch adds a new interface to function_resolver::resolve_to
in which the mode suffix stays the same (which is the common case).
It then moves the handling of explicit first type suffixes from
function_resolver::resolve_unary to this new function.
This makes things slightly simpler for existin
Le 09/11/2022 à 21:50, Harald Anlauf via Fortran a écrit :
Dear all,
Jose posted a patch here that was never reviewed:
https://gcc.gnu.org/pipermail/fortran/2021-June/056162.html
I think the diagnostics improvement is helpful, as it adjusts
to the changes from F2003 to F2008.
The patch suf
On Sun, Nov 13, 2022 at 1:47 AM Bernhard Reutner-Fischer via Fortran
wrote:
> --- a/gcc/fortran/arith.cc
> +++ b/gcc/fortran/arith.cc
> @@ -1135,7 +1135,7 @@ compare_complex (gfc_expr *op1, gfc_expr *op2)
> strings. We return -1 for a < b, 0 for a == b and 1 for a > b.
> We use the proces
On Sun, 13 Nov 2022 12:13:26 +0200
Janne Blomqvist wrote:
> On Sun, Nov 13, 2022 at 1:47 AM Bernhard Reutner-Fischer via Fortran
> wrote:
> > --- a/gcc/fortran/arith.cc
> > +++ b/gcc/fortran/arith.cc
> > @@ -1135,7 +1135,7 @@ compare_complex (gfc_expr *op1, gfc_expr *op2)
> > strings. We re
On Sun, 13 Nov 2022 at 01:17, Jonathan Wakely via Libstdc++
wrote:
>
> Tested x86_64-linux and powerpc64le-linux. Pushed to trunk.
>
> -- >8 --
>
> Also add the basic types for timezones, without the non-inline
> definitions needed to actually use them.
This is the patch for the rest of the time
On 11/11/22 18:25, Arnaud Charlet wrote:
>
>> Similarly to other manuals, we should include the page
>> in HTML builder.
>>
>> What Ada folks think about it?
>
> The latest changes have broken our build of the Ada doc at AdaCore so until
> further notice, please do not make any additional chang
On Fri, Nov 11, 2022 at 08:43:04AM +0100, Jakub Jelinek wrote:
> Again, because stage1 close is near, posting the following patch
> to implement CWG 2654.
>
> Ok for trunk if it passes bootstrap/regtest and is voted into C++23
> and C++20 as a DR?
Here is an updated patch that passed bootstrap/re
On Fri, Nov 11, 2022 at 06:07:04PM +0100, Jakub Jelinek wrote:
> The following patch on top of Marek's P2448 PR106649 patch
> (mainly because that patch implements the previous __cpp_constexpr
> feature test macro bump so this can't go in earlier; OT,
> P2280R4 doesn't have any feature test macro?)
On Sat, Nov 12, 2022 at 12:23:56PM +0100, Jakub Jelinek wrote:
> The following patch implements CWG2635.
>
> So far tested on
> GXX_TESTSUITE_STDS=98,11,14,17,20,2b make check-g++
> RUNTESTFLAGS="dg.exp=decomp*"
> ok for trunk if it passes full bootstrap/regtest and it is voted in?
Here is anoth
> Am 12.11.2022 um 19:18 schrieb Joseph Myers :
>
> C2x adds __STDC_VERSION_*_H__ macros to individual headers with
> interface changes compared to C17. All the new header features in
> headers provided by GCC have now been implemented, so define those
> macros to the value given in the curre
> Sorry for the breakage. However, I contacted you (and your colleague) and
> haven't received
> any feedback for a couple of weeks.
Right although I did give you feedback that what you sent wasn’t in a suitable
form for review wrt Ada.
Arno
On 11/13/22 13:26, Arnaud Charlet wrote:
>
>> Sorry for the breakage. However, I contacted you (and your colleague) and
>> haven't received
>> any feedback for a couple of weeks.
>
> Right although I did give you feedback that what you sent wasn’t in a
> suitable form for review wrt Ada.
Sure,
From: Christoph Müllner
This patch adds a new pass that looks up function pointer assignments,
and adds guarded direct calls to the call sites of the function
pointers.
E.g.: Lets assume an assignment to a function pointer as follows:
b->cb = &myfun;
Other part of the program can u
During the Sphinx-migration development, I used
SPHINX_BUILD='' in order to skip building info and manual
pages in gcc folder. However, we've got HAS_SPHINX_BUILD
which is the correct flag for that.
With the patch, one will get a nicer error message when
sphinx-build is missing and one builds (exp
From: mtsamis
The IPA CP pass offers a wide range of optimizations, where most of them
lead to specialized functions that are called from a call site.
This can lead to multiple specialized function clones, if more than
one call-site allows such an optimization.
If not all call-sites can be optimi
Applied to master. Thanks!
Note that the multiply-by-200 (in the testcase) originates from Dhrystone.
Philipp.
On Sun, 13 Nov 2022 at 02:23, Jeff Law wrote:
>
>
> On 11/10/22 14:34, Philipp Tomsich wrote:
> > The strength-reduction implementation in expmed.cc will assess the
> > profitability
It is confusing that 'Indexes and tables' contains TODO. One gets
Index by clicking to the Index link.
PR web/107643
ChangeLog:
* doc/baseconf.py: Set include_todo tag if INCLUDE_TODO env
is set.
* doc/indices-and-tables.rst: Use include_todo tag.
---
doc/basecon
Applied to master as obvious.
ChangeLog:
* doc/contrib.rst: Update Jeff Law's email address.
Signed-off-by: Philipp Tomsich
---
doc/contrib.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/contrib.rst b/doc/contrib.rst
index 96bf2a56af4..15e358b7903 100644
-
On 11/11/22 22:10, Sandra Loosemore wrote:
> On 11/11/22 13:52, Gerald Pfeifer wrote:
>> On Tue, 8 Nov 2022, Martin Liška wrote:
>>> After the migration, people should be able to build (and install) GCC
>>> even if they miss Sphinx (similar happens now if you miss makeinfo).
>>
>> My nightly *insta
Applied to master. Thanks!
--Philipp.
On Sun, 13 Nov 2022 at 01:24, Jeff Law wrote:
>
>
> On 11/8/22 12:54, Philipp Tomsich wrote:
> > If-conversion is turning '(a >= 0) ? b : 0' into a branchless sequence
> > not a5,a0
> > sraia5,a5,63
> > and a0,a1,a5
> > missing t
This patch adds support for Ampere-1A CPU:
- recognize the name of the core and provide detection for -mcpu=native,
- updated extra_costs,
- adds a new fusion pair for (A+B+1 and A-B-1).
Ampere-1A and Ampere-1 have more timing difference than the extra
costs indicate, but these don't propagate
> >> Sorry for the breakage. However, I contacted you (and your colleague) and
> >> haven't received
> >> any feedback for a couple of weeks.
> >
> > Right although I did give you feedback that what you sent wasn’t in a
> > suitable form for review wrt Ada.
>
> Sure, but sending a patch set to
Committed to trunk.
Dave
---
Skip guality tests on hppa-hpux.
The guality check command hangs. This causes TCL errors in
other tests and slows testsuite execution.
2022-11-13 John David Anglin
gcc/testsuite/ChangeLog:
* g++.dg/guality/guality.exp: Skip on hppa*-*-hpux*.
* g
I'm unsure why this issue only started manifesting now with how old this
code is, but this should fix it.
libstdc++-v3/ChangeLog:
* python/Makefile.am: Call mkinstalldirs before INSTALL_DATA
when installing gdb scripts.
* python/Makefile.in: Regenerate.
---
Hi,
Someone sp
On 11/9/22 10:09, Martin Liška wrote:
I noticed I modified Makefile.in files in the Sphinx series. While I was
supposed to modifiky Makefile.am and use automake. I'm going to fix that soon.
A recent master build against (apparently too old)
python3-sphinx-5.0.2-2.fc37.noarch failed for me with
On 11/12/22 03:47, Jonathan Wakely wrote:
On Fri, 11 Nov 2022 at 21:00, Stephan Bergmann wrote:
On 11/11/22 06:30, Jonathan Wakely via Gcc-patches wrote:
As discussed in the PR, this makes it three times faster to construct
iostreams objects.
Tested x86_64-linux. Pushed to trunk.
I haven't
On 11/13/22 20:18, Stephan Bergmann wrote:
> On 11/9/22 10:09, Martin Liška wrote:
>> I noticed I modified Makefile.in files in the Sphinx series. While I was
>> supposed to modifiky Makefile.am and use automake. I'm going to fix that
>> soon.
>
> A recent master build against (apparently too old
On Sun, 13 Nov 2022, 19:23 Stephan Bergmann via Libstdc++, <
libstd...@gcc.gnu.org> wrote:
> On 11/12/22 03:47, Jonathan Wakely wrote:
> > On Fri, 11 Nov 2022 at 21:00, Stephan Bergmann
> wrote:
> >>
> >> On 11/11/22 06:30, Jonathan Wakely via Gcc-patches wrote:
> >>> As discussed in the PR, this
On 11/12/22 01:06, Joseph Myers wrote:
> On Fri, 11 Nov 2022, Tobias Burnus wrote:
>
>> For /onlinedocs/, I concur that we want to have the old doc there as there
>> are
>> many
>> deep links. Still, we should consider adding a disclaimer box to all former
>> mainline
>> documentation stating tha
On Sun, 13 Nov 2022, 18:06 Arsen Arsenović via Libstdc++, <
libstd...@gcc.gnu.org> wrote:
> I'm unsure why this issue only started manifesting now with how old this
> code is, but this should fix it.
>
I just pushed a change to how the debug build makefiles are generated,
which presumably uncover
It seems SQRT is relatively straightforward, and it's something Jakub
wanted for this release.
Jakub, what do you think?
p.s. Too tired to think about op1_range.
gcc/ChangeLog:
* gimple-range-op.cc (class cfn_sqrt): New.
(gimple_range_op_handler::maybe_builtin_call): Add cases f
Am 13.11.22 um 11:39 schrieb Bernhard Reutner-Fischer via Gcc-patches:
On Sun, 13 Nov 2022 12:13:26 +0200
Janne Blomqvist wrote:
On Sun, Nov 13, 2022 at 1:47 AM Bernhard Reutner-Fischer via Fortran
wrote:
--- a/gcc/fortran/arith.cc
+++ b/gcc/fortran/arith.cc
@@ -1135,7 +1135,7 @@ compare_com
On Sun, 13 Nov 2022 19:42:52 +
Jonathan Wakely via Gcc-patches wrote:
> On Sun, 13 Nov 2022, 18:06 Arsen Arsenović via Libstdc++, <
> libstd...@gcc.gnu.org> wrote:
>
> > I'm unsure why this issue only started manifesting now with how old this
> > code is, but this should fix it.
> >
>
>
On Sun, Nov 13, 2022 at 09:05:53PM +0100, Aldy Hernandez wrote:
> It seems SQRT is relatively straightforward, and it's something Jakub
> wanted for this release.
>
> Jakub, what do you think?
>
> p.s. Too tired to think about op1_range.
That would be multiplication of the same value twice, i.e.
RISC-V's .p2align (currently) ignores the max-skip argument. As we
have experimental patches underway to address this in a
backwards-compatible manner, let's prepare GCC for the day when
binutils gets updated.
gcc/ChangeLog:
* config/riscv/riscv.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Implement.
The Zihintpause extension uses an opcode from the 'fence' opcode range
to add a true hint instruction (i.e. if it is not supported on any
given platform, the 'fence' that is encoded will not enforce any
specific ordering on memory accesses) for entering a low-power state
(e.g. in an idle thread).
This series provides support for the Ventana VT1 (a 4-way superscalar
rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support
for the supported instruction fusion patterns.
This includes the addition of the fusion-aware scheduling
infrastructure for RISC-V and implements idiom rec
The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and
XVentanaCondOps.
This introduces a placeholder -mcpu=ventana-vt1, so tooling and
scripts don't need to change once full support (pipeline, tuning,
etc.) will become public later.
gcc/ChangeLog:
* config/riscv/riscv-core
For a straightforward application of bext for the following function
long bext64(long a, char bitno)
{
return (a & (1UL << bitno)) ? 0 : -1;
}
we generate
srl a0,a0,a1# 7 [c=4 l=4] lshrdi3
andia0,a0,1 # 8 [c=4 l=4] anddi3/1
addia0,a0,-
The Ventana VT1 core supports quad-issue and instruction fusion.
This implemented TARGET_SCHED_MACRO_FUSION_P to keep fusible sequences
together and adds idiom matcheing for the supported fusion cases.
gcc/ChangeLog:
* config/riscv/riscv.cc (enum riscv_fusion_pairs): Add symbolic
Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..."
that can be expressed as bexti + bexti + andn.
gcc/ChangeLog:
* config/riscv/bitmanip.md
(*branch_mask_twobits_equals_singlebit):
Handle "if ((a & T) == C)" using Zbs, when T has 2 bits set and C has
on
We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1"
by splitting it into a zero-extraction (bext) and an xori. This both
avoids burning a register on a temporary and generates a sequence that
clearly captures 'extract bit, then invert bit'.
This change improves the previousl
Hi!
x86_64/i686 has for a few weeks working std::bfloat16_t support, __bf16
there is no longer a storage only type, but can be used for arithmetics
and is supported in libgcc and libstdc++.
The following patch adds similar support for AArch64.
Bootstrapped/regtested on aarch64-linux.
Regression
Am 13.11.22 um 09:51 schrieb Andreas Schwab:
This breaks aarch64:
$ /opt/gcc/gcc-20221113/Build/./gcc/xgcc -B/opt/gcc/gcc-20221113/Build/./gcc/
-B/usr/aarch64-suse-linux/bin/ -B/usr/aarch64-suse-linux/lib/ -isystem
/usr/aarch64-suse-linux/include -isystem /usr/aarch64-suse-linux/sys-include
On Sat, Nov 12 2022, Martin Jambor wrote:
> Hi,
>
> When building vectors of known aggregate values, there is no point in
> including those for parameters which are not used in any way
> whatsoever.
>
> Bootstrapped and tested on x86_64-linux. OK for master?
>
> Thanks,
>
> Martin
When doing LTO
...similar to 1f9c79367e136e0ca5b775562e6111e1a0d0046f "sphinx: fix
building if
sphinx-build is missing"
gcc/ChangeLog:
* fortran/Make-lang.in: Build info pages conditionally.
---
gcc/fortran/Make-lang.in | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/fortra
On 11/13/22 20:26, Martin Liška wrote:
The patch is fine, please send it to gcc-patches ML and install it.
I sent a patch now, but don't have commit rights.
This adds the xventanacondops extension to the option parsing and as a
default for the ventana-vt1 core:
gcc/Changelog:
* common/config/riscv/riscv-common.cc: Recognize
"xventanacondops" as part of an architecture string.
* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS
Adds a pattern to map the output of noce_try_store_flag_mask
if-conversion in the combiner onto vt.maskc; the input patterns
supported are similar to the following:
(set (reg/v/f:DI 75 [ ])
(and:DI (neg:DI (ne:DI (reg:DI 82)
(const_int 0 [0])))
(reg/v
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what combination of XVentanaCondOps and Zbs are
available, th
Both the XVentanaCondOps (a vendor-defined extension from Ventana
Microsystems) and the proposed ZiCondOps extensions define a
conditional-zero(-or-value) instruction, which is similar to the
following C construct:
rd = rc ? rs : 0
This functionality can be tied back into if-convertsion and al
When if-conversion encounters sequences using immediates, the
sequences can't trivially map back onto vt.maskc/vt.maskcn (even if
benefitial) due to vt.maskc and vt.maskcn not having immediate forms.
This adds a splitter to rewrite opportunities for XVentanaCondOps that
operate on an immediate by
When if-conversion in noce_try_store_flag_mask starts the sequence off
with an order-operator, our patterns for vt.maskc will receive the
result of the order-operator as a register argument; consequently,
they can't know that the result will be either 1 or 0.
To convey this information (and make v
While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can
trigger conversion into efficient branchless sequences
- with Zbs (bexti + neg + and)
- with XVentanaCondOps (andi + vt.maskc)
the inverted/negated case results in
andi a5,a0,1024
seqz a5,a5
neg a5,a5
and a5,a5,a1
du
Some architectures, as it the case on RISC-V with the proposed
ZiCondOps and the vendor-defined XVentanaCondOps, define a
conditional-zero instruction that is equivalent to:
- the positive form: rd = (rc != 0) ? rs : 0
- the negated form: rd = (rc == 0) ? rs : 0
While noce_try_store_flag_mask
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_CORE): Update the
Ventana-VT1 definition to include the xventanacondops
extension.
Signed-off-by: Philipp Tomsich
---
Changes in v2:
- New in v2.
gcc/config/riscv/riscv-cores.def | 2 +-
1 file changed, 1 insertion(+
From: Christoph Müllner
This series adds support for the following vendor extensions
from T-Head:
* XTheadCmo, XTheadSync
* XTheadBa, XTheadBb, XTheadBs
* XTheadCondMov
* XTheadMac
* XTheadFmv, XTheadInt
No regressions observed.
Christoph Müllner (7):
riscv: Add basic XThead* vendor extensio
From: Christoph Müllner
This patch add basic support for the following XThead* ISA extensions:
* XTheadCmo, XTheadSync
* XTheadBa, XTheadBb, XTheadBs, XTheadCondMov
* XTheadMac
* XTheadFMemIdx, XTheadMemIdx
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add xthead* extensions.
From: Christoph Müllner
This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").
gcc/ChangeLog:
From: Christoph Müllner
This patch adds support for XTheadCondMov ISA extension.
The extension brings a one-sided conditional move (no else-assignment).
Given that GCC has a great if-conversion pass, we don't need to do much,
besides properly expanding movcc accordingly and adjust the cost
model.
From: Christoph Müllner
The XTheadBb ISA extension provides instructions similar to Zbb:
* th.srri/th.srriw
* th.ext/th.extu
* th.ff1 (count-leading-zeros)
* th.rev/th.revw
Instructions that are not covered, because they don't fit into a
pattern:
* th.ff0 (count-leading-ones)
* th.tstnbz
For th
From: Christoph Müllner
This patch adds support for the following T-Head vendor extensions:
* XTheadBa
* XTheadBs
Both extensions provide just one instruction, that has a counterpart
in the similar named Bitmanip ISA extension.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs):
From: Christoph Müllner
This patch add basic support for the XTheadFmv and XTheadInt
ISA extension. As both extensions only contain instruction,
which are not supposed to be emitted by the compiler, the support
only covers awareness of the extension name in the march string
and the definition of
From: Christoph Müllner
The XTheadMac ISA extension provides multiply-accumulate/subtract
instructions:
* mula/mulaw/mulah
* muls/mulsw/mulsh
To benefit from middle-end passes, we expand the following named
patterns in riscv.md (as they are not T-Head-specific):
* maddhisi4
* msubhisi4
gcc/Chan
On 13 November 2022 21:29:50 CET, Harald Anlauf wrote:
>Replacing "int" by "signed char" adds confusion and makes code
>less understandable, so I would oppose it, as we don't solve a
>real problem and rather add confusion.
Ok so consider the non-bool hunks dropped, they just fell out of my helpe
From: "moiz.hussain"
The XTheadMacXTheadMemPair ISA extension provides load/store
pair instructions:
* th.ldd
* th.sdd
* th.lwd
* th.lwud
* th.swd
We added the following unnamed patterns to the
peephole.md stage:
* load/store pair patterns for 4 instructions
* load/store pair patterns for 2 inst
This patch adds a new -Wanalyzer-tainted-assertion warning to
-fanalyzer's "taint" mode (which also requires -fanalyzer-checker=taint).
It complains about attacker-controlled values being used in assertions,
or in any expression affecting control flow that guards a "noreturn"
function. As noted i
From: Christoph Müllner
This patch adds the field overlap_op_by_pieces to the struct
riscv_tune_param, which allows to enable the overlap_op_by_pieces
infrastructure.
gcc/ChangeLog:
* config/riscv/riscv.c (struct riscv_tune_param): New field.
(riscv_overlap_op_by_pieces): New fu
From: Christoph Müllner
The current implementation of riscv_block_move_straight() emits a couple
of load-store pairs with maximum width (e.g. 8-byte for RV64).
The remainder is handed over to move_by_pieces(), which emits code based
target settings like slow_unaligned_access and overlap_op_by_pie
From: Christoph Müllner
This patchset adds includes patches to improve the following builtin
expansions:
* cpymemsi: Allow by-pieces to generate overlapping memory accesses
* cmpstrsi: Add expansion for strcmp and strncmp for aligned strings when
zbb/orc.b is available
* strlen: Add expansion f
From: Philipp Tomsich
As a basis for optimized string functions (e.g., the by-pieces
implementations), we need orc.b available. This adds orc.b as an
unspec, so we can expand to it.
gcc/ChangeLog:
* config/riscv/bitmanip.md (orcb2): Add orc.b as an
unspec.
* config/ri
From: Christoph Müllner
INSNs are usually postfixed by a number representing the argument count.
Given the instructions will be used in a later commit, let's make them
visible, but add a "riscv_" prefix to avoid conflicts with standard
INSNs.
gcc/ChangeLog:
* config/riscv/bitmanip.md (*
From: Christoph Müllner
Let's try to not accumulate too much functionality in one single file
as this does not really help maintaining or extending the code.
So in order to add more similar functionality like riscv_block_move_loop
let's move this function to a separate file.
This change does not
From: Christoph Müllner
This patch implements the expansion of the strlen builtin
using Zbb instructions (if available) for aligned strings
using the following sequence:
li a3,-1
addia4,a0,8
.L2: ld a5,0(a0)
addia0,a0,8
orc.b a5,a5
beq a5,a3
From: Christoph Müllner
This patch implements expansions for the cmpstrsi and the cmpstrnsi
builtins using Zbb instructions (if available).
This allows to inline calls to strcmp() and strncmp().
The expansion basically emits a peeled comparison sequence (i.e. a peeled
comparison loop) which comp
On Sun, 13 Nov 2022, Martin Liška wrote:
> So Gerald, I'm suggesting a new url base gcc.gnu.org/docs that will be
> filled with the new manuals and gcc.gnu.org/onlinedocs/$man and
> gcc.gnu.org/install locations should point to older (trunk) manuals
> (prev folder at server I guess). Having that
On Wed, Nov 9, 2022 at 9:29 AM Hongyu Wang wrote:
>
> > Although ix86_small_unroll_insns is coming from issue_rate, it's tuned
> > for codesize.
> > Make it exact as issue_rate and using factor * issue_width /
> > loop->ninsns may increase code size too much.
> > So I prefer to add those 2 paramet
On Thu, Nov 10, 2022 at 2:04 PM Haochen Jiang via Gcc-patches
wrote:
>
> Hi all,
>
> This patch aims to mention newly added Intel ISA and march support.
>
> Ok for trunk?
Ok.
>
> BRs,
> Haochen
>
> ---
> htdocs/gcc-13/changes.html | 50 ++
> 1 file changed, 50
On Fri, Nov 11, 2022 at 10:47 PM Tamar Christina via Gcc-patches
wrote:
>
> Hi All,
>
> The current i386 implementation of the TARGET_CAN_CHANGE_MODE_CLASS is
> currently
> not useful before re-alloc.
>
> In particular before regalloc optimization passes query the hook using
> ALL_REGS,
> but be
How about I do this work on Glibc?
在 2022/11/12 下午3:08, Xi Ruoyao 写道:
On Wed, 2022-11-09 at 21:53 +0800, Xi Ruoyao wrote:
These patches allow to expand the following builtins to floating point
instructions for LoongArch:
- __builtin_rint{,f}
- __builtin_{l,ll}rint{,f}
- __builtin_{l,ll}floor
On 11/13/22 15:05, Christoph Muellner wrote:
+static bool
+riscv_overlap_op_by_pieces (void)
+{
+ return tune_param->overlap_op_by_pieces;
Does this not need to be gated on unaligned access enabled as well.
-Vineet
Hi.
The situation with the Sphinx migration went out of control. The TODO list
overwhelmed me and there are road-blocks that can't be easily fixed with what
Sphinx currently supports. That would require addition of an upstream support
and
a possible new Sphinx release.
Let me summarize the bigge
The following patch will be needed for ChangeLog entry emission
of the reverted Sphinx commits.
Pushed.
Martin
contrib/ChangeLog:
* gcc-changelog/git_commit.py: Temporarily disable
check_line.start.
---
contrib/gcc-changelog/git_commit.py | 2 ++
1 file changed, 2 insertions(+)
On 11/13/22 18:03, Arnaud Charlet wrote:
Sorry for the breakage. However, I contacted you (and your colleague) and
haven't received
any feedback for a couple of weeks.
>>>
>>> Right although I did give you feedback that what you sent wasn’t in a
>>> suitable form for review wrt Ada
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