Re: [PATCH] Always use TYPE_MODE instead of DECL_MODE for vector field

On Fri, Oct 21, 2022 at 6:18 PM H.J. Lu wrote: > > On Fri, Oct 21, 2022 at 2:33 AM Richard Biener > wrote: > > > > On Thu, Oct 20, 2022 at 6:58 PM H.J. Lu via Gcc-patches > > wrote: > > > > > > commit e034c5c895722e0092d2239cd8c2991db77d6d39 > > > Author: Jakub Jelinek > > > Date: Sat Dec 2 0

Re: vect: Make vect_check_gather_scatter reject offsets that aren't multiples of BITS_PER_UNIT [PR107346]

On Fri, 21 Oct 2022, Andre Vieira (lists) wrote: > Hi, > > The ada failure reported in the PR was being caused by > vect_check_gather_scatter failing to deal with bit offsets that weren't > multiples of BITS_PER_UNIT. This patch makes vect_check_gather_scatter reject > memory accesses with such o

[PATCH] c, c++: Fix up excess precision handling of scalar_to_vector conversion [PR107358]

Hi! As mentioned earlier in the C++ excess precision support mail, the following testcase is broken with excess precision both in C and C++ (though just in C++ it was triggered in real-world code). scalar_to_vector is called in both FEs after the excess precision promotions (or stripping of EXCESS

Re: [PATCH] Rename nonzero_bits to known_zero_bits.

On Fri, Oct 21, 2022 at 3:15 PM Aldy Hernandez via Gcc-patches wrote: > > The name nonzero_bits is confusing. We're not tracking nonzero bits. > We're tracking known-zero bits, or at the worst we're tracking "maye > nonzero bits". But really, the only thing we're sure about in the > "nonzero" bi

[PATCH] c++: Fix up constexpr handling of char/signed char/short pre/post inc/decrement [PR105774]

Hi! signed char, char or short int pre/post inc/decrement are represented by normal {PRE,POST}_{INC,DEC}REMENT_EXPRs in the FE and only gimplification ensures that the {PLUS,MINUS}_EXPR is done in unsigned version of those types: case PREINCREMENT_EXPR: case PREDECREMENT_EXPR: case POS

Re: [RFC] how to handle the combination of -fstrict-flex-arrays + -Warray-bounds

On Sat, 22 Oct 2022, Martin Sebor wrote: > On 10/21/22 09:29, Qing Zhao wrote: > > Hi, > > > > (FAM below refers to Flexible Array Members): > > > > I need inputs on how to handle the combination of -fstrict-flex-arrays + > > -Warray-bounds. > > > > Our initial goal is to update -Warray-bounds

Re: [PATCH] [PR tree-optimization/107365] Check HONOR_NANS instead of flag_finite_math_only in frange:verify_range.

On Sun, Oct 23, 2022 at 4:57 PM Aldy Hernandez via Gcc-patches wrote: > > [Jakub and other FP experts, would this be OK, or am I missing > something?] > > Vax does not seem to have !flag_finite_math_only, but float_type_node > does not HONOR_NANS. The check in frange::verify_range dependend on >

*ping* Re: [Patch] OpenMP: Fix reverse offload GOMP_TARGET_REV IFN corner cases [PR107236]

Ping this patch – and also "Re: [Patch][v5] libgomp/nvptx: Prepare for reverse-offload callback handling". For the latter cf. Alexander's code approval https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603908.html – and his concerns regarding the generic feature in https://gcc.gnu.org/piperm

Re: [PATCH] lto: Always quote path to touch

On Fri, 21 Oct 2022, Torbj?rn SVENSSON wrote: > When generating the makefile, make sure that the paths are quoted so > that a native Windows path works within Cygwin. > > Without this patch, this error is reported by the DejaGNU test suite: > > make: [T:\ccMf0kI3.mk:3: T:\ccGEvdDp.ltrans0.ltrans

Re: Extend fold_vec_perm to fold VEC_PERM_EXPR in VLA manner

On Mon, 17 Oct 2022 at 16:02, Prathamesh Kulkarni wrote: > > On Mon, 10 Oct 2022 at 16:18, Prathamesh Kulkarni > wrote: > > > > On Fri, 30 Sept 2022 at 21:38, Richard Sandiford > > wrote: > > > > > > Richard Sandiford via Gcc-patches writes: > > > > Prathamesh Kulkarni writes: > > > >> Sorry t

Re: Adding a new thread model to GCC

> could you please refresh/recheck your patch for the current gcc master > and solve the objections noted in the thread? is it possible? I can do the former, but not the latter as my development setup (mostly testing) on Windows has nearly vanished in the meantime. But this rewritten implementa

Re: Adding a new thread model to GCC

On 2022-10-24 08:15, Eric Botcazou wrote: could you please refresh/recheck your patch for the current gcc master and solve the objections noted in the thread? is it possible? Hi, I can do the former, but not the latter as my development setup (mostly testing) on Windows has nearly vanished

[PATCH] Relax assertion in profile.cc

Hi, this assertion in branch_prob: if (bb == ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb) { location_t loc = DECL_SOURCE_LOCATION (current_function_decl); gcc_checking_assert (!RESERVED_LOCATION_P (loc)); had been correct until: 2021-08-11 Bernd Edlinger PR debug/101598

Re: vect: Make vect_check_gather_scatter reject offsets that aren't multiples of BITS_PER_UNIT [PR107346]

> Eric - the docs of DECL_BIT_FIELD are vague enough "must be accessed > specially" but ISTR it might eventually only apply to the fields > (bit) size and not it's position. OTOH the Ada frontend might not > be too careful in setting this flag for bit-packed structs? It sets the flag when the ali

Re: [PATCH] lto: Always quote path to touch

On 2022-10-24 10:07, Richard Biener wrote: On Fri, 21 Oct 2022, Torbj?rn SVENSSON wrote: When generating the makefile, make sure that the paths are quoted so that a native Windows path works within Cygwin. Without this patch, this error is reported by the DejaGNU test suite: make: [T:\ccMf

[PATCH] ARM: Make ARMv8-M attribute cmse_nonsecure_call work in Ada

Hi, until most other machine attributes, this one does not work in Ada because, while it applies to pointer-to-function types, it is explicitly marked as requiring declarations in the implementation. Now, in Ada, machine attributes are specified like this: type Non_Secure is access procedure;

[PATCH] Aarch64: Do not define DONT_USE_BUILTIN_SETJMP

Hi, we have been using an Ada compiler for the Aarch64 architecture configured with SJLJ exceptions as for the other architectures for some time, and have not run into any problems so far so the setting looks obsolete now. OK for the mainline? 2022-10-24 Eric Botcazou * config/aar

[PATCH] Support Intel CMPccXADD

Hi all, I just refined CMPccXADD patch to make the enum in order intrin file aligned with how opcode does. Ok for trunk? BRs, Haochen gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect cmpccxadd. * common/config/i386/i386-common.cc (O

RE: [PATCH] Support Intel CMPccXADD

> -Original Message- > From: Gcc-patches bounces+haochen.jiang=intel@gcc.gnu.org> On Behalf Of Haochen Jiang > via Gcc-patches > Sent: Monday, October 24, 2022 5:01 PM > To: gcc-patches@gcc.gnu.org > Cc: Liu, Hongtao > Subject: [PATCH] Support Intel CMPccXADD > > Hi all, > > I just

Re: [PATCH] Support Intel CMPccXADD

On Mon, Oct 24, 2022 at 11:01 AM Haochen Jiang wrote: > > Hi all, > > I just refined CMPccXADD patch to make the enum in order intrin file > aligned with how opcode does. > > Ok for trunk? > > BRs, > Haochen > > gcc/ChangeLog: > > * common/config/i386/cpuinfo.h (get_available_features): >

[PATCH] RISC-V: Add h extension support

`h` was the prefix of multi-letter extension name, but it become a extension in later RISC-V isa spec. Fortunately we don't have any extension really defined is prefixed with `h`, so we can just change that. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table):

Re: [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM

Segher Boessenkool writes: > On Thu, Oct 20, 2022 at 07:34:13AM +, Jiang, Haochen wrote: >> > > + /* Argument 3 must be either zero or one. */ >> > > + if (INTVAL (op3) != 0 && INTVAL (op3) != 1) >> > > +{ >> > > + warning (0, "invalid fourth argument to %<__builtin_prefetch%>;" >>

Re: [PATCH] RISC-V: Support --target-help for -mcpu/-mtune

committed. On Fri, Sep 30, 2022 at 10:06 AM Kito Cheng wrote: > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc (riscv_tunes): New. > (riscv_get_valid_option_values): New. > (TARGET_GET_VALID_OPTION_VALUES): New. > * config/riscv/riscv-cores.def (RISCV_T

Re: vect: Make vect_check_gather_scatter reject offsets that aren't multiples of BITS_PER_UNIT [PR107346]

On 24/10/2022 08:17, Richard Biener wrote: Can you check why vect_find_stmt_data_reference doesn't trip on the if (TREE_CODE (DR_REF (dr)) == COMPONENT_REF && DECL_BIT_FIELD (TREE_OPERAND (DR_REF (dr), 1))) { free_data_ref (dr); return opt_result::failure_at (stmt

vect: Fix wrong shift_n after widening on BE [PR107338]

Hi, As PR107338 shows, with the use of widening loads, the container_type can become a wider type, it causes us to get wrong shift_n since the BIT_FIELD_REF offset actually becomes bigger on BE. Taking the case in PR107338 as example, at the beginning the container type is short and BIT_FIELD_REF

Re: [PATCH] Add -gcodeview option

On Mon, 24 Oct 2022, Mark Harmstone wrote: Both current lld and the next version of ld have an option -pdb, which creates a PDB file which Microsoft's debuggers can use. This patch adds a -gcodeview option, which passes this to the linker. I do intend to expand this so it also creates the .debu

Re: [PATCH] Relax assertion in profile.cc

On Mon, Oct 24, 2022 at 10:26 AM Eric Botcazou via Gcc-patches wrote: > > Hi, > > this assertion in branch_prob: > > if (bb == ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb) > { > location_t loc = DECL_SOURCE_LOCATION (current_function_decl); > gcc_checking_assert (!RESERVED_LOCATION_P

Re: [PATCH] c++ modules: verify_type failure with typedef enum [PR106848]

On 10/21/22 09:11, Patrick Palka wrote: On Fri, 21 Oct 2022, Nathan Sidwell wrote: Thanks for the explanation, it's a situation I didn;t anticipate and your fix is good. Could you add a comment about why you need to propagate the values though? Thanks a lot, will do. Just to make sure sin

Re: vect: Make vect_check_gather_scatter reject offsets that aren't multiples of BITS_PER_UNIT [PR107346]

On Mon, 24 Oct 2022, Andre Vieira (lists) wrote: > > On 24/10/2022 08:17, Richard Biener wrote: > > > > Can you check why vect_find_stmt_data_reference doesn't trip on the > > > >if (TREE_CODE (DR_REF (dr)) == COMPONENT_REF > >&& DECL_BIT_FIELD (TREE_OPERAND (DR_REF (dr), 1))) > >

Re: vect: Fix wrong shift_n after widening on BE [PR107338]

On Mon, Oct 24, 2022 at 12:43 PM Kewen.Lin wrote: > > Hi, > > As PR107338 shows, with the use of widening loads, the > container_type can become a wider type, it causes us to > get wrong shift_n since the BIT_FIELD_REF offset actually > becomes bigger on BE. Taking the case in PR107338 as > examp

Re: [Patch] OpenMP: Fix reverse offload GOMP_TARGET_REV IFN corner cases [PR107236]

On Tue, Oct 18, 2022 at 09:27:04PM +0200, Tobias Burnus wrote: > The cgraph_node::create_clone issue is exposed with -O2 for the existing > libgomp.fortran/reverse-offload-1.f90. > > omp-offload.cc > > PR middle-end/107236 > > gcc/ChangeLog: > * omp-expand.cc (expand_omp_target): Set

Re: vect: Make vect_check_gather_scatter reject offsets that aren't multiples of BITS_PER_UNIT [PR107346]

On 24/10/2022 13:46, Richard Biener wrote: On Mon, 24 Oct 2022, Andre Vieira (lists) wrote: On 24/10/2022 08:17, Richard Biener wrote: Can you check why vect_find_stmt_data_reference doesn't trip on the if (TREE_CODE (DR_REF (dr)) == COMPONENT_REF && DECL_BIT_FIELD (TREE_OPERAND

Re: vect: Make vect_check_gather_scatter reject offsets that aren't multiples of BITS_PER_UNIT [PR107346]

On Mon, 24 Oct 2022, Andre Vieira (lists) wrote: > > On 24/10/2022 13:46, Richard Biener wrote: > > On Mon, 24 Oct 2022, Andre Vieira (lists) wrote: > > > >> On 24/10/2022 08:17, Richard Biener wrote: > >>> Can you check why vect_find_stmt_data_reference doesn't trip on the > >>> > >>> if (TR

[PATCH] [PR tree-optimization/107355] Handle NANs in abs range-op entry.

The problem here is that the threader is coming up with a path where the only valid result is a NAN. When the abs op1_range entry is trying to add the negative posibility, it attempts to get the bounds of the working range. NANs don't have bounds so they need to be special cased. PR tree

Re: [PATCH] [PR tree-optimization/107355] Handle NANs in abs range-op entry.

Tested on x86-64 Linux. Pushed. On Mon, Oct 24, 2022 at 3:33 PM Aldy Hernandez wrote: > > The problem here is that the threader is coming up with a path where > the only valid result is a NAN. When the abs op1_range entry is > trying to add the negative posibility, it attempts to get the bounds

Re: Ping (c,c++): Handling of main() function for freestanding

On 10/23/22 07:54, Arsen Arsenović via Gcc-patches wrote: On Friday, 21 October 2022 23:02:02 CEST Joseph Myers wrote: I have no objections to the C changes. Great! Thanks for the review. I don't have push rights currently, so I must ask that someone else pushes this patch for me. Have a gr

Re: [Patch][v5] libgomp/nvptx: Prepare for reverse-offload callback handling

On Wed, Oct 12, 2022 at 10:55:26AM +0200, Tobias Burnus wrote: > libgomp/nvptx: Prepare for reverse-offload callback handling > > This patch adds a stub 'gomp_target_rev' in the host's target.c, which will > later handle the reverse offload. > For nvptx, it adds support for forwarding the offload

Re: [PATCH] c++: Fix up constexpr handling of char/signed char/short pre/post inc/decrement [PR105774]

On 10/24/22 03:27, Jakub Jelinek wrote: Hi! signed char, char or short int pre/post inc/decrement are represented by normal {PRE,POST}_{INC,DEC}REMENT_EXPRs in the FE and only gimplification ensures that the {PLUS,MINUS}_EXPR is done in unsigned version of those types: case PREINCREMENT_EXP

Re: [RFC] how to handle the combination of -fstrict-flex-arrays + -Warray-bounds

> On Oct 22, 2022, at 12:54 PM, Martin Sebor wrote: > > On 10/21/22 09:29, Qing Zhao wrote: >> Hi, >> (FAM below refers to Flexible Array Members): >> I need inputs on how to handle the combination of -fstrict-flex-arrays + >> -Warray-bounds. >> Our initial goal is to update -Warray-bounds wi

[PATCH] RISC-V: Fix typo.

From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Fix typo. --- gcc/config/riscv/riscv-modes.def | 46 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/

RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen4 CPU

> > > This grew insn-automata.cc from 201502 lines to 639968 lines and the > > > build of the automata (genautomata) to several minutes in my dev tree. > > > > Yeah, in my unoptimized non-bootstrapped development tree genautomata > > now takes over 12 minutes on a fast box, that is simply not accep

Re: [PATCH] c++: ICE with invalid structured bindings [PR107276]

On 10/21/22 19:29, Marek Polacek wrote: This test ICEs in C++23 because we reach the new code in do_auto_deduction: 30468 if (cxx_dialect >= cxx23 30469 && context == adc_return_type 30470 && (!AUTO_IS_DECLTYPE (auto_node) 30471 || !unparenthesized_id_or_class_member_acce

Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen4 CPU

On Mon, Oct 24, 2022 at 4:26 PM Alexander Monakov wrote: > > > > This grew insn-automata.cc from 201502 lines to 639968 lines and the > > > > build of the automata (genautomata) to several minutes in my dev > tree. > > > > > > Yeah, in my unoptimized non-bootstrapped development tree genautomata

Re: [RFC] how to handle the combination of -fstrict-flex-arrays + -Warray-bounds

> On Oct 24, 2022, at 3:30 AM, Richard Biener wrote: > > On Sat, 22 Oct 2022, Martin Sebor wrote: > >> On 10/21/22 09:29, Qing Zhao wrote: >>> Hi, >>> >>> (FAM below refers to Flexible Array Members): >>> >>> I need inputs on how to handle the combination of -fstrict-flex-arrays + >>> -Warr

Re: [PATCH] RISC-V: Add h extension support

On 10/24/22 03:55, Kito Cheng wrote: `h` was the prefix of multi-letter extension name, but it become a extension in later RISC-V isa spec. Fortunately we don't have any extension really defined is prefixed with `h`, so we can just change that. gcc/ChangeLog: * common/config/riscv/ri

Re: [PATCH] microblaze: use strverscmp() in MICROBLAZE_VERSION_COMPARE()

On 10/16/22 12:15, Ovidiu Panait via Gcc-patches wrote: Currently, combining '-mxl-multiply-high' with -mcpu=v11.0 produces the following bogus warning: echo "int main(){}" | ./microblazeel-linux-gnu-gcc -mxl-multiply-high \ -mno-xl-soft-mul -mcpu=v11.0 -nostdlib -x c - warning: '-mxl

Re: [PATCH RFA] tree: add build_string_literal overloads

On 10/20/22 14:20, Jason Merrill via Gcc-patches wrote: Tested x86_64-pc-linux-gnu, OK for trunk? -- >8 -- Simplify several calls to build_string_literal by not requiring redundant strlen or IDENTIFIER_* in the caller. I also corrected a wrong comment on IDENTIFIER_LENGTH. gcc/ChangeLog:

Re: [PATCH] c, c++: Fix up excess precision handling of scalar_to_vector conversion [PR107358]

On 10/24/22 01:19, Jakub Jelinek via Gcc-patches wrote: Hi! As mentioned earlier in the C++ excess precision support mail, the following testcase is broken with excess precision both in C and C++ (though just in C++ it was triggered in real-world code). scalar_to_vector is called in both FEs a

Re: [PATCH] builtins: Add __builtin_nextafterf16b builtin

On 10/21/22 01:23, Jakub Jelinek wrote: Hi! On top of the pending https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603665.html patch, the following patch adds another needed builtin. The above patch adds among other things __builtin_nextafterf16 builtin which we need in order to constexp

[OG12 commit] amdgcn, libgomp: USM allocation update

I've committed this patch to the devel/omp/gcc-12 branch. I will have to fold it into my previous OpenMP memory management patch series when I repost it. The patch changes the internal memory allocation method such that memory is allocated in the regular heap and then marked as "coarse-grained

[PATCH] c++: remove use_default_args parm of coerce_template_parms

It looks like the parameter use_default_args introduced in r110693 is effectively unused ever since r7-5536-g3c75aaa3d884ef removed the last (and probably only) 'coerce_template_parms (..., true, false)' call, so this patch gets rid of it. In passing, I noticed we currently define wrapper overload

Re: [PATCH] builtins: Add various complex builtins for _Float{16,32,64,128,32x,64x,128x}

On 10/21/22 09:42, Jakub Jelinek wrote: Hi! On top of the pending https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603665.html https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604080.html the following patch adds some complex builtins which have libm implementation in glibc 2.26 an

[OG12 commit] amdgcn: disallow USM on gfx908

I've committed this patch to the devel/omp/gcc-12 branch. I will have to fold it into my previous OpenMP memory management patch series when I repost it. The GFX908 (MI100) devices only partially support the Unified Shared Memory model that we have, and only then with additional kernel boot p

[OG12 commit] vect: WORKAROUND vectorizer bug

I've committed this to the OG12 branch to remove some test failures. We probably ought to have something on mainline also, but a proper fix would be better. Without this. the libgomp.oacc-c-c++-common/private-variables.c testcase fails to compile due to an ICE. The OpenACC worker broadcasting

[PATCH v2] c++: ICE with invalid structured bindings [PR107276]

On Mon, Oct 24, 2022 at 10:31:50AM -0400, Jason Merrill wrote: > On 10/21/22 19:29, Marek Polacek wrote: > > This test ICEs in C++23 because we reach the new code in do_auto_deduction: > > > > 30468 if (cxx_dialect >= cxx23 > > 30469 && context == adc_return_type > > 30470 && (!AUTO_

Re: [PATCH] c++: Implement -Wdangling-reference [PR106393]

On 10/21/22 19:28, Marek Polacek wrote: This patch implements a new experimental warning (enabled by -Wextra) to detect references bound to temporaries whose lifetime has ended. The Great! primary motivation is the Note in : Capturing the

Re: [PATCH v2] c++: ICE with invalid structured bindings [PR107276]

On 10/24/22 13:13, Marek Polacek wrote: On Mon, Oct 24, 2022 at 10:31:50AM -0400, Jason Merrill wrote: On 10/21/22 19:29, Marek Polacek wrote: This test ICEs in C++23 because we reach the new code in do_auto_deduction: 30468 if (cxx_dialect >= cxx23 30469 && context == adc_return_type

Re: [OG12 commit] vect: WORKAROUND vectorizer bug

> Am 24.10.2022 um 18:51 schrieb Andrew Stubbs : > > I've committed this to the OG12 branch to remove some test failures. We > probably ought to have something on mainline also, but a proper fix would be > better. > > Without this. the libgomp.oacc-c-c++-common/private-variables.c testcase

[PATCH (pushed)] x86: fix VENDOR_MAX enum value

Hi. The following patch fixes detection of VENDOR_CENTAUR CPU vendors when -march=native is used. Problem what that BUILTIN_VENDOR_MAX dropped the current enum value to VENDOR_OTHER (4) and thus VENDOR_MAX was 5 and not 7. Patch can bootstrap on x86_64-linux-gnu and survives regression tests. I

Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen4 CPU

On Mon, 24 Oct 2022, Jan Hubička wrote: > > By the way, it appears pre-existing znver[123] models are also causing > > some kind > > of combinatorial blow-up, but before znver4 it was not a blocking issue: > > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87832 > > > It is really easy to make

Re: [Patch][v5] libgomp/nvptx: Prepare for reverse-offload callback handling

Hi Tobias! On 2022-10-24T16:07:25+0200, Jakub Jelinek via Gcc-patches wrote: > On Wed, Oct 12, 2022 at 10:55:26AM +0200, Tobias Burnus wrote: >> libgomp/nvptx: Prepare for reverse-offload callback handling > Ok, thanks. Per commit r13-3460-g131d18e928a3ea1ab2d3bf61aa92d68a8a254609 "libgomp/nvp

Re: [Patch][v5] libgomp/nvptx: Prepare for reverse-offload callback handling

Hi Tobias! On 2022-10-24T21:05:46+0200, I wrote: > On 2022-10-24T16:07:25+0200, Jakub Jelinek via Gcc-patches > wrote: >> On Wed, Oct 12, 2022 at 10:55:26AM +0200, Tobias Burnus wrote: >>> libgomp/nvptx: Prepare for reverse-offload callback handling > >> Ok, thanks. > > Per commit r13-3460-g131d

Re: [Patch][v5] libgomp/nvptx: Prepare for reverse-offload callback handling

Hi Tobias! On 24.10.22 21:11, Thomas Schwinge wrote: On 2022-10-24T21:05:46+0200, I wrote: On 2022-10-24T16:07:25+0200, Jakub Jelinek via Gcc-patches wrote: On Wed, Oct 12, 2022 at 10:55:26AM +0200, Tobias Burnus wrote: libgomp/nvptx: Prepare for reverse-offload callback handling Well.

libgomp/nvptx: Prepare for reverse-offload callback handling, resolve spurious SIGSEGVs (was: [Patch][v5] libgomp/nvptx: Prepare for reverse-offload callback handling)

Hi! On 2022-10-24T21:11:04+0200, I wrote: > On 2022-10-24T21:05:46+0200, I wrote: >> On 2022-10-24T16:07:25+0200, Jakub Jelinek via Gcc-patches >> wrote: >>> On Wed, Oct 12, 2022 at 10:55:26AM +0200, Tobias Burnus wrote: libgomp/nvptx: Prepare for reverse-offload callback handling >> >>> Ok

Re: [PATCH] c++: remove use_default_args parm of coerce_template_parms

On 10/24/22 12:27, Patrick Palka wrote: It looks like the parameter use_default_args introduced in r110693 is effectively unused ever since r7-5536-g3c75aaa3d884ef removed the last (and probably only) 'coerce_template_parms (..., true, false)' call, so this patch gets rid of it. In passing, I no

[PATCH v2] Always use TYPE_MODE instead of DECL_MODE for vector field

On Mon, Oct 24, 2022 at 12:12 AM Richard Biener wrote: > > On Fri, Oct 21, 2022 at 6:18 PM H.J. Lu wrote: > > > > On Fri, Oct 21, 2022 at 2:33 AM Richard Biener > > wrote: > > > > > > On Thu, Oct 20, 2022 at 6:58 PM H.J. Lu via Gcc-patches > > > wrote: > > > > > > > > commit e034c5c895722e0092d

Re: [PATCH] c, c++: Fix up excess precision handling of scalar_to_vector conversion [PR107358]

On 10/24/22 03:19, Jakub Jelinek wrote: Hi! As mentioned earlier in the C++ excess precision support mail, the following testcase is broken with excess precision both in C and C++ (though just in C++ it was triggered in real-world code). scalar_to_vector is called in both FEs after the excess pr

[committed] wwwdocs: search: Remove trailing slashes on tags

HTML 5 recommends against those. Pushed. --- htdocs/search.html | 46 +++--- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/htdocs/search.html b/htdocs/search.html index 83f26fb5..b3cfa3ce 100644 --- a/htdocs/search.html +++ b/htdocs/search

Re: Adding a new thread model to GCC

On 10/24/22 05:40, LIU Hao via Gcc-patches wrote: 在 2022/10/21 20:34, i.nix...@autistici.org 写道: got it... anyway it seems logical to me the way I proposed :) Below is a message forwarded from mingw-w64-public, elaborating the necessity of a new thread model. As there are objections from

[committed] analyzer: handle "pipe" and "pipe2" [PR106300]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r13-3466-g792f039fc37faa. gcc/analyzer/ChangeLog: PR analyzer/106300 * engine.cc (impl_region_model_context::get_fd_map): New. * exploded-graph.h (impl_region_model_context::get_fd_map): New

[committed] analyzer: simplify sm_state_map lookup

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r13-3467-g53881c47e4b357. gcc/analyzer/ChangeLog: * engine.cc (impl_region_model_context::get_malloc_map): Replace with... (impl_region_model_context::get_state_map_by_name): ...this.

[committed] analyzer: handle (NULL == &VAR) [PR107345]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r13-3468-g18faaeb3af42f3. gcc/analyzer/ChangeLog: PR analyzer/107345 * region-model.cc (region_model::eval_condition_without_cm): Ensure that constants are on the right-hand side before checki

[committed] diagnostics: fix ICE in sarif output with NULL filename [PR107366]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r13-3469-g2e8a0553918adc. gcc/ChangeLog: PR analyzer/107366 * diagnostic-format-sarif.cc (sarif_builder::maybe_make_physical_location_object): Gracefully reject locations with NULL fil

[commited] analyzer: fix ICE on va_copy [PR107349]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Lightly tested with aarch64-unknown-linux. Pushed to trunk as r13-3470-g687d11fd74e7de gcc/analyzer/ChangeLog: PR analyzer/107349 * varargs.cc (get_va_copy_arg): Fix the non-pointer case. gcc/testsuite/ChangeLog:

Re: [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM

On Mon, Oct 24, 2022 at 11:00:26AM +0100, Richard Sandiford wrote: > Segher Boessenkool writes: > > On Thu, Oct 20, 2022 at 07:34:13AM +, Jiang, Haochen wrote: > >> > > + /* Argument 3 must be either zero or one. */ > >> > > + if (INTVAL (op3) != 0 && INTVAL (op3) != 1) > >> > > +{ > >>

Re: [PATCH-2, rs6000] Reverse V8HI on Power8 by vector rotation [PR100866]

Hi! On Mon, Oct 24, 2022 at 11:14:20AM +0800, HAO CHEN GUI wrote: > This patch implements V8HI byte reverse on Power8 by vector rotation. Please put *byte* reverse as the commit subject as well? > It should be effecient than orignial vector permute. The patch comes from > Xionghu's comments in

Re: [PATCH] Add -gcodeview option

On 24/10/22 12:08, Martin Storsjö wrote: Hmm, what does this end up passing to the linker in the end - does it just pass "-pdb="? (What does the "*" parameter do here?) If that's the case - that sounds reasonable - assuming that if a user passes an extra -Wl,--pdb,myspecificname.pdb, that would ta

[PATCH v6] tree-optimization/101186 - extend FRE with "equivalence map" for condition prediction

Sorry for the late update. I've been on a vacation and then I spent some time updating and verifying the patch. Attached is a new version of the patch. There are some changes: 1. Store equivalences in a vn_pval chain in vn_ssa_aux, rather than in the expression hash table. (Following Richard's

Re: [PATCH zero-call-used-regs] Add leafy mode for zero-call-used-regs

Hello, Qing, It was a pleasure to meet you at the Cauldron. On Oct 21, 2022, Qing Zhao wrote: > Hi, Alexandre, > Could you please explain a little bit on the motivation of this patch first? It was a suggestion I got after the Cauldron presentation. It made sense to me, and was easy enough to

[PATCH] RISC-V: ADJUST_NUNITS according to -march.

From: Ju-Zhe Zhong This patch fixed PR107357: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357 gcc/ChangeLog: * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Set to minimum size. (ADJUST_NUNITS): Adjust according to -march. (ADJUST_BYTESIZE): Ditto. * config

[r13-3463 Regression] FAIL: gcc.target/i386/builtin_target.c (test for excess errors) on Linux/x86_64

On Linux/x86_64, f751bf4c5d1aaa1aacfcbdec62881c5ea1175dfb is the first bad commit commit f751bf4c5d1aaa1aacfcbdec62881c5ea1175dfb Author: Martin Liska Date: Mon Oct 24 15:34:39 2022 +0200 x86: fix VENDOR_MAX enum value caused FAIL: gcc.target/i386/builtin_target.c (test for excess errors

[PATCH][pushed] i386: fix pedantic warning

Pushed. Sorry for the stupid error, I noticed the test became UNRESOLVED, but I forgot to investigate that. Cheers, Martin PR target/107364 gcc/ChangeLog: * common/config/i386/i386-cpuinfo.h (enum processor_vendor): Fix pedantic warning. --- gcc/common/config/i386/i386-

Re: [PATCH] [x86_64] Zhaoxin lujiazui enablement

Hello. I noticed this patch set which is kind of related to https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107364. And I have a couple of questions: 1) I noticed you drop AVX and F16C features for the newly added "lujiazui". Why do you need it? I would expect these features would be properly

[PATCH] riscv: fix cross compiler

More riscv_get_valid_option_values out of Fixes: riscv/riscv-common.cc:1748:40: error: ‘riscv_get_valid_option_values’ was not declared in this scope Now I get: ./xgcc -B. --completion=-mcp -mcpu=sifive-e20 -mcpu=sifive-e21 -mcpu=sifive-e24 -mcpu=sifive-e31 -mcpu=sifive-e34 -mcpu=sifive-e76 -mc

Re: [PATCH] riscv: fix cross compiler

On 10/25/22 07:01, Martin Liška wrote: > |More riscv_get_valid_option_values out of| * Move

Re: [PATCH] riscv: fix cross compiler

Ok, thanks for the fix! Martin Liška 於 2022年10月25日 週二 13:02 寫道： > On 10/25/22 07:01, Martin Liška wrote: > > |More riscv_get_valid_option_values out of| > > * Move >

Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT

On Mon, Oct 24, 2022 at 2:20 PM Kong, Lingling wrote: > > > From: Gcc-patches > > On Behalf Of Hongtao Liu via Gcc-patches > > Sent: Monday, October 17, 2022 1:47 PM > > To: Jiang, Haochen > > Cc: Liu, Hongtao ; gcc-patches@gcc.gnu.org > > Subject: Re: [PATCH 4/6] Support Intel AVX-NE-CONVERT >

Re: vect: Fix wrong shift_n after widening on BE [PR107338]

on 2022/10/24 20:55, Richard Biener wrote: > On Mon, Oct 24, 2022 at 12:43 PM Kewen.Lin wrote: >> >> Hi, >> >> As PR107338 shows, with the use of widening loads, the >> container_type can become a wider type, it causes us to >> get wrong shift_n since the BIT_FIELD_REF offset actually >> becomes b

Re: [PATCH] ix86: Suggest unroll factor for loop vectorization

Any comments? On Mon, Oct 24, 2022 at 10:46 AM Cui,Lili via Gcc-patches wrote: > > Hi Hongtao, > > This patch introduces function finish_cost and > determine_suggested_unroll_factor for x86 backend, to make it be > able to suggest the unroll factor for a given loop being vectorized. > Referring t

[PATCH] RISC-V: Recognized Svinval and Svnapot extensions

gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Add svinval and svnapot extension. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_SVINVAL): New. (MASK_SVNAPOT): Ditto. (TARGET_SVINVAL): Ditto.

Re: [PATCH v2] Always use TYPE_MODE instead of DECL_MODE for vector field

On Mon, Oct 24, 2022 at 10:02 PM H.J. Lu wrote: > > On Mon, Oct 24, 2022 at 12:12 AM Richard Biener > wrote: > > > > On Fri, Oct 21, 2022 at 6:18 PM H.J. Lu wrote: > > > > > > On Fri, Oct 21, 2022 at 2:33 AM Richard Biener > > > wrote: > > > > > > > > On Thu, Oct 20, 2022 at 6:58 PM H.J. Lu via

Ping [PATCH] Add condition coverage profiling

On 12/10/2022 12:16, Jørgen Kvalsvik wrote: > This patch adds support in gcc+gcov for modified condition/decision > coverage (MC/DC) with the -fprofile-conditions flag. MC/DC is a type of > test/code coverage and it is particularly important in the avation and > automotive industries for safety-cri