On Mon, Oct 24, 2022 at 11:01 AM Haochen Jiang <haochen.ji...@intel.com> wrote:
>
> Hi all,
>
> I just refined CMPccXADD patch to make the enum in order intrin file
> aligned with how opcode does.
>
> Ok for trunk?
>
> BRs,
> Haochen
>
> gcc/ChangeLog:
>
> * common/config/i386/cpuinfo.h (get_available_features):
> Detect cmpccxadd.
> * common/config/i386/i386-common.cc
> (OPTION_MASK_ISA2_CMPCCXADD_SET,
> OPTION_MASK_ISA2_CMPCCXADD_UNSET): New.
> (ix86_handle_option): Handle -mcmpccxadd, unset cmpccxadd when avx2
> is disabled.
> * common/config/i386/i386-cpuinfo.h (enum processor_features):
> Add FEATURE_CMPCCXADD.
> * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
> cmpccxadd.
> * config.gcc: Add cmpccxaddintrin.h.
> * config/i386/cpuid.h (bit_CMPCCXADD): New.
> * config/i386/i386-builtin-types.def:
> Add DEF_FUNCTION_TYPE(INT, PINT, INT, INT, INT)
> and DEF_FUNCTION_TYPE(LONGLONG, PLONGLONG, LONGLONG, LONGLONG, INT).
> * config/i386/i386-builtin.def (BDESC): Add new builtins.
> * config/i386/i386-c.cc (ix86_target_macros_internal): Define
> __CMPCCXADD__.
> * config/i386/i386-expand.cc (ix86_expand_special_args_builtin):
> Add new parameter to indicate constant position.
> Handle INT_FTYPE_PINT_INT_INT_INT
> and LONGLONG_FTYPE_PLONGLONG_LONGLONG_LONGLONG_INT.
> * config/i386/i386-isa.def (CMPCCXADD): Add DEF_PTA(CMPCCXADD).
> * config/i386/i386-options.cc (isa2_opts): Add -mcmpccxadd.
> (ix86_valid_target_attribute_inner_p): Handle cmpccxadd.
> * config/i386/i386.opt: Add option -mcmpccxadd.
> * config/i386/sync.md (cmpccxadd_<mode>): New define insn.
> * config/i386/x86gprintrin.h: Include cmpccxaddintrin.h.
> * doc/extend.texi: Document cmpccxadd.
> * doc/invoke.texi: Document -mcmpccxadd.
> * doc/sourcebuild.texi: Document target cmpccxadd.
> * config/i386/cmpccxaddintrin.h: New file.
>
> gcc/testsuite/ChangeLog:
>
> * g++.dg/other/i386-2.C: Add -mcmpccxadd.
> * g++.dg/other/i386-3.C: Ditto.
> * gcc.target/i386/avx-1.c: Add builtin define for enum.
> * gcc.target/i386/funcspec-56.inc: Add new target attribute.
> * gcc.target/i386/sse-13.c: Add builtin define for enum.
> * gcc.target/i386/sse-23.c: Ditto.
> * gcc.target/i386/x86gprintrin-1.c: Add -mcmpccxadd for 64 bit target.
> * gcc.target/i386/x86gprintrin-2.c: Add -mcmpccxadd for 64 bit target.
> Add builtin define for enum.
> * gcc.target/i386/x86gprintrin-3.c: Add -mcmpccxadd for 64 bit target.
> * gcc.target/i386/x86gprintrin-4.c: Add mcmpccxadd for 64 bit target.
> * gcc.target/i386/x86gprintrin-5.c: Add mcpmccxadd for 64 bit target.
> Add builtin define for enum.
> * gcc.target/i386/cmpccxadd-1.c: New test.
> * gcc.target/i386/cmpccxadd-2.c: New test.
> ---
> gcc/common/config/i386/cpuinfo.h | 2 +
> gcc/common/config/i386/i386-common.cc | 15 ++
> gcc/common/config/i386/i386-cpuinfo.h | 1 +
> gcc/common/config/i386/i386-isas.h | 1 +
> gcc/config.gcc | 3 +-
> gcc/config/i386/cmpccxaddintrin.h | 89 +++++++++++
> gcc/config/i386/cpuid.h | 1 +
> gcc/config/i386/i386-builtin-types.def | 4 +
> gcc/config/i386/i386-builtin.def | 4 +
> gcc/config/i386/i386-c.cc | 2 +
> gcc/config/i386/i386-expand.cc | 22 ++-
> gcc/config/i386/i386-isa.def | 1 +
> gcc/config/i386/i386-options.cc | 4 +-
> gcc/config/i386/i386.opt | 5 +
> gcc/config/i386/sync.md | 42 ++++++
> gcc/config/i386/x86gprintrin.h | 2 +
> gcc/doc/extend.texi | 5 +
> gcc/doc/invoke.texi | 10 +-
> gcc/doc/sourcebuild.texi | 3 +
> gcc/testsuite/g++.dg/other/i386-2.C | 2 +-
> gcc/testsuite/g++.dg/other/i386-3.C | 2 +-
> gcc/testsuite/gcc.target/i386/avx-1.c | 4 +
> gcc/testsuite/gcc.target/i386/cmpccxadd-1.c | 61 ++++++++
> gcc/testsuite/gcc.target/i386/cmpccxadd-2.c | 138 ++++++++++++++++++
> gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +
> gcc/testsuite/gcc.target/i386/sse-13.c | 6 +-
> gcc/testsuite/gcc.target/i386/sse-23.c | 6 +-
> .../gcc.target/i386/x86gprintrin-1.c | 2 +-
> .../gcc.target/i386/x86gprintrin-2.c | 6 +-
> .../gcc.target/i386/x86gprintrin-3.c | 2 +-
> .../gcc.target/i386/x86gprintrin-4.c | 2 +-
> .../gcc.target/i386/x86gprintrin-5.c | 6 +-
> gcc/testsuite/lib/target-supports.exp | 10 ++
> 33 files changed, 450 insertions(+), 15 deletions(-)
> create mode 100644 gcc/config/i386/cmpccxaddintrin.h
> create mode 100644 gcc/testsuite/gcc.target/i386/cmpccxadd-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/cmpccxadd-2.c
+;; CMPCCXADD
+
+(define_insn "@cmpccxadd_<mode>_1"
+ [(set (match_operand:SWI48x 1 "register_operand" "+r")
+ (match_operand:SWI48x 0 "memory_operand" "+m"))
+ (set (match_dup 0)
+ (unspec_volatile:SWI48x
+ [(match_dup 0)
+ (match_dup 1)
+ (match_operand:SWI48x 2 "register_operand" "r")
+ (match_operand:SI 3 "const_0_to_15_operand" "n")]
+ UNSPECV_CMPCCXADD))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_CMPCCXADD && TARGET_64BIT"
+{
IMO, the above should be defined much like the existing cmpxchg
pattern (see atomic_compare_and_swap<mode>_1 named pattern), where the
memory operand is updated like the one in xadd pattern
(atomic_fetch_add<mode> named pattern). The above "+r" is not needed
when matched operands are used (see mentioned two patterns). Using
this approach, the expander won't be needed as well, since reload will
take care of the correct input/output operand matching.
Uros.
