[PATCH] Optimize vpermtiw/b to vpunpcklqdq for certain cases.

Assembly Optimization like: - vmovq %xmm0, %xmm2 - vmovdqa .LC0(%rip), %xmm0 vmovq %xmm1, %xmm1 - vpermi2w%xmm1, %xmm2, %xmm0 + vmovq %xmm0, %xmm0 + vpunpcklqdq %xmm1, %xmm0, %xmm0 ... -.LC0: - .value 0 - .value 1 - .valu

Re: [PATCH] Avoid visiting newly-created blocks in harden-conditionals

On May 12, 2022, Richard Biener wrote: > Note you are relying on an implementation detail here, it might be > better to mark blocks visited or iterate over the CFG in a more > defined manner *nod*, I was wondering whether that property could be relied on. I also see BB_NEW set in bb->flags in t

[PATCH] Fix wrong SRA with VIEW_CONVERT_EXPR and reverse SSO

Hi, most cases of VIEW_CONVERT_EXPRs involving reverse scalar storage order are disqualified for SRA because they are storage_order_barrier_p, but you can still have a VIEW_CONVERT_EXPR to a regular composite type being applied to a component of a record type with reverse scalar storage order, alt

[Ada] Ineffective use type clause warnings cause compile time crash

This patch corrects an error in the compiler whereby the presence of a generic instance featuring a use type clause at library level may cause a crash at compile time when warnings for ineffective use clauses are enabled and the type in question is already use visible. Tested on x86_64-pc-linux-gn

[Ada] Remove redundant guard in checks for volatile actuals

When flagging names of volatile objects occurring in actual parameters we guard against identifiers without entity. This is redundant, because earlier in the resolution of actual parameters we already guard against actuals with Any_Type. Code cleanup related to handling of volatile components; beh

[Ada] Accept effectively volatile components in actuals

In SPARK we forbid names that are effectively volatile for reading if they occur in actual subprogram parameters. We wrongly rejected references to components, which are not names in Ada. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * sem_res.adb (Flag_Effectively_Volatile_

[Ada] Spurious access error in function returning type with access discriminant

This patch fixes an issue in the compiler whereby incorrect accessibility checks were generated in functions returning types with unconstrained access discriminants when the value supplied for the discriminant is a formal parameter. More specifically, accessibility checks for return statements fea

[Ada] Fix the Ada 2022 iterated component association RM reference

Fix the error message pointing to the Ada reference section on mixed iterated component association being forbidden. Remove useless loop. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * sem_aggr.adb (Resolve_Array_Aggregate): Fix ARM reference. Remove useless loop.d

[Ada] Remove obsolete uses of Unchecked_Deallocation from Ada 83

In Ada 83 the Unchecked_Deallocation was a top-level unit; since Ada 95 it is an obsolete renaming of Ada.Unchecked_Deallocation. GNAT doesn't yet warn about uses of these obsolete renamings, but it still seems better to avoid them. Cleanup before adding a new instance of Unchecked_Deallocation. O

[Ada] Fix compiler crash on FOR iteration scheme over container

The front-end drops a freeze node on the floor because it puts the node into the Condition_Actions of an N_Iteration_Scheme of a FOR loop. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * exp_util.adb (Insert_Actions) : Check that it is a WHILE iteration scheme before

[Ada] Remove obsolete uses of Unchecked_Conversion from Ada 83

Similar to a recent removal of obsolete uses of Unchecked_Deallocation. In Ada 83 the Unchecked_Conversion was a top-level unit; since Ada 95 it is an obsolete renaming of Ada.Unchecked_Conversion. GNAT doesn't warn yet about uses of these obsolete renamings, but it still seems better to avoid the

[Ada] Improve expected type error messages

This patch improves error messages concerning type mismatches by printing the actual expected type in more cases instead of the expected type's first subtype. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * sem_util.adb (Wrong_Type): Avoid using the first subtype of

[Ada] Crash in task body reference to discriminant

The compiler may crash processing the successor or predecessor of a task type discrete discriminant. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * sem_attr.adb (Resolve_Attribute): Ensure that attribute expressions are resolved at this stage; required for preanalyz

[Ada] Wrong address for class-wide interface access conversion

The compiler generates wrong code on instantiations of package Address_To_Access_Conversions when the generic formal is a class-wide interface type; this causes wrong dispatching calls when the access-to-class-wide-interface object returned by To_Pointer is used to dispatch a call. Tested on x86_6

[Ada] Document control flow redundancy

Add documentation about -fharden-control-flow-redundancy. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * doc/gnat_rm/security_hardening_features.rst: Add subsection on Control Flow Redundancy. * gnat_rm.texi: Regenerate.diff --git a/gcc/ada/doc/gnat_rm/secur

[Ada] Do not overwrite limited view of result type

This removes obsolete code that overwrites a limited view present as the result type of a function during the tentative analysis of prefixed views for function calls involving tagged types. The original view is necessary for the code generator to break the circularity present in this setup. The ch

[PATCH] Do not use DW_OP_not for TRUTH_NOT_EXPR in conditional expressions

Hi, DW_OP_not is a bitwise, not a logical NOT, so it computes the wrong result in a DWARF conditional expression. Tested (GCC + GDB° on x86-64/Linux, OK for the mainline? 2022-05-13 Eric Botcazou * dwarf2out.c (loc_list_from_tree_1) : Swap the operands if the condition is a

[Ada] Fix code example on representation clause

The column is superfluous, component names are missing. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * doc/gnat_rm/representation_clauses_and_pragmas.rst: Fix code snippet. * gnat_rm.texi: Regenerate.diff --git a/gcc/ada/doc/gnat_rm/representation_clauses_an

[Ada] Facilitate proof of Overwrite in bounded strings library

Consistently use >= operator in both the code and contracts of function/procedure Overwrite, to facilitate proof, instead of the strict inequality > sometimes, as only New_Item remains in the result in the case of equal size too. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/

[Ada] Handle IN iterator for class-wide derived object of iterator type

The compiler currently rejects iterating on an interface type derived from an iterator type. See Ada RM 5.5.1(6/3) and 5.5.2(3/3). Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * sem_ch5.adb (Analyze_Iterator_Specification): Fix Typ in the case of a class-wide deriv

[Ada] Implement late initialization rules for type extensions

Default initialization of a record object is required to initialize any components that "require late initialization" after other components. This includes the case of a type extension; "late initialization" components of the parent type are required to be initialized after non-late-init extension

[Ada] Take into account GNSA_ROOT env var for prefix

The GNSA_ROOT environment variable can be used to indicate to the compiler how to find the runtime directory. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * osint.ads, osint.adb (Relocate_Path): If the GNSA_ROOT environment variable is set, we use that as the prefix

[Ada] Ada ABI change when building with assertions

Compiling with and without assertions enabled the name of some generated symbols differ; this is an issue when using pre-built libraries. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * freeze.adb (Check_Inherited_Conditions): Dispatch table wrappers must be placed i

[Ada] Remove dependency on tampering checks and controlled types for formal

Formal hashed sets and maps are now using a different type of hash table that does not require controlled types. This is possible because formal containers do not rely on tampering checks, as cursors do not hold a pointer to a single matching container, but are logical indexes that can be used with

[Ada] Adapt body of formal sets and maps for SPARK

Remove violations of SPARK rules, to prepare for the proof of hashed sets and maps: - Make the type of hash tables not tagged, so that it will be possible to mark the type of nodes as having relaxed initialization. - Remove comparison of addresses as check or optimization: as a check, it is n

[Ada] Simplify helper units for formal hashed sets/maps

As tampering checks do not exist in formal hashed sets and maps, remove the machinery for such checks in the version of generic key and node operations for formal sets/maps. Update comments as well. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * libgnat/a-chtgfk.adb (Checke

[Ada] Fix iterated component association for array aggregate

Create a scope for the Ada 2022 iterated component association loops. In the case of elements needing finalization, the late expansion would crash on references to the loop variable within the loop body. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * exp_aggr.adb (Gen_Loop)

[Ada] Extend hardcfr testing (documentation)

Having realized that noreturn calls of __builtin_return are special, and other noreturn calls don't get edges to the exit block, I've realized the consequences of the logic to insert checking before noreturn and tail calls were not quite what I'd expected before. Specifically, noreturn calls other

[Ada] CUDA: use binder to generate kernel-registration code

Compiling CUDA code requires compiling code for the host (= CPU) and for the device (= GPU). Device code is embedded into the host code and must be registered with the CUDA runtime by the host. The original approach we took for registering CUDA kernels was to generate the registration-code on a un

[Ada] Only use alternate stack when needed

If we're not going to install a signal handler for SIGSEGV then we do not need an alternate stack to handle this signal (and e.g. stack overflows). Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * libgnarl/s-taprop__linux.adb (Initialize): Do not use an alternate stac

[Ada] Storage_Model_Object fails to return object entity

After a compilation unit containing a Designated_Storage_Model aspect was processed by the compiler front end, the aspect's expression was seen as not having been analyzed. In some cases this can lead to the Storage_Model_Object function not returning the entity of the associated model object (such

[Ada] Fix incorrect call to inherited function with limited return type

This is a return convention mismatch coming from a discrepancy of the Returns_By_Ref flag for the inherited function. Tested on x86_64-pc-linux-gnu, committed on trunk gcc/ada/ * sem_ch3.adb (Derive_Subprogram): For a function, also copy the Returns_By_Ref flag from the parent.di

Re: [PATCH] Avoid visiting newly-created blocks in harden-conditionals

On Fri, May 13, 2022 at 9:47 AM Alexandre Oliva wrote: > > On May 12, 2022, Richard Biener wrote: > > > Note you are relying on an implementation detail here, it might be > > better to mark blocks visited or iterate over the CFG in a more > > defined manner > > *nod*, I was wondering whether that

Re: [PATCH] Fix wrong SRA with VIEW_CONVERT_EXPR and reverse SSO

On Fri, May 13, 2022 at 9:57 AM Eric Botcazou via Gcc-patches wrote: > > Hi, > > most cases of VIEW_CONVERT_EXPRs involving reverse scalar storage order are > disqualified for SRA because they are storage_order_barrier_p, but you can > still have a VIEW_CONVERT_EXPR to a regular composite type bei

Re: [PATCH] Optimize vpermtiw/b to vpunpcklqdq for certain cases.

On Fri, May 13, 2022 at 9:16 AM liuhongt wrote: > > Assembly Optimization like: > - vmovq %xmm0, %xmm2 > - vmovdqa .LC0(%rip), %xmm0 > vmovq %xmm1, %xmm1 > - vpermi2w%xmm1, %xmm2, %xmm0 > + vmovq %xmm0, %xmm0 > + vpunpcklqdq %xmm1, %xmm0, %xm

Re: [PATCH] Do not use DW_OP_not for TRUTH_NOT_EXPR in conditional expressions

On Fri, May 13, 2022 at 10:21 AM Eric Botcazou via Gcc-patches wrote: > > Hi, > > DW_OP_not is a bitwise, not a logical NOT, so it computes the wrong result in > a DWARF conditional expression. > > Tested (GCC + GDB° on x86-64/Linux, OK for the mainline? But this doesn't fix case TRUTH_NOT_E

Re: [PATCH v2] RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO

+Jakub Jelinek Jakub, I see you have recently worked on lib/target-support.exp: could you do the review of that part? Thanks, Philipp. On Fri, 13 May 2022 at 00:36, Palmer Dabbelt wrote: > > On Thu, 12 May 2022 11:33:34 PDT (-0700), philipp.toms...@vrull.eu wrote: > > The Zbb support has intro

RE: [PATCH] Optimize vpermtiw/b to vpunpcklqdq for certain cases.

> -Original Message- > From: Uros Bizjak > Sent: Friday, May 13, 2022 4:15 PM > To: Liu, Hongtao > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH] Optimize vpermtiw/b to vpunpcklqdq for certain cases. > > On Fri, May 13, 2022 at 9:16 AM liuhongt wrote: > > > > Assembly Optimization

Re: [PATCH] Optimize vpermtiw/b to vpunpcklqdq for certain cases.

On Fri, May 13, 2022 at 10:54 AM Liu, Hongtao wrote: > > > > > -Original Message- > > From: Uros Bizjak > > Sent: Friday, May 13, 2022 4:15 PM > > To: Liu, Hongtao > > Cc: gcc-patches@gcc.gnu.org > > Subject: Re: [PATCH] Optimize vpermtiw/b to vpunpcklqdq for certain cases. > > > > On Fr

Re: [PATCH] Do not use DW_OP_not for TRUTH_NOT_EXPR in conditional expressions

> But this doesn't fix > > case TRUTH_NOT_EXPR: > case BIT_NOT_EXPR: > op = DW_OP_not; > goto do_unop; Nope (I couldn't trigger it after my change). > I also wonder where we get the TRUTH_NOT_EXPR to expand from? I suspect > some non-gimplified global tree? Yes, it's in the

Re: [PATCH] Fix wrong SRA with VIEW_CONVERT_EXPR and reverse SSO

> OK. Possibly also qualifies for the branch(es) as wrong-code fix. Thanks. It's not a regression, but I can indeed put in on recent branches. -- Eric Botcazou

Re: [PATCH] Do not use DW_OP_not for TRUTH_NOT_EXPR in conditional expressions

On Fri, May 13, 2022 at 10:25:02AM +0200, Richard Biener via Gcc-patches wrote: > On Fri, May 13, 2022 at 10:21 AM Eric Botcazou via Gcc-patches > wrote: > > > > Hi, > > > > DW_OP_not is a bitwise, not a logical NOT, so it computes the wrong result > > in > > a DWARF conditional expression. > > >

[PATCH v2] Optimize vpermtiw/b to vpunpcklqdq for certain cases.

Here's updated patch which adds ix86_pre_reload_split () to those 2 define_insn_and_splits. Assembly Optimization like: - vmovq %xmm0, %xmm2 - vmovdqa .LC0(%rip), %xmm0 vmovq %xmm1, %xmm1 - vpermi2w%xmm1, %xmm2, %xmm0 + vmovq %xmm0, %xmm0 + vpun

Re: [PATCH 1/2] xtensa: Rename deprecated extv/extzv insn patterns to extvsi/extzvsi

On Fri, May 6, 2022 at 3:37 AM Takayuki 'January June' Suwa via Gcc-patches wrote: > > These patterns were deprecated since GCC 4.8. > > gcc/ChangeLog: > > * config/xtensa/xtensa.md (extvsi, extvsi_internal, extzvsi, > extzvsi_internal): Rename from extv, extv_internal, extzv and >

Re: [Ada] Introduce hardbool Machine_Attribute for Ada

On May 12, 2022, Pierre-Marie de Rodat wrote: > Implement and document hardened booleans, from nonstandard boolean types > with representation clauses to the extra validity checking performed on > boolean types annotated with the "hardbool" Machine_Attribute pragma. And here is a test for testsu

[PATCH] ada: gcc-if: build proper String_Pointer for Get_External_Name

The compiler is allowed to assume it can access String bounds, such as the prefix passed to Get_External_Name, even in circumstances in which the prefix is not going to be used and has_prefix is false, so, from the C side, we have to build a proper String_Template for the String_Pointer. Regstra

Re: [PATCH 2/2] xtensa: Reflect the 32-bit Integer Divide Option

On Fri, May 6, 2022 at 3:36 AM Takayuki 'January June' Suwa via Gcc-patches wrote: > > On Espressif's ESP8266 (based on Tensilica LX106, no hardware divider), > this patch reduces the size of each: > >__moddi3() @ libgcc.a : 969 -> 301 (saves 668) >__divmoddi4() : -> 426 (sav

[x86 PATCH take 2] Improved V1TI (and V2DI) mode equality/inequality.

Hi Uros, Now that we're back in stage 1, here's the revised version of the patch I submitted here: https://gcc.gnu.org/pipermail/gcc-patches/2022-April/593434.html incorporating all the suggested improvements from your review here: https://gcc.gnu.org/pipermail/gcc-patches/2022-April/593454.html

[PATCH] Add MIN/MAX folding from fold_cond_expr_with_comparison to match.pd

The following adds MIN/MAX folding from fold_cond_expr_with_comparison to the part GIMPLE of match.pd, leaving the GENERIC part in fold-const.cc since that's constrainted on frontend specific things I did not want to carry to match.pd. The effect becomes appearant when we no longer can rely on GEN

Re: Supporting RISC-V Vendor Extensions in the GNU Toolchain

On Wed, May 11, 2022 at 2:02 AM Palmer Dabbelt wrote: > > [Sorry for cross-posting to a bunch of lists, I figured it'd be best to > have all the discussions in one thread.] > > We currently only support what is defined by official RISC-V > specifications in the various GNU toolchain projects. The

[PATCH] Fix OMP CAS expansion with separate condition

When forcing the condition to be split out from COND_EXPRs I see a runtime failure of libgomp.fortran/atomic-19.f90 which can be reduced to !$omp atomic update, compare, capture if (x == 69_2 - r) x = 6_8 v = x being miscompiled, the difference being - _13 = .ATOMIC_COMPARE_EXCHANGE (_9

[committed 1/2] arm: fix some issues in mve_vector_mem_operand

There are a couple of issues with the mve_vector_mem_operand function. Firstly, SP is permitted as a register provided there is no write-back operation. Secondly, there were some cases where 'strict' was not being applied when checking which registers had been used. gcc/ChangeLog: * con

[committed 2/2] arm: correctly handle misaligned MEMs on MVE [PR105463]

Vector operations in MVE must be aligned to the element size, so if we are asked for a misaligned move in a wider mode we must recast it to a form suitable for the known alignment (larger elements have better address offset ranges, so there is some advantage to using wider element sizes if possibl

Re: [PATCH V2] powerpc: properly check for feenableexcept() on FreeBSD

On 22-05-13 10:59:59, Kewen.Lin wrote: > on 2022/5/13 04:16, Segher Boessenkool wrote: > > Hi Piotr, > > > > On Tue, May 03, 2022 at 12:21:12PM +0200, pku...@freebsd.org wrote: > >> FreeBSD/powerpc* has feenableexcept() defined in fenv.h header. > > > > Declared, not defined. These are required

Re: Supporting RISC-V Vendor Extensions in the GNU Toolchain

On Fri, 13 May 2022 at 12:00, Christoph Müllner wrote: > > On Wed, May 11, 2022 at 2:02 AM Palmer Dabbelt wrote: > > > > [Sorry for cross-posting to a bunch of lists, I figured it'd be best to > > have all the discussions in one thread.] > > > > We currently only support what is defined by offici

Re: [PATCH] Avoid visiting newly-created blocks in harden-conditionals

On May 13, 2022, Richard Biener wrote: > Yeah, I'm not sure who clears that bit - grepping shows no user > besides the setter... *nod*, that's what I'd found out myself. Oh well... >> Though I suppose it might be useful to document and enforce the property >> that a newly-created block takes u

Re: Supporting RISC-V Vendor Extensions in the GNU Toolchain

* Christoph Müllner via Binutils: > I'd like to add two points to this topic and raise two questions. > > 1) Accepting vendor extensions = avoidance of fragmentation > > RISC-V implementors are actively encouraged to implement their > own ISA extensions. To avoid fragmentation in the SW ecosystem

Re: [PATCH] [Middle-end] Enhance final_value_replacement_loop to handle bitwise induction.

On Fri, May 13, 2022 at 5:37 AM Hongtao Liu wrote: > > On Wed, May 11, 2022 at 4:45 PM Richard Biener via Gcc-patches > wrote: > > > > On Mon, May 9, 2022 at 7:19 AM liuhongt wrote: > > > > > > This patch will enable below optimization: > > > > > > { > > > - int bit; > > > - long long unsigne

Re: Supporting RISC-V Vendor Extensions in the GNU Toolchain

On Fri, 13 May 2022 at 12:58, Florian Weimer wrote: > > * Christoph Müllner via Binutils: > > > I'd like to add two points to this topic and raise two questions. > > > > 1) Accepting vendor extensions = avoidance of fragmentation > > > > RISC-V implementors are actively encouraged to implement the

[PATCH] [i386] Fix ICE caused by wrong condition.

When d->perm[i] == d->perm[i-1] + 1 and d->perm[i] == nelt, it's not continuous. It should fail if there's more than 2 continuous areas. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR target/105587 * config/i386/i386-expand.cc (

libgomp nvptx plugin: Only consider '--with-cuda-driver=[...]' when applicable

Hi! Another small one: On 2022-05-12T14:39:14+0200, I wrote: > Again, no change in behavior, just refactoring, making things more > explicit, in preparation for other changes. > "Refactor '-ldl' handling for libgomp proper and plugins"? > --- a/libgomp/plugin/Makefrag.am > +++ b/libgomp/plugin/

Re: Supporting RISC-V Vendor Extensions in the GNU Toolchain

On Fri, May 13, 2022 at 12:58 PM Florian Weimer wrote: > > * Christoph Müllner via Binutils: > > > I'd like to add two points to this topic and raise two questions. > > > > 1) Accepting vendor extensions = avoidance of fragmentation > > > > RISC-V implementors are actively encouraged to implement

libgomp nvptx plugin: Remove '--with-cuda-driver=[...]' etc. configuration option (was: Proposal to remove '--with-cuda-driver')

Hi! On 2022-04-29T15:48:03+0200, I wrote: > On 2022-04-06T11:57:57+0200, Tom de Vries wrote: >> On 4/5/22 17:14, Thomas Schwinge wrote: >>> Regarding [...] >>> Now, consider doing a GCC/nvptx offloading build with >>> '--with-cuda-driver' [...] >> Thanks for reminding me, I forgot about this co

[committed 01/12] libstdc++: Disable Doxygen GROUP_NESTED_COMPOUNDS config option

Tested powerpc64le-linux, pushed to trunk. -- >8 -- Before Doxygen version 1.9.2 this option is broken (see https://github.com/doxygen/doxygen/issues/8638 for more details) and classes are not added to the correct groups by @ingroup and @addtogroup. Also remove the obsolete CLASS_DIAGRAMS option

[committed 03/12] libstdc++: Add macros for the inline namespace std::_V2

Tested powerpc64le-linux, pushed to trunk. Unlike the rest of the series, this isn't suitable for backporting because it changes the ABI for the gnu-versioned-namespace build. That's fine for GCC 13, but not OK to change within a release branch, e.g. between 12.1 and 12.2. If we want to backport i

[committed 04/12] libstdc++: Improve doxygen docs for std::pointer_traits

Tested powerpc64le-linux, pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * include/bits/ptr_traits.h: Add some doxygen comments. --- libstdc++-v3/include/bits/ptr_traits.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/libstdc++-v3/include/bits/ptr_traits.h b/libstdc++-v3

[committed 02/12] libstdc++: Fix typo in doxygen @headerfile command

Tested powerpc64le-linux, pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * include/bits/mofunc_impl.h: Fix doxygen command. --- libstdc++-v3/include/bits/mofunc_impl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libstdc++-v3/include/bits/mofunc_impl.h b/libst

[committed 07/12] libstdc++: Improve doxygen docs for

Tested powerpc64le-linux, pushed to trunk. -- >8 -- Add @headerfile and @since tags. Improve grouping of non-member functions via @relates tags. Mark the std::pair base class of std::sub_match as undocumented, so that the docs don't show all the related non-member functions are part of the sub_m

[committed 08/12] libstdc++: Improve doxygen docs for std::allocator

Tested powerpc64le-linux, pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * doc/doxygen/user.cfg.in (PREDEFINED): Define __allocator_base so that Doxygen shows the right base-class for std::allocator. * include/bits/alloc_traits.h: Improve doxygen docs. * includ

[committed 05/12] libstdc++: Improve doxygen docs for

Tested powerpc64le-linux, pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * include/std/system_error: Improve doxygen comments. --- libstdc++-v3/include/std/system_error | 136 -- 1 file changed, 107 insertions(+), 29 deletions(-) diff --git a/libstdc++-v3/inc

[committed 10/12] libstdc++: Improve doxygen docs for and

Tested powerpc64le-linux, pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * include/bits/std_thread.h (thread, thread::id): Improve doxygen docs. * include/std/future: Likewise. * include/std/thread (jthread): Likewise. --- libstdc++-v3/include/bits/std_thread.

[committed 06/12] libstdc++: Improve doxygen docs for

Tested powerpc64le-linux, pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * include/std/atomic: Suppress doxygen docs for implementation details. * include/bits/atomic_base.h: Likewise. * include/bits/shared_ptr_atomic.h: Use markdown. Fix grouping so th

[committed 11/12] libstdc++: Improve doxygen docs for some of

Tested powerpc64le-linux, pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * doc/doxygen/user.cfg.in (PREDEFINED): Define _GLIBCXX23_CONSTEXPR macro. * include/backward/auto_ptr.h (auto_ptr): Use @deprecated. * include/bits/unique_ptr.h (default_delete): Use @sin

[committed 09/12] libstdc++: Improve doxygen docs for algorithms and more

Tested powerpc64le-linux, pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * include/bits/ostream_insert.h: Mark helper functions as undocumented by Doxygen. * include/bits/stl_algo.h: Use markdown for formatting and mark helper functions as undocumented.

[committed 12/12] libstdc++: Improve doxygen docs for

Tested powerpc64le-linux, pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * doc/doxygen/user.cfg.in (PREDEFINED): Define _GTHREAD_USE_MUTEX_TIMEDLOCK macro. * include/bits/std_mutex.h (mutex, lock_guard): Use @since and @headerfile. * include/bits/unique

Re: [PATCH V2] powerpc: properly check for feenableexcept() on FreeBSD

On Fri, May 13, 2022 at 12:34:05PM +0200, Piotr Kubaj wrote: > On 22-05-13 10:59:59, Kewen.Lin wrote: > > on 2022/5/13 04:16, Segher Boessenkool wrote: > > > On Tue, May 03, 2022 at 12:21:12PM +0200, pku...@freebsd.org wrote: > > >> FreeBSD/powerpc* has feenableexcept() defined in fenv.h header. >

Re: libgompd: ADD OMPD support and global ICV functions

On Tue, May 10, 2022 at 07:40:41AM +0200, Mohamed Atef wrote: > --- a/libgomp/env.c > +++ b/libgomp/env.c > @@ -33,6 +33,7 @@ > #ifndef LIBGOMP_OFFLOADED_ONLY > #include "libgomp_f.h" > #include "oacc-int.h" > +#include "ompd-support.h" > #include > #include > #include > @@ -89,6 +90,7 @@

Re: [PATCH v4, rs6000] Add a combine pattern for CA minus one [PR95737]

Hi! On Fri, May 13, 2022 at 09:07:54AM +0800, HAO CHEN GUI wrote: >This patch adds a combine pattern for "CA minus one". As CA only has two > values (0 or 1), we could convert following pattern > (sign_extend:DI (plus:SI (reg:SI 98 ca) > (const_int -1 [0x]

Re: [PATCH v4, rs6000] Add a combine pattern for CA minus one [PR95737]

Hi! On Fri, May 13, 2022 at 10:40:22AM +0800, Kewen.Lin wrote: > on 2022/5/13 09:07, HAO CHEN GUI wrote: > > * config/rs6000/rs6000.md (extenddi_ca_minus_one): Define. > > Nit: (*extenddi_ca_minus_one): New define_insn_and_split. Or just "New." even :-) It's boring, yes, but boring is good.

[PATCH 1/5] xtensa: Simplify EXTUI instruction maskimm validations

No functional changes. gcc/ChangeLog: * gcc/config/xtensa/predicates.md (extui_fldsz_operand): Simplify. * gcc/config/xtensa/xtensa.cc (xtensa_mask_immediate, print_operand): Ditto. --- gcc/config/xtensa/predicates.md | 2 +- gcc/config/xtensa/xtensa.cc | 24 +++

[PATCH 2/5] xtensa: Make use of IN_RANGE macro where appropriate

No functional changes. gcc/ChangeLog: * gcc/config/xtensa/constraints.md (M, O): Use the macro. * gcc/config/xtensa/predicates.md (addsubx_operand, extui_fldsz_operand, sext_fldsz_operand): Ditto. * gcc/config/xtensa/xtensa.cc (xtensa_simm8, xtensa_simm8x256,

[PATCH 3/5] xtensa: Fix instruction counting regarding block move expansion

This patch makes counting the number of instructions of the remainder (modulo 4) part more accurate. gcc/ChangeLog: * gcc/config/xtensa/xtensa.cc (xtensa_expand_block_move): Make instruction counting more accurate, and simplify emitting insns. --- gcc/config/xtensa/xtensa.cc | 8

[PATCH 4/5] xtensa: Add setmemsi insn pattern

This patch introduces setmemsi insn pattern of two kinds, unrolled loop and small loop, for fixed small length and constant initialization value. gcc/ChangeLog: * gcc/config/xtensa/xtensa-protos.h (xtensa_expand_block_set_unrolled_loop, xtensa_expand_block_set_small_loop)

[PATCH 5/5] xtensa: Improve bswap[sd]i2 insn patterns

This patch makes bswap[sd]i2 better register allocation, and reconstructs bswapsi2 in order to take advantage of GIMPLE manual byte-swapping recognition. gcc/ChangeLog: * gcc/config/xtensa/xtensa.md (bswapsi2): New expansion pattern. (bswapsi2_internal): Revise the template and c

[COMMITTED] Make range_from_dom more effective.

This patch enhances  how ranger's cache picks up ranges from dominators. The previous version was pretty basic, simply walking the DOM tree back until it ran into a "complicated" situation.. (for instance when the dominator has multiple successors)  then falling back to the non-dominator based

[COMMITTED] Clear killing defs when resetting the path in, path_oracle.

When we clear the path in the relation path oracle, we should also reset the killing defs bitmap. Bootstraps on build-x86_64-pc-linux with no regressions.  Pushed. Andrew commit 602a3161f425ee3fe325413eeab9792e8e07a2ff Author: Andrew MacLeod Date: Wed Feb 23 12:25:20 2022 -0500 Clear k

Re: [PATCH v2] RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO

LGTM, thanks :) On Fri, May 13, 2022 at 4:43 PM Philipp Tomsich wrote: > > +Jakub Jelinek > > Jakub, > > I see you have recently worked on lib/target-support.exp: could you do > the review of that part? > > Thanks, > Philipp. > > On Fri, 13 May 2022 at 00:36, Palmer Dabbelt wrote: > > > > On Thu

Re: [PATCH v2] RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO

Oh, one minor comment: > +/* { dg-additional-options "-march=rv64gc_zbb" { target { lp64 && > riscv64*-*-* } } } */ { target { rv64 } here > +/* { dg-additional-options "-march=rv32gc_zbb" { target { ilp32 && > riscv64*-*-* } } } */ and { target { rv32 } here That should make riscv32*-*-* also

Re: [PATCH v2] RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO

On Fri, May 13, 2022 at 09:53:46PM +0800, Kito Cheng wrote: > LGTM, thanks :) > > On Fri, May 13, 2022 at 4:43 PM Philipp Tomsich > wrote: > > I see you have recently worked on lib/target-support.exp: could you do > > the review of that part? Generally, target specific additions to gcc/testsuite

[COMMITTED] Export global ranges during the VRP block walk.

VRP currently searches the ssa_name list for globals to exported after it  finishes running.  This change simply exports globals as they are calculated for the final time during the DOM walk. This avoid the occasional awkwardness of determined what ssa-names in the list are important, as well

Re: [PATCH] [i386] Fix ICE caused by wrong condition.

On Fri, May 13, 2022 at 1:43 PM liuhongt wrote: > > When d->perm[i] == d->perm[i-1] + 1 and d->perm[i] == nelt, it's not > continuous. It should fail if there's more than 2 continuous areas. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ok for trunk? > > > gcc/ChangeLog: > >

c++: Local symbols do not get module manglings

Internal-linkage entity mangling is entirely implementation defined -- there's no ABI issue. Let's not mangle in any module attachment to them, it makes the symbols unnecessarily longer. nathan -- Nathan SidwellFrom 8dc7e0287223bfe48f16cfc10ee87cd5ff05f277 Mon Sep 17 00:00:00 2001 From: Nathan

[COMMITTED] PR tree-optimization/104547 - Add relation between op1 & op2 to lhs_opN_relation API.

We use the relation between op1 and op2 to help fold a statement, but it was not provided to the lhs_op1_relation and lhs_op2_relation routines to determine if is also creates a relation between the LHS and either operand. This patch adds the relation to the API.  It also implelements the basi

[COMMITTED] Fix return value in ranger_cache::get_global_range

This fixes a buglet in get_global_range where it was not returning the correct value. It was returning whether the value was current, not whether it originally had a global value set as it was suppose to.  The current_p flag is returned as a parameter already. Bootstrapped on x86_64-pc-linux-g

[PATCH] Optimize vec_splats of constant V2DI/V2DF vec_extract, PR target/99293

Optimize vec_splats of constant V2DI/V2DF vec_extract, PR target/99293. This patch has been previously posted, but it seemed to get lost.: | Date: Tue, 29 Mar 2022 23:25:31 -0400 | Subject: [PATCH, V2] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293. | Message-ID: | h

[COMMITTED] Add a return value to intersect and speed it up.

This patch optimizes the multi-range intersect routine for irange. It now has a return value which indicates if the intersection changed the range or not. This can be used to short-circuit updating caches and avoiding additional overheads. It also provides/uses a new routine which returns tru

[PATCH] Replace UNSPEC with RTL code for extendditi2.

Replace UNSPEC with RTL code for extendditi2. When I submitted my patch on March 12th for extendditi2, Segher wished I had removed the use of the UNSPEC for the vextsd2q instruction. This patch rewrites extendditi2_vector to use VEC_SELECT rather than UNSPEC. 2022-05-13 Michael Meissner gcc

[COMMITTED] Return a bool result for union, and add performance improvements.

This does the same for union.. adds a return value indicating in the union call changes the range. It adds a routine for efficiency which performs a union between 2 single pairs, the most common case. Improvements are much nominal.. along the 0.1% range, but again, will be utilized by forthc

Re: [AArch64] PR105162: emit barrier for __sync and __atomic builtins on CPUs without LSE

"Pop, Sebastian via Gcc-patches" writes: >> Yes this looks good to me (still needs maintainer approval). > > Thanks again Wilco for your review. > >> One minor nitpick, >> a few of the tests check for __aarch64_cas2 - this should be >> __aarch64_cas2_sync. > > Fixed in the attached patch. > >> N

[COMMITTED] MAINTAINERS: Add myself for write after approval

2022-05-13  Surya Kumari Jangala     * MAINTAINERS: Add myself to write after approval. diff --git a/MAINTAINERS b/MAINTAINERS index a1b84ac5646..8bca7a636b7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -464,6 +464,7 @@ Daniel Jacobowitz  Andreas Jaeger  Harsha Jagasia  Fariborz Jahanian +

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