Re: [PATCH] Don't use nullptr return from simplify_gen_subreg

On Thu, Apr 29, 2021 at 10:22 PM H.J. Lu via Gcc-patches wrote: > > On Thu, Apr 29, 2021 at 8:52 AM Jeff Law wrote: > > > > This change: > > > > 985b3a6837dee7001e6b618f073ed74f0edf5787 is the first bad commit > > commit 985b3a6837dee7001e6b618f073ed74f0edf5787 > > Author: H.J. Lu > > Date: Mo

Re: [PATCH/RFC] Add a new memory gathering optimization for loop (PR98598)

On Thu, Jan 21, 2021 at 7:28 AM Feng Xue OS via Gcc-patches wrote: > > This patch implements a new loop optimization according to the proposal > in RFC given at https://gcc.gnu.org/pipermail/gcc/2021-January/234682.html. > So do not repeat the idea in this mail. Hope your comments on it. > > Boots

回复：About implementation of the Negative property of options.

Thanks for your replies. On Thurs, Apr 29, 2021, utc+8 PM Joseph Myers wrote: Could you please explain the bug at the *user-visible* level? That is, the particular options passed to the compiler, how those options behave, and how you think they should behave instead. This is the real bug I met

[PATCH] i386: Introduce reversed ADC and SBB patterns [PR98060]

The compiler is able to merge LTU comparisons with PLUS or MINUS pattern to form addition with carry (ADC) and subtraction with borrow (SBB) instructions: op = op + carry[ADC $0, op] op = op - carry[SBB $0, op] The patch introduces reversed ADC and SBB insn patterns:

[PATCH] arm: Fix ICE with CMSE nonsecure call on Armv8.1-M [PR100333]

Hi, As the PR shows, we ICE shortly after expanding nonsecure calls for Armv8.1-M. For Armv8.1-M, we have TARGET_HAVE_FPCXT_CMSE. As it stands, the expander (arm.md:nonsecure_call_internal) moves the callee's address to a register (with copy_to_suggested_reg) only if !TARGET_HAVE_FPCXT_CMSE. How

Re: [PATCH] AArch64: Cleanup aarch64_classify_symbol

Wilco Dijkstra via Gcc-patches writes: > Hi Richard, > >> Just to check: I guess this part is an optimisation, because it >> means that we can share the GOT entry with other TUs.  Is that right? >> I think it would be worth having a comment either way, whatever the >> rationale.  A couple of other

Re: [PATCH 01/12] Update alignment_for_piecewise_move

"H.J. Lu via Gcc-patches" writes: > alignment_for_piecewise_move is called only with MOVE_MAX_PIECES or > STORE_MAX_PIECES, which are the number of bytes at a time that we > can move or store efficiently. We should call mode_for_size without > limit to MAX_FIXED_MODE_SIZE, which is an integer exp

Re: [PATCH 02/12] Allow generating pseudo register with specific alignment

"H.J. Lu via Gcc-patches" writes: > gen_reg_rtx tracks stack alignment needed for pseudo registers so that > associated hard registers can be properly spilled onto stack. But there > are cases where associated hard registers will never be spilled onto > stack. gen_reg_rtx is changed to take an a

[RFC] Using main loop's updated IV as base_address for epilogue vectorization

Hi, The aim of this RFC is to explore a way of cleaning up the codegen around data_references.  To be specific, I'd like to reuse the main-loop's updated data_reference as the base_address for the epilogue's corresponding data_reference, rather than use the niters.  We have found this leads t

[PATCH] tree-optimization/96513 - add testcase for fixed bug

This adds a testcase for a bug that was fixed with the hybrid SLP detection rewrite. Tested on x86_64-unknown-linux-gnu, pushed. 2021-04-30 Richard Biener PR tree-optimization/96513 * gcc.dg/torture/pr96513.c: New testcase. --- gcc/testsuite/gcc.dg/torture/pr96513.c | 26

Re: [PATCH] Disable section anchors for VAR_DECLs if -fdata-sections

David Edelsohn via Gcc-patches writes: > -fdata-sections places data symbols into their own, unique, named > sections. > -fsection-anchors create an anchor to access neighboring symbols > within a section. > > When both are enabled, a separate section anchor is created for each >

GCC 9.4 Status Report (2021-04-21)

Status == It's time for the GCC 9.4 release, I therefore plan to do a GCC 9.4 release candidate on May 19th and the release about a week after that if no unforseen problems arise. We have one P1 regression, PR98032 which is a C++ frontend issue. Please make sure to backport regression fixes

Re: [PATCH 02/12] Allow generating pseudo register with specific alignment

On Fri, Apr 30, 2021 at 2:06 AM Richard Sandiford wrote: > > "H.J. Lu via Gcc-patches" writes: > > gen_reg_rtx tracks stack alignment needed for pseudo registers so that > > associated hard registers can be properly spilled onto stack. But there > > are cases where associated hard registers will

Re: [PATCH] AArch64: Cleanup aarch64_classify_symbol

Hi Richard, > Hmm, OK.  I guess it makes things more consistent in that sense > (PIC vs. non-PIC).  But on the other side it's making things less > internally consistent for non-PIC, since we don't use the GOT for > anything else there.  I guess in principle there's a danger that a > custom *-elf

[PATCH] c++/98032 - add testcase

This adds another testcase for PR95719. Tested on x86_64-unknown-linux-gnu, pushed. 2021-04-30 Richard Biener PR c++/98032 * g++.dg/pr98032.C: New testcase. --- gcc/testsuite/g++.dg/pr98032.C | 20 1 file changed, 20 insertions(+) create mode 100644 gcc/

[PATCH] C-SKY: Add fpuv3 instructions and CK860 arch.

gcc/ChangeLog: * config/csky/constraints.md ("W"): New constriant for mem operand with base reg, index register. ("Q"): Renamed and modified "csky_valid_fpuv2_mem_operand" to "csky_valid_mem_constraint_operand" to deal with both "Q" and "W" constraint.

[PATCH "58/57"] rs6000: Avoid problems with undefined decimal float types

On 4/27/21 10:32 AM, Bill Schmidt wrote: The design of the target-specific built-in function support in the Power back end has not stood the test of time. The machinery is grossly inefficient, confusing, and arcane; and adding new built-in functions is inefficient and error-prone. This patch se

[PATCH "59/57"] rs6000: Fix builtins that should have been available everywhere

On 4/27/21 10:32 AM, Bill Schmidt wrote: The design of the target-specific built-in function support in the Power back end has not stood the test of time. The machinery is grossly inefficient, confusing, and arcane; and adding new built-in functions is inefficient and error-prone. This patch se

Re: [PATCH 02/12] Allow generating pseudo register with specific alignment

"H.J. Lu via Gcc-patches" writes: > On Fri, Apr 30, 2021 at 2:06 AM Richard Sandiford > wrote: >> >> "H.J. Lu via Gcc-patches" writes: >> > gen_reg_rtx tracks stack alignment needed for pseudo registers so that >> > associated hard registers can be properly spilled onto stack. But there >> > ar

Re: [PATCH 02/12] Allow generating pseudo register with specific alignment

On Fri, Apr 30, 2021 at 5:42 AM Richard Sandiford wrote: > > "H.J. Lu via Gcc-patches" writes: > > On Fri, Apr 30, 2021 at 2:06 AM Richard Sandiford > > wrote: > >> > >> "H.J. Lu via Gcc-patches" writes: > >> > gen_reg_rtx tracks stack alignment needed for pseudo registers so that > >> > associ

Re: [PATCH] AArch64: Cleanup aarch64_classify_symbol

Wilco Dijkstra via Gcc-patches writes: > Hi Richard, >> Hmm, OK.  I guess it makes things more consistent in that sense >> (PIC vs. non-PIC).  But on the other side it's making things less >> internally consistent for non-PIC, since we don't use the GOT for >> anything else there.  I guess in prin

[PATCH] C-SKY: Delete LO_REGS and HI_REGS, use HILO_REGS instead.

gcc/ChangeLog: * config/csky/constraints.md ("l", "h"): Delete. * config/csky/csky.h (reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Delete LO_REGS and HI_REGS. * config/csky/csky.c (regno_reg_classm, csky_secondary_reload, csky_register_move_cost):

[PATCH] C-SKY: Bug fix for bad setting of TARGET_DSP and TARGET_DIV.

gcc/ChangeLog: * config/csky/csky.c (csky_option_override): Init csky_arch_isa_features[] advanced, so TARGET_DSP and TARGET_DIV can be set well. --- gcc/config/csky/csky.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/gcc/

[PATCH] C-SKY: Separate FRAME_POINTER_REGNUM into FRAME_POINTER_REGNUM and HARD_FRAME_POINTER_REGNUM.

gcc/ChangeLog: * config/csky/csky.h (FRAME_POINTER_REGNUM): Use HARD_FRAME_POINTER_REGNUM and FRAME_POINTER_REGNUM instead of the signle definition. The signle definition may not work well at simplify_subreg_regno(). (ELIMINABLE_REGS): Add for HARD_FRAME_POI

[PATCH] C-SKY: Add insn "ldbs".

gcc/ChangeLog: config/csky/csky.md (cskyv2_sextend_ldbs): New insn. --- gcc/config/csky/csky.md | 10 ++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md index c27d627..b980d4c 100644 --- a/gcc/config/csky/csky.md +++ b/gcc/config/cs

[PATCH] C-SKY: Cases for csky fpuv3 instructions.

gcc/testsuite/ChangeLog: * gcc/testsuite/gcc.target/csky/fpuv3/fpuv3.exp: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_div.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fadd.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fdtos.c: New. * gcc/tests

[PATCH] C-SKY: Use default for TARGET_CAN_CHANGE_MODE_CLASS.

gcc/ChangeLog: * config/csky/csky.c (csky_can_change_mode_class): Delete. For csky, HF/SF mode use the low bits of VREGS. --- gcc/config/csky/csky.c | 16 1 file changed, 16 deletions(-) diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c index 7f2af82..

[PATCH] C-SKY: Fix for gcc.dg/torture/stackalign/builtin-return-2.c.

gcc/ChangeLog: * config/csky/csky.md (untyped_call): Emit clobber for return registers to mark them used. --- gcc/config/csky/csky.md | 4 1 file changed, 4 insertions(+) diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md index b980d4c..f91d851 100644 --- a/gcc/c

[PATCH] C-SKY: Use default for TARGET_PROMOTE_PROTOTYPES.

gcc/ChangeLog: * config/csky/csky.c (TARGET_PROMOTE_PROTOTYPES): Use default. --- gcc/config/csky/csky.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c index 67cdf9c..e4c92fe 100644 --- a/gcc/config/csky/csky.c +++ b/gcc/config/csky/c

[PATCH] C-SKY: Support for fpuv2:fldrd/fstrd and fpuv3:fldr.64/fstr.64.

gcc/ChangeLog: * config/csky/csky.c (ck810_legitimate_index_p): Modified for support "base + index" with DF mode. * config/csky/constraints.md ("Y"): New constraint for memory operands without index register. * config/csky/csky_insn_fpuv2.md (fpuv3_m

[committed] testsuite: Adjust expected error in a testcase [PR98358]

On Fri, Apr 23, 2021 at 05:24:00PM -0400, Jason Merrill via Gcc wrote: > On Fri, Apr 23, 2021 at 7:55 AM Jakub Jelinek wrote: > > > > Status > > == > > > > GCC 8.5 release and closing of the 8 branch is several months overdue, > > we don't have enough time to maintain trunk and 4 supported rel

Re: [PATCH 02/12] Allow generating pseudo register with specific alignment

On Fri, Apr 30, 2021 at 5:49 AM H.J. Lu wrote: > > On Fri, Apr 30, 2021 at 5:42 AM Richard Sandiford > wrote: > > > > "H.J. Lu via Gcc-patches" writes: > > > On Fri, Apr 30, 2021 at 2:06 AM Richard Sandiford > > > wrote: > > >> > > >> "H.J. Lu via Gcc-patches" writes: > > >> > gen_reg_rtx trac

[committed] libstdc++: Define effective-target for net::ip features [PR 100351]

Define a new effective-target keyword so that tests for the Networking TS header can be skipped on targets where none of it can be usefully defined. libstdc++-v3/ChangeLog: PR libstdc++/100180 PR libstdc++/100286 PR libstdc++/100351 * testsuite/experimental/net/in

[committed] libstdc++: Use features conditionally [PR 100285]

This makes the uses of getsockopt and setsockopt in conditional on the availability of . It also fixes a test to check for instead of . libstdc++-v3/ChangeLog: PR libstdc++/100285 * include/experimental/socket (__basic_socket_impl::set_option) (__basic_socket_impl::get_

[committed] libstdc++: Implement LWG 1203 for rvalue iostreams

This implements the resolution of LWG 1203 so that the constraints for rvalue stream insertion/extraction are simpler, and the return type is the original rvalue stream type not its base class. Signed-off-by: Jonathan Wakely libstdc++-v3/ChangeLog: * include/std/istream (operator>>(Istr

[PATCH] testsuite/arm: Add mve-vsub-scalar-1.c test

This patchs adds a test similar to mve-vsub_1.c, but operates on a scalar as second argument. For the moment we do not select the T2 vsub variant operating on a scalar final argument, and we use vadd of the opposite. 2021-04-26 Christophe Lyon gcc/testsuite/ * gcc.target/arm/si

[PATCH] testsuite/arm: Add mve-vmul-scalar-1.c test

Support for vmul has been present for a while, but it was lacking a test for the scalar variant. This patch adds one, precisely noting that we do not yet use the T2 variants of vmul, which take a scalar as final argument. 2021-04-22 Christophe Lyon gcc/testsuite/ * gcc.target/

[PATCH] testsuite/arm: Add mve-vadd-scalar-1.c test

This patch adds a test for the scalar mode of vadd, precisely noting that we do not yet use the T2 variants of vadd, which take a scalar as final argument. 2021-04-22 Christophe Lyon gcc/testsuite/ * gcc.target/arm/simd/mve-vadd-scalar-1: New. --- .../gcc.target/arm/simd/mve-v

[PATCH 1/9] arm: MVE: Convert vcmp[eq|ne]* in arm_mve.h to use only 's' builtin version

There is no need to have a signed and an unsigned version of these builtins. This is similar to what we do for Neon in arm_neon.h. This mechanical patch enables later cleanup patches. 2021-03-01 Christophe Lyon gcc/ * config/arm/arm_mve.h (__arm_vcmpeq*u*, __arm_vcmpne*u*): Cal

[PATCH 2/9] arm: MVE: Cleanup vcmpne/vcmpeq builtins

After the previous patch, we no longer need to emit the unsigned variants of vcmpneq/vcmpeqq. This patch removes them as well as the corresponding iterator entries. 2021-03-01 Christophe Lyon gcc/ * config/arm/arm_mve_builtins.def (vcmpneq_u): Remove. (vcmpneq_n_u): Lik

[PATCH 4/9] arm: MVE: Factorize all vcmp* integer patterns

After removing the signed and unsigned suffixes in the previous patches, we can now factorize the vcmp* patterns: there is no longer an asymmetry where operators do not have the same set of signed and unsigned variants. The will make maintenance easier. MVE has a different set of vector compariso

[PATCH 5/9] arm: MVE: Factorize vcmp_*f*

Like in the previous, we factorize the vcmp_*f* patterns to make maintenance easier. 2021-03-12 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_FP_COMPARISONS): New. * config/arm/mve.md (mve_vcmpq_f) (mve_vcmpq_n_f): New, merge all vcmp_*f* patterns.

[PATCH 3/9] arm: MVE: Remove _s and _u suffixes from vcmp* builtins.

This patch brings more unification in the vector comparison builtins, by removing the useless 's' (signed) suffix since we no longer need unsigned versions. 2021-03-01 Christophe Lyon gcc/ * config/arm/arm_mve.h (__arm_vcmp*): Remove 's' suffix. * config/arm/arm_mve_bui

[PATCH 7/9] arm: Auto-vectorization for MVE: add __fp16 support to VCMP

This patch adds __fp16 support to the previous patch that added vcmp support with MVE. For this we update existing expanders to use VDQWH iterator, and add a new expander vcond. In the process we need to create suitable iterators, and update v_cmp_result as needed. 2021-04-26 Christophe Lyon

[PATCH 6/9] arm: Auto-vectorization for MVE: vcmp

Since MVE has a different set of vector comparison operators from Neon, we have to update the expansion to take into account the new ones, for instance 'NE' for which MVE does not require to use 'EQ' with the inverted condition. Conversely, Neon supports comparisons with #0, MVE does not. For: ty

[PATCH 8/9] arm: Auto-vectorization for MVE: vld2/vst2

This patch enables MVE vld2/vst2 instructions for auto-vectorization. We move the existing expanders from neon.md and enable them for MVE, calling the respective emitter. 2021-03-12 Christophe Lyon gcc/ * config/arm/neon.md (vec_load_lanesoi) (vec_store_lanesoi): Move .

[PATCH 9/9] arm: Auto-vectorization for MVE: vld4/vst4

This patch enables MVE vld4/vst4 instructions for auto-vectorization. We move the existing expanders from neon.md and enable them for MVE, calling the respective emitter. 2021-03-12 Christophe Lyon gcc/ * config/arm/neon.md (vec_load_lanesxi) (vec_store_lanexoi): Move .

Re: [PATCH] testsuite/arm: Improve unsigned-float.c

ping? On Thu, 22 Apr 2021 at 15:32, Christophe Lyon wrote: > > The test requires an FPU, so use -march=armv7-a+fp -mfpu=auto instead > of -march=armv7-a. > > We also remove dg-require-effective-target arm_fp_ok, but keep > dg-add-options arm_fp: this enables the test to pass on arm-eabi > configu

Re: [PATCH] arm: remove error in CPP_SPEC when float-abi soft and hard are used together

ping? On Thu, 22 Apr 2021 at 09:01, Christophe Lyon wrote: > > arm.h has had this error message since 1997, and was never updated to > take softfp into account. Anyway, it seems it was useful long ago, but > it is no longer needed since option parsing has been improved: > -mfloat-abi is handled v

Re: [PATCH] testsuite/arm: Fix and rename arm_qbit_ok into arm_sat_ok effective-target

ping? On Wed, 21 Apr 2021 at 22:48, Christophe Lyon wrote: > > The acle/saturation.c test uses __[su]sat() and > __saturation_occurred() intrinsics but __[su]sat() are defined in > acle.h if __ARM_FEATURE_SAT true, while __saturation_occurred() > depends on __ARM_FEATURE_QBIT. > > QBIT is a v5te

Re: [PATCH 1/20] aarch64: Use RTL builtin for vmull[_high]_p8 intrinsics

Thanks for the review, I've updated the patch as per option 1. Tested and bootstrapped on aarch64-none-linux-gnu with no issues. Ok for master? Thanks, Jonathan From: Richard Sandiford Sent: 28 April 2021 15:11 To: Jonathan Wright via Gcc-patches Cc: Jonathan W

Re: [PATCH 10/20] aarch64: Use RTL builtins for FP ml[as]_n intrinsics

Patch updated as per your suggestion. Tested and bootstrapped on aarch64-none-linux-gnu - no issues. Ok for master? Thanks, Jonathan From: Richard Sandiford Sent: 28 April 2021 16:11 To: Jonathan Wright via Gcc-patches Cc: Jonathan Wright Subject: Re: [PATCH 1

[PATCH] libstdc++: Implement P2328 changes to join_view

This implements the wording changes of "join_view should join all views of ranges". Tested on x86_64-pc-linux-gnu, does this look OK for trunk? libstdc++-v3/ChangeLog: * include/std/ranges (__detail::__non_propating_cache): Define as per P2328. (join_view): Remove constra

Re: [PR94092] Re: [RFC] test builtin ratio for loop distribution

On 4/28/2021 10:26 PM, Alexandre Oliva wrote: On Feb 22, 2021, Richard Biener wrote: On Fri, Feb 19, 2021 at 9:08 AM Alexandre Oliva wrote: Here's an improved version of the patch. Regstrapped on x86_64-linux-gnu, with and without a patchlet that moved multi-pieces ahead of setmem, and al

[committed] libstdc++: Use std::addressof to avoid ADL for operator& [PR 60497]

This is another small step towards avoiding the problems described in PR 60497, by using std::addressof to avoid ADL, so that we don't require all template arguments to be complete. libstdc++-v3/ChangeLog: PR libstdc++/60497 * include/bits/basic_ios.tcc (basic_ios::copyfmt): use

Re: [PATCH v2 15/21] libcc1: share GDB plugin code

On 4/27/2021 7:01 PM, Tom Tromey wrote: The two GDB plugins in libcc1 share a fair amount of code. This was done by copy-and-paste, though in reality the underlying code is nearly identical. libcc1/ChangeLog 2021-04-27 Tom Tromey * libcp1.cc (struct libcp1): Derive from base_gdb_p

Re: [PATCH 12/20] aarch64: Use RTL builtins for FP ml[as][q]_lane intrinsics

Patch updated as per suggestion (similar to patch 10/20.) Tested and bootstrapped on aarch64-none-linux-gnu - no issues. Ok for master? Thanks, Jonathan From: Richard Sandiford Sent: 28 April 2021 16:37 To: Jonathan Wright via Gcc-patches Cc: Jonathan Wright S

[committed] libstdc++: Implement proposed resolution for LWG 3532

Tested on x86_64-pc-linux-gnu, committed as "obvious". libstdc++-v3/ChangeLog: * include/std/ranges (split_view::_InnerIter::operator++): Depend on _Base instead of _Vp directly, as per LWG 3532. --- libstdc++-v3/include/std/ranges | 2 +- 1 file changed, 1 insertion(+), 1 deleti

Re: [PATCH v2 17/21] libcc1: share the GCC interface code

On 4/27/2021 7:01 PM, Tom Tromey wrote: Both the C and C++ side of the GDB plugin in libcc1 share a lot of code relating to the base GCC interface. It was all copy-and-pasted, but is essentially identical between the two. This is by design, as the base GCC API is intended to be shared. This

Re: [PATCH v2 19/21] libcc1: use variadic templates for callbacks

On 4/27/2021 7:01 PM, Tom Tromey wrote: This patch completes the transition of libcc1 from the use of separate template functions for different arities to the use of variadic functions. This is how I had wanted it to work from the very beginning, and is possible now with C++11. I had thought

Re: [PATCH] clear base0 flag for pointers (PR 100307)

On 4/28/2021 6:51 PM, Martin Sebor via Gcc-patches wrote: When the compute_objsize_r() function sees a pointer whose target it can't determine it sets the size of the pointed to object to the maximum but it doesn't clear the base0 flag to indicate that the offset need not be zero-based.  This i

[GCC-10 backport][PATCH] arm: _Generic feature failing with ICE for -O0 (pr97205).

Hi, This is a backport to GCC-10 to fix PR97205, patch applies cleanly on the branch. Regression tested and found no issues. Ok for GCC-10 backport? Regards, Srinath. This makes sure that stack allocated SSA_NAMEs are at least MODE_ALIGNED. Also increase the MEM_ALIGN for the corr

[pushed] libgfortran, configure : Adjust configure to autoconf-2.69

Hi As discussed on irc with Tobias… (I’ve included the changes to configure in this case since they are the only changes in the patch) bootstrapped on x86-64-linux-gnu pushed to releases/gcc-9. thanks Iain == It appears that at some point the configure file has been regenerated with auto

Re: [PATCH 1/20] aarch64: Use RTL builtin for vmull[_high]_p8 intrinsics

Jonathan Wright writes: > Thanks for the review, I've updated the patch as per option 1. > > Tested and bootstrapped on aarch64-none-linux-gnu with no issues. > > Ok for master? OK, thanks, Richard > Thanks, > Jonathan > --

Re: [PATCH 10/20] aarch64: Use RTL builtins for FP ml[as]_n intrinsics

Jonathan Wright writes: > Patch updated as per your suggestion. > > Tested and bootstrapped on aarch64-none-linux-gnu - no issues. > > Ok for master? OK, thanks. Richard > Thanks, > Jonathan > --- > From: Richard Sandif

Re: [PATCH 12/20] aarch64: Use RTL builtins for FP ml[as][q]_lane intrinsics

Jonathan Wright writes: > Patch updated as per suggestion (similar to patch 10/20.) > > Tested and bootstrapped on aarch64-none-linux-gnu - no issues. > > Ok for master? OK, thanks. Richard > Thanks, > Jonathan > --- >

Re: [PATCH 1/2] Jump threader refactor.

On 4/28/2021 11:12 AM, Aldy Hernandez wrote: This is an overall refactor of the jump threader, both for the low level bits in tree-ssa-threadupdate.* and the high level bits in tree-ssa-threadedge.*. There should be no functional changes. Some of the benefits of the refactor are: a) Eliminat

Re: [PATCH 02/12] Allow generating pseudo register with specific alignment

"H.J. Lu via Gcc-patches" writes: > On Fri, Apr 30, 2021 at 5:49 AM H.J. Lu wrote: >> >> On Fri, Apr 30, 2021 at 5:42 AM Richard Sandiford >> wrote: >> > >> > "H.J. Lu via Gcc-patches" writes: >> > > On Fri, Apr 30, 2021 at 2:06 AM Richard Sandiford >> > > wrote: >> > >> >> > >> "H.J. Lu via G

Re: [PATCH 2/2] Refactor backward threader registry and profitability code into classes.

On 4/28/2021 11:12 AM, Aldy Hernandez wrote: This refactors the registry and the profitability code from the backwards threader into two separate classes. It cleans up the code, and makes it easier for alternate implementations to share code. Tested on x86-64 Linux. gcc/ChangeLog: *

Re: [PATCH V7 4/7] CTF/BTF debug formats

>> For a moment, for the sake of this question, if we establish that CTF/BTF >> generation always feeds off DWARF DIEs (so there is no need to access >> type/decl tree nodes), what will it take to keep LTO support while keeping >> ctf_debug_finalize in dwarf2out_finish ? > > I don't think it's po

Re: [PATCH 2/2] Refactor backward threader registry and profitability code into classes.

I may just do that :). Thanks. Aldy On Fri, Apr 30, 2021 at 6:10 PM Jeff Law wrote: > > > On 4/28/2021 11:12 AM, Aldy Hernandez wrote: > > This refactors the registry and the profitability code from the > > backwards threader into two separate classes. It cleans up the code, > > and makes it ea

Re: [PATCH] split loop for NE condition.

On 4/29/2021 3:50 AM, Jiufu Guo via Gcc-patches wrote: When there is the possibility that overflow may happen on the loop index, a few optimizations would not happen. For example code: foo (int *a, int *b, unsigned k, unsigned n) { while (++k != n) a[k] = b[k] + 1; } For this code, i

Re: [PATCH 13/20] aarch64: Use RTL builtins for FP ml[as][q]_laneq intrinsics

Updated the patch to be more consistent with the others in the series. Tested and bootstrapped on aarch64-none-linux-gnu - no issues. Ok for master? Thanks, Jonathan From: Gcc-patches on behalf of Jonathan Wright via Gcc-patches Sent: 28 April 2021 15:42 To: g

Re: [PATCH 13/20] aarch64: Use RTL builtins for FP ml[as][q]_laneq intrinsics

Jonathan Wright writes: > Updated the patch to be more consistent with the others in the series. > > Tested and bootstrapped on aarch64-none-linux-gnu - no issues. > > Ok for master? OK, thanks. Richard > > Thanks, > Jonathan > ---

Re: [PATCH 14/20] testsuite: aarch64: Add fusion tests for FP vml[as] intrinsics

Updated the patch to implement suggestions - restricting these tests to run on only aarch64 targets. Tested and all new tests pass on aarch64-none-linux-gnu. Ok for master? Thanks, Jonathan From: Richard Sandiford Sent: 28 April 2021 16:46 To: Jonathan Wright vi

Re: [PATCH 14/20] testsuite: aarch64: Add fusion tests for FP vml[as] intrinsics

Jonathan Wright writes: > Updated the patch to implement suggestions - restricting these tests to run on > only aarch64 targets. > > Tested and all new tests pass on aarch64-none-linux-gnu. > > Ok for master? OK, thanks. Richard > Thanks, > Jonathan > ---

Re: [PATCH] libstdc++: Implement P2328 changes to join_view

On 30/04/21 10:38 -0400, Patrick Palka via Libstdc++ wrote: This implements the wording changes of "join_view should join all views of ranges". Tested on x86_64-pc-linux-gnu, does this look OK for trunk? OK, thanks. libstdc++-v3/ChangeLog: * include/std/ranges (__detail::__non_propa

Re: [committed] libstdc++: Implement proposed resolution for LWG 3532

On 30/04/21 11:07 -0400, Patrick Palka via Libstdc++ wrote: Tested on x86_64-pc-linux-gnu, committed as "obvious". Thanks. OK for 11 and 10 too. libstdc++-v3/ChangeLog: * include/std/ranges (split_view::_InnerIter::operator++): Depend on _Base instead of _Vp directly, as per

Re: [PATCH, V2] Define KFmode constants for libgcc.

On Thu, 29 Apr 2021, Segher Boessenkool wrote: > > > > gcc/ > > > > 2021-04-29 Michael Meissner > > > > > > > > PR bootstrap/100327 > > > > * config/rs6000/rs6000.c > > > > (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define. > > > > > > I don't see this used anywhere on

Re: [PATCH 02/12] Allow generating pseudo register with specific alignment

y generated when inlining memcpy and memset. For memcpy, there is no need to spill: [hjl@gnu-cfl-2 pieces]$ cat spill1.i extern void *ops1; extern void *ops2; extern void bar (void); void foo (void) { __builtin_memcpy (ops1, ops2, 32); bar (); __builtin_memcpy (ops1, ops2, 32); } [hjl@gnu-cfl-

Re: [PATCH] libstdc++: Implement P2328 changes to join_view

On Fri, Apr 30, 2021 at 12:11 PM Patrick Palka via Libstdc++ wrote: > > + template > + _Tp& > + _M_emplace_deref(const _Iter& __i) > + { > + this->reset(); > + return this->emplace(*__i); > + } This incurs a move, avoiding of which is the

Re: [PATCH] PING implement pre-c++20 contracts

Hello! Looping back around to this. re: https://gcc.gnu.org/pipermail/gcc-patches/2021-March/567334.html On 3/25/21, Jason Merrill wrote: > On 3/1/21 8:12 AM, Jeff Chapman wrote: >> On 1/18/21, Jason Merrill wrote: >>> On 1/4/21 9:58 AM, Jeff Chapman wrote: Ping. re: https://gcc.gnu.or

Re: About implementation of the Negative property of options.

On Thu, 29 Apr 2021, Jim Wilson wrote: > Note that only in the -mfoo6= case are the duplicate options removed from > the command line. So pruning options requires that you have both > RejectNegative and Negative pointing at yourself, which is not what the > documentation says. Thanks for the exa

Re: [PATCH] aarch64: Avoid duplicating bti j insns for jump tables [PR99988]

Hi Richard, On 21/04/2021 13:05, Richard Sandiford wrote: > Alex Coplan writes: > > Hi Richard, > > > > On 15/04/2021 18:45, Richard Sandiford wrote: > >> Looks good in general, but like you say, it's GCC 12 material. > > > > Thanks for the review. The attached patch addresses these comments and

Re: [PATCH 13/20] aarch64: Use RTL builtins for FP ml[as][q]_laneq intrinsics

Richard Sandiford via Gcc-patches writes: > Jonathan Wright writes: >> diff --git a/gcc/config/aarch64/aarch64-simd.md >> b/gcc/config/aarch64/aarch64-simd.md >> index >> bdee49f74f4725409d33af733bb55be290b3f0e7..234762960bd6df057394f753072ef65a6628a43d >> 100644 >> --- a/gcc/config/aarch64/aa

Re: RFC: Changing AC_PROG_CC to AC_PROG_CC_C99 in top level configure

On 2021-04-26 7:32 a.m., Nick Clifton via Gdb-patches wrote:> Hi Guys, > > Given that gcc, gdb and now binutils are all now requiring C99 as a > minimum version of C, are there any objections to updating > configure.ac to reflect this ? > > Cheers > Nick > > diff --git a/configure.ac b/c

Re: [PATCH V7 4/7] CTF/BTF debug formats

On 4/30/21 9:11 AM, Jose E. Marchesi via Gcc-patches wrote: > >>> For a moment, for the sake of this question, if we establish that CTF/BTF >>> generation always feeds off DWARF DIEs (so there is no need to access >>> type/decl tree nodes), what will it take to keep LTO support while keeping >>>

[PATCH] c++: mark_used and ADL with template-id [PR100344]

My r11-295 patch for PR68942 didn't consider that the callee of an ADL-eligible function call can be a TEMPLATE_ID_EXPR, and we don't want to disable mark_used when substituting into the template arguments of this TEMPLATE_ID_EXPR because the arguments are clearly used regardless of the outcome of

[PATCH "60/57"] rs6000: Fix AltiVec builtin marked as VSX

On 4/27/21 10:32 AM, Bill Schmidt wrote: The design of the target-specific built-in function support in the Power back end has not stood the test of time. The machinery is grossly inefficient, confusing, and arcane; and adding new built-in functions is inefficient and error-prone. This patch se

Re: [Ping] AVR CC0 conversion

Senthil Kumar Selvaraj via Gcc-patches: John Paul Adrian Glaubitz writes: On 4/28/21 7:59 PM, Senthil Kumar Selvaraj wrote: https://gcc.gnu.org/git?p=gcc.git;a=commit;h=3ba781d3b5c8efadb60866c9743b657e8f0eb222 Awesome \o/. Should we wait for the second patch [1] to be merged as well before clo

Re: [PATCH, libstdc++] GLIBCXX_HAVE_INT64_T

On 29/04/21 16:06 -0400, David Edelsohn wrote: On Fri, Jan 8, 2021 at 1:37 PM Jonathan Wakely wrote: On 06/01/21 19:41 -0500, David Edelsohn wrote: >Thanks for clarifying the issue. > >As you implicitly point out, GCC knows the type of INT64 and defines >the macro __INT64_TYPE__ . The revised

Re: [PATCH 39/57] rs6000: Darwin builtin support

Bill Schmidt via Gcc-patches wrote: 2021-03-04 Bill Schmidt gcc/ * config/rs6000/darwin.h (SUBTARGET_INIT_BUILTINS): Use the new decl when new_builtins_are_live. * config/rs6000/rs6000-builtin-new.def (__builtin_cfstring): New built-in. This is fine from th

Re: [PATCH, libstdc++] GLIBCXX_HAVE_INT64_T

On Fri, Apr 30, 2021 at 3:31 PM Jonathan Wakely wrote: > > On 29/04/21 16:06 -0400, David Edelsohn wrote: > >On Fri, Jan 8, 2021 at 1:37 PM Jonathan Wakely wrote: > >> > >> On 06/01/21 19:41 -0500, David Edelsohn wrote: > >> >Thanks for clarifying the issue. > >> > > >> >As you implicitly point o

Re: About implementation of the Negative property of options.

On Fri, Apr 30, 2021 at 1:03 AM gengqi-linux wrote: > Thanks for your replies. > I would suggest filing a bug report, and adding useful info from this thread to the bug report. Then we can track it. Jim

Re: [committed] libstdc++: Define __cpp_lib_constexpr_string macro

On 28/04/21 16:14 +0100, Jonathan Wakely wrote: As noted in r11-1339-gb6ab9ecd550227684643b41e9e33a4d3466724d8 we define a non-standard __cpp_lib_constexpr_char_traits feature test macro to indicate support for P0426R1 and P1032R1. At some point last year the __cpp_lib_constexpr_string macro was

Re: [PATCH] libstdc++: Implement P2328 changes to join_view

On Fri, 30 Apr 2021, Tim Song wrote: > On Fri, Apr 30, 2021 at 12:11 PM Patrick Palka via Libstdc++ > wrote: > > > > + template > > + _Tp& > > + _M_emplace_deref(const _Iter& __i) > > + { > > + this->reset(); > > + return this->emplace(*__i); > >

Re: [PATCH] split loop for NE condition.

Hi! On Thu, Apr 29, 2021 at 05:50:48PM +0800, Jiufu Guo wrote: > When there is the possibility that overflow may happen on the loop index, > a few optimizations would not happen. For example code: > > foo (int *a, int *b, unsigned k, unsigned n) > { > while (++k != n) > a[k] = b[k] + 1; >

Re: RFC: Changing AC_PROG_CC to AC_PROG_CC_C99 in top level configure

On 4/30/2021 12:36 PM, Simon Marchi via Gcc-patches wrote: On 2021-04-26 7:32 a.m., Nick Clifton via Gdb-patches wrote:> Hi Guys, Given that gcc, gdb and now binutils are all now requiring C99 as a minimum version of C, are there any objections to updating configure.ac to reflect this

Ping: [PATCH] diagnostics: Support for -finput-charset [PR93067]

Hi David- With GCC 11 released now, I thought it might be a good time to ping this patch that supports -finput-charset for diagnostics please? [https://gcc.gnu.org/pipermail/gcc-patches/2021-January/564527.html] Patch still applies to master, and tests still look good as before. If you have any co

Re: [PATCH] libstdc++: Implement P2328 changes to join_view

On 30/04/21 17:34 -0400, Patrick Palka via Libstdc++ wrote: On Fri, 30 Apr 2021, Tim Song wrote: On Fri, Apr 30, 2021 at 12:11 PM Patrick Palka via Libstdc++ wrote: > > + template > + _Tp& > + _M_emplace_deref(const _Iter& __i) > + { > + this->reset(); >

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