[PATCH] add g_nonstandard_bool attribute for GIMPLE FE use

This adds __attribute__((g_nonstandard_bool(precision))) to be able to construct nonstandard boolean types which for the included testcase is needed to simulate Ada and LTO interaction (Ada uses a 8 bit precision boolean_type_node). This will also be useful for vector unit testcases where we need

[PATCH] tree-optimization/95582 - fix vector pattern with bool conversions

The pattern recognizer fends off against recognizing conversions from VECT_SCALAR_BOOLEAN_TYPE_P to precision one types but what it really needs to fend off is conversions between VECT_SCALAR_BOOLEAN_TYPE_P types - the Ada FE uses an 8 bit boolean type that satisfies this predicate. Bootstrapped a

Re: [PATCH] ira.c: Fix ICE in ira-color [PR97092]

Vladimir Makarov writes: > On 2020-12-10 10:12 a.m., Andrea Corallo wrote: >> Hi all, >> >> following discussion on PR97092 I'd like to submit the following patch >> with a fix plus associated testcase. >> >> With this patch applied mode is recomputed at each iteration while >> looping across dif

RE: RFC: ARM MVE and Neon auto-vectorization

> -Original Message- > From: Gcc-patches On Behalf Of > Richard Sandiford via Gcc-patches > Sent: 10 December 2020 17:54 > To: Christophe Lyon > Cc: Christophe Lyon via Gcc-patches > Subject: Re: RFC: ARM MVE and Neon auto-vectorization > > Christophe Lyon writes: > > On Wed, 9 Dec 2

RE: [PATCH 1/5] arm: Auto-vectorization for MVE: vand

Hi Christophe, From: Christophe Lyon Sent: 10 December 2020 12:16 To: Kyrylo Tkachov Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH 1/5] arm: Auto-vectorization for MVE: vand On Tue, 8 Dec 2020 at 15:00, Kyrylo Tkachov wrote: > -Original Message- >

[PATCH] expand: Fix up expand_doubleword_mod on 32-bit targets [PR98229]

Hi! As the testcase shows, for 32-bit word size we can end up with op1 up to 0x (0x1 % 0x == 1 and so we use bit == 32 for that), but the CONST_INT we got from caller is for DImode in that case and not valid for SImode operations. The following patch canonicalizes the two

[PATCH] tree-optimization/98235 - limit SLP discovery

With following backedges and the SLP discovery cache not being permute aware we have to put some discovery limits in place again. That's also the opportunity to ditch the separate limit on the number of permutes we try, so the patch limits the overall work done (as in vect_build_slp_tree cache miss

Re: [PATCH] Complete _GLIBCXX_DEBUG constexpr compatibility

On 11/12/20 08:20 +0100, François Dumont via Libstdc++ wrote: Hi I'd like to commit this small fix to complete _GLIBCXX_DEBUG constexpr compatibility. There are still 2 macros not using __glibcxx_assert_1. It fixes the generated diagnostic to have the __failed_assertion rather than a messag

Re: [PATCH] expand: Fix up expand_doubleword_mod on 32-bit targets [PR98229]

On Fri, 11 Dec 2020, Jakub Jelinek wrote: > Hi! > > As the testcase shows, for 32-bit word size we can end up with op1 > up to 0x (0x1 % 0x == 1 and so we use bit == 32 > for that), but the CONST_INT we got from caller is for DImode in that case > and not valid for SImode

[PATCH] expand, v2: Fix up expand_doubleword_mod on 32-bit targets [PR98229]

On Fri, Dec 11, 2020 at 11:34:01AM +0100, Richard Biener wrote: > Shouldn't we simply use gen_int_mode? You're right, that is shorter. So like this? BTW, looking at gen_int_mode, wouldn't it be better to add an overload for HOST_WIDE_INT first argument so that it wouldn't need to go through poly

RE: [PATCH][GCC10][1/6] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

> -Original Message- > From: Andrea Corallo > Sent: 03 December 2020 17:08 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; nd > Subject: [PATCH][GCC10][1/6] arm: Add vld1_lane_bf16 + vldq_lane_bf16 > intrinsics > > Hi all, > > first patch of the series to ba

RE: [PATCH][GCC10][2/6] arm: Add vst1_lane_bf16 + vstq_lane_bf16 intrinsics

> -Original Message- > From: Andrea Corallo > Sent: 03 December 2020 17:09 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; nd > Subject: [PATCH][GCC10][2/6] arm: Add vst1_lane_bf16 + vstq_lane_bf16 > intrinsics > > Hi all, > > second patch of the series to b

RE: [PATCH][GCC10][3/6] arm: Add vld1_bf16 + vld1q_bf16 intrinsics

> -Original Message- > From: Andrea Corallo > Sent: 03 December 2020 17:10 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; nd > Subject: [PATCH][GCC10][3/6] arm: Add vld1_bf16 + vld1q_bf16 intrinsics > > Hi all, > > third patch of the series to backport a nu

RE: [PATCH][GCC10][4/6] arm: Add vst1_bf16 + vst1q_bf16 intrinsics

> -Original Message- > From: Andrea Corallo > Sent: 03 December 2020 17:11 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; nd > Subject: [PATCH][GCC10][4/6] arm: Add vst1_bf16 + vst1q_bf16 intrinsics > > Hi all, > > forth patch of the series to backport a nu

RE: [PATCH][GCC10][5/6] arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics

> -Original Message- > From: Andrea Corallo > Sent: 03 December 2020 17:13 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; nd > Subject: [PATCH][GCC10][5/6] arm: Add vldN_lane_bf16 + vldNq_lane_bf16 > intrisics > > Hi all, > > fifth patch of the series to ba

RE: [PATCH][GCC10][6/6] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics

> -Original Message- > From: Andrea Corallo > Sent: 03 December 2020 17:14 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; nd > Subject: [PATCH][GCC10][6/6] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 > intrisics > > Hi all, > > last patch of the series to bac

RE: [PATCH] arm: Improve documentation for effective target 'arm_softfloat'

> -Original Message- > From: Andrea Corallo > Sent: 01 December 2020 13:52 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; nd > Subject: [PATCH] arm: Improve documentation for effective target > 'arm_softfloat' > > Hi all, > > I'd like to submit the followin

RE: [PATCH V2] arm: [testsuite] fix lob tests for -mfloat-abi=hard

> -Original Message- > From: Andrea Corallo > Sent: 01 December 2020 10:13 > To: gcc-patches@gcc.gnu.org > Cc: Richard Earnshaw ; nd ; > Kyrylo Tkachov > Subject: [PATCH V2] arm: [testsuite] fix lob tests for -mfloat-abi=hard > > Hi all, > > second version of this patch here fixing l

RE: [backport gcc-10][AArch64] ACLE bf16 convert

> -Original Message- > From: Dennis Zhang > Sent: 10 December 2020 14:27 > To: gcc-patches@gcc.gnu.org > Cc: nd ; Richard Earnshaw ; > Marcus Shawcroft ; Kyrylo Tkachov > ; Richard Sandiford > > Subject: [backport gcc-10][AArch64] ACLE bf16 convert > > Hi all, > > This patch backport

Re: [PATCH] expand, v2: Fix up expand_doubleword_mod on 32-bit targets [PR98229]

On Fri, 11 Dec 2020, Jakub Jelinek wrote: > On Fri, Dec 11, 2020 at 11:34:01AM +0100, Richard Biener wrote: > > Shouldn't we simply use gen_int_mode? > > You're right, that is shorter. So like this? Yes, OK. > BTW, looking at gen_int_mode, wouldn't it be better to add an overload > for HOST_WI

RE: [PR66791][ARM] Replace __builtin_neon_vcreate* for vcreate intrinsics

> -Original Message- > From: Prathamesh Kulkarni > Sent: 08 December 2020 09:41 > To: Kyrylo Tkachov > Cc: gcc Patches > Subject: Re: [PR66791][ARM] Replace __builtin_neon_vcreate* for vcreate > intrinsics > > On Fri, 4 Dec 2020 at 16:26, Prathamesh Kulkarni > wrote: > > > > On Thu,

RE: [ARM][PR66791] Replace builtins for vclt and vcgt intrinsics in arm_neon.h

> -Original Message- > From: Prathamesh Kulkarni > Sent: 08 December 2020 11:04 > To: gcc Patches ; Kyrylo Tkachov > > Subject: [ARM][PR66791] Replace builtins for vclt and vcgt intrinsics in > arm_neon.h > > Hi, > This patch replaces calls to __builtin_neon_vcgt* by < and > in vclt >

RE: [PR66791][ARM] Replace __builtin_neon_vneg* by - for vneg intrinsics

> -Original Message- > From: Prathamesh Kulkarni > Sent: 08 December 2020 09:57 > To: gcc Patches ; Kyrylo Tkachov > > Subject: Re: [PR66791][ARM] Replace __builtin_neon_vneg* by - for vneg > intrinsics > > On Thu, 3 Dec 2020 at 16:23, Prathamesh Kulkarni > wrote: > > > > Hi, > > This

RE: [backport gcc-10][AArch64] ACLE bf16 get

> -Original Message- > From: Dennis Zhang > Sent: 10 December 2020 14:35 > To: gcc-patches@gcc.gnu.org > Cc: nd ; Richard Earnshaw ; > Marcus Shawcroft ; Kyrylo Tkachov > ; Richard Sandiford > > Subject: [backport gcc-10][AArch64] ACLE bf16 get > > Hi all, > > This patch backports th

[PATCH] testsuite/98239 - require vect_condition for gcc.dg/vect/bb-slp-69.c

Committed. 2020-12-11 Richard Biener PR testsuite/98239 * gcc.dg/vect/bb-slp-69.c: Require vect_condition. --- gcc/testsuite/gcc.dg/vect/bb-slp-69.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-69.c b/gcc/testsuite/gcc.dg/vect/bb-slp-69

Re: [PATCH] tree-optimization/98211 - fix bogus vectorization of conversion

Richard Biener writes: > Pattern recog incompletely handles some bool cases but we shouldn't > miscompile as a result but not vectorize. Unfortunately > vectorizable_assignment lets invalid conversions (that > vectorizable_conversion rejects) slip through. The following > rectifies that. > > Boo

[PATCH] testsuite/98240 - amend gcc.dg/vect/pr97678.c

Committed. 2020-12-11 Richard Biener PR testsuite/98240 * gcc.dg/vect/pr97678.c: Require vect_int_mult and vect_pack_trunc. --- gcc/testsuite/gcc.dg/vect/pr97678.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/testsuite/gcc.dg/vect/pr97678.c b/gcc/testsuit

Re: [PATCH] tree-optimization/98211 - fix bogus vectorization of conversion

On Fri, 11 Dec 2020, Richard Sandiford wrote: > Richard Biener writes: > > Pattern recog incompletely handles some bool cases but we shouldn't > > miscompile as a result but not vectorize. Unfortunately > > vectorizable_assignment lets invalid conversions (that > > vectorizable_conversion reject

[PATCH] testsuite/98242 - amend gcc.dg/vect/bb-slp-subgroups-3.c

Committed. 2020-12-11 Richard Biener PR testsuite/98242 * gcc.dg/vect/bb-slp-subgroups-3.c: Require vect_int_mult. --- gcc/testsuite/gcc.dg/vect/bb-slp-subgroups-3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-subgroups-3.c b/gcc/tests

[PATCH] testsuite/98244 - amend gcc.dg/vect/vect-live-6.c

Committed. 2020-12-11 Richard Biener PR testsuite/98244 * gcc.dg/vect/vect-live-6.c: Require vect_condition. --- gcc/testsuite/gcc.dg/vect/vect-live-6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/vect/vect-live-6.c b/gcc/testsuite

Re: [PATCH] aix: Fixinclude updates [PR98208]

On 12/10/20 7:59 PM, Ilya Leoshkevich wrote: Tested on gcc121 (x86_64 CentOS Linux 7). Ok for master? After 92648faa1cb2 ("aix: Fixinclude") make check-fixincludes began to fail (at least on gcc121 machine). Fix by updating fixincludes/tests and rerunning genfixes. diff --git a/fixinclud

Re: [PATCH] tree-optimization/98211 - fix bogus vectorization of conversion

Richard Biener writes: > On Fri, 11 Dec 2020, Richard Sandiford wrote: >> > diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c >> > index a4980a931a9..d3ab8aa1c29 100644 >> > --- a/gcc/tree-vect-stmts.c >> > +++ b/gcc/tree-vect-stmts.c >> > @@ -5123,6 +5123,17 @@ vectorizable_assignment (v

Re: [PATCH] tree-optimization/98211 - fix bogus vectorization of conversion

On Fri, 11 Dec 2020, Richard Sandiford wrote: > Richard Biener writes: > > On Fri, 11 Dec 2020, Richard Sandiford wrote: > >> > diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c > >> > index a4980a931a9..d3ab8aa1c29 100644 > >> > --- a/gcc/tree-vect-stmts.c > >> > +++ b/gcc/tree-vect-stm

Re: [PATCH] tree-optimization/98211 - fix bogus vectorization of conversion

Richard Biener writes: > On Fri, 11 Dec 2020, Richard Sandiford wrote: > >> Richard Biener writes: >> > On Fri, 11 Dec 2020, Richard Sandiford wrote: >> >> > diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c >> >> > index a4980a931a9..d3ab8aa1c29 100644 >> >> > --- a/gcc/tree-vect-stmts.

Re: [PATCH] tree-optimization/98211 - fix bogus vectorization of conversion

On December 11, 2020 2:49:07 PM GMT+01:00, Richard Sandiford wrote: >Richard Biener writes: >> On Fri, 11 Dec 2020, Richard Sandiford wrote: >> >>> Richard Biener writes: >>> > On Fri, 11 Dec 2020, Richard Sandiford wrote: >>> >> > diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c >>>

Re: [PATCH][GCC10][1/6] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

Kyrylo Tkachov writes: [...] > Ok. > Thanks, > Kyrill Hi Kyrill, I've installed the serie into releases/gcc-10 as follow: 00be3a70dd8 arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics 69191da4f4f arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics f09b8cc616a arm: Add vst1_bf16 + vst1q_bf16

Re: [PATCH V2] arm: [testsuite] fix lob tests for -mfloat-abi=hard

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 01 December 2020 10:13 >> To: gcc-patches@gcc.gnu.org >> Cc: Richard Earnshaw ; nd ; >> Kyrylo Tkachov >> Subject: [PATCH V2] arm: [testsuite] fix lob tests for -mfloat-abi=hard >> >> Hi all, >> >> second ve

Re: [PATCH] arm: Improve documentation for effective target 'arm_softfloat'

Kyrylo Tkachov writes: >> -Original Message- >> From: Andrea Corallo >> Sent: 01 December 2020 13:52 >> To: gcc-patches@gcc.gnu.org >> Cc: Kyrylo Tkachov ; Richard Earnshaw >> ; nd >> Subject: [PATCH] arm: Improve documentation for effective target >> 'arm_softfloat' >> >> Hi all, >>

c++: Module lang hook overriding

This installs stub lang hooks for modules and creates the module dump file. gcc/cp/ * cp-lang.c (LANG_HOOKS_PREPROCESS_MAIN_FILE): Override. (LANG_HOOKS_PREPROCESS_OPTIONS): Override. (LANG_HOOKS_PREPROCESS_TOKEN): Override. * cp-objcp-common.c (cp_registe

Re: [PATCH 00/31] VAX: Bring the port up to date (yes, MODE_CC conversion is included)

On Wed, 9 Dec 2020, Paul Koning wrote: > > This all sounds great. Do you happen to know if it is cycle-accurate > > with respect to individual hardware microarchitectures simulated? That > > would be required for performance evaluation of compiler-generated code. > > No, it isn't. I believe

V2 [PATCH] x86: Update user interrupt handler stack frame

On Thu, Dec 10, 2020 at 1:57 PM Uros Bizjak wrote: > > On Thu, Dec 10, 2020 at 10:20 PM H.J. Lu wrote: > > > > User interrupt handler stack frame is similar to exception interrupt > > handler stack frame. Instead of error code, the second argument is > > user interrupt request register vector. >

Re: [PATCH] c++: Diagnose unstable satisfaction results

On Thu, 10 Dec 2020, Patrick Palka wrote: > On Thu, 10 Dec 2020, Jason Merrill wrote: > > > On 12/10/20 11:21 AM, Patrick Palka wrote: > > > This implements lightweight heuristical detection and diagnosing of > > > satisfaction results that change at different points in the program, > > > which r

[committed] arc: Refurbish adc/sbc patterns

The adc/sbc patterns were unecessary spliting, remove that and associated functions. gcc/ 2020-12-11 Claudiu Zissulescu * config/arc/arc-protos.h (arc_scheduling_not_expected): Remove it. (arc_sets_cc_p): Likewise. (arc_need_delay): Likewise. * config/ar

c++: cp_tree_equal tweaks

When comparing streamedtrees we can encounter NON_LVALUE_EXPR and VIEW_CONVERT_EXPRs with null types. Also, whenchecking a potential duplicate we don't want to reject PARM_DECLs with different contexts, if those two contexts are the two decls of interest. gcc/cp/ * cp-tre

c++: module test harness

Here is the module test harness -- but no tests. gcc/testsuite/ * g++.dg/modules/modules.exp: New. -- Nathan Sidwell diff --git c/gcc/testsuite/g++.dg/modules/modules.exp w/gcc/testsuite/g++.dg/modules/modules.exp new file mode 100644 index 000..e2fd2a7fdd0 --- /dev/null

[committed] arc: Avoid generating brcc instructions with limm

From: Claudiu Zissulescu BRcc instructions are generated quite late in the compilation process. These instructions combines a compare with a regular conditional branch if the result of the compare is not used anylonger. However, when compiling for size, it is better to avoid BRcc instructions whi

[committed] arc: Update ARC700 cache hazard detection.

From: Claudiu Zissulescu Replace/update ARC700 cache hazard detection. The next situations are handled: - There are 2 stores back2back, then 3 loads in next 3 or 4 instructions. if 3 loads in 3 instructions then we insert 2 nops after stores. if 3 loads in 4 instructions then we insert

Re: [backport gcc-10][AArch64] ACLE bf16 get

Hi Kyrylo, > > From: Kyrylo Tkachov > Sent: Friday, December 11, 2020 11:58 AM > To: Dennis Zhang; gcc-patches@gcc.gnu.org > Cc: nd; Richard Earnshaw; Marcus Shawcroft; Richard Sandiford > Subject: RE: [backport gcc-10][AArch64] ACLE bf16 get > > > -O

[PATCH] arm: Auto-vectorization for MVE clean condition for vand and vorr expanders

The patch restores the unconditional definition of the VDQ iterator, and changes the conditions of the vand and vorr expanders to use ARM_HAVE__ARITH. 2020-12-11 Christophe Lyon gcc/ * config/arm/iterators.md (VDQ): Remove TARGET_HAVE_MVE conditions. * config/ar

Re: [backport gcc-10][AArch64] ACLE bf16 convert

> > From: Kyrylo Tkachov > Sent: Friday, December 11, 2020 11:23 AM > To: Dennis Zhang; gcc-patches@gcc.gnu.org > Cc: nd; Richard Earnshaw; Marcus Shawcroft; Richard Sandiford > Subject: RE: [backport gcc-10][AArch64] ACLE bf16 convert > > > -Original

RE: [PATCH] arm: Auto-vectorization for MVE clean condition for vand and vorr expanders

> -Original Message- > From: Gcc-patches On Behalf Of > Christophe Lyon via Gcc-patches > Sent: 11 December 2020 16:33 > To: gcc-patches@gcc.gnu.org > Subject: [PATCH] arm: Auto-vectorization for MVE clean condition for vand > and vorr expanders > > The patch restores the unconditional

Re: [PATCH] arm: Auto-vectorization for MVE clean condition for vand and vorr expanders

On Fri, 11 Dec 2020 at 17:35, Kyrylo Tkachov wrote: > > > > > -Original Message- > > From: Gcc-patches On Behalf Of > > Christophe Lyon via Gcc-patches > > Sent: 11 December 2020 16:33 > > To: gcc-patches@gcc.gnu.org > > Subject: [PATCH] arm: Auto-vectorization for MVE clean condition for

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

Στις Πέμ, 10 Δεκ 2020 στις 7:42 π.μ., ο/η Dimitar Dimitrov έγραψε: > On сряда, 9 декември 2020 г. 15:12:49 EET abebeos via Gcc-patches wrote: > > Essence: > > > > I need a confirmation that the testsuite setup as presented in: > > > > https://github.com/abebeos/avr-gnu > > > > works fine. > > > >

Re: [gcc r11-4816] Fix Ada build failure for the SuSE PowerPC64/Linux compiler

> On Dez 03 2020, Eric Botcazou wrote: >> I'm afraid we cannot support both given the current setup, so you'll have to >> make a choice for the powerpc64-suse-linux compiler. Are you saying that ADA doesn't support multilibs and you can only have/use the default lib? On 12/3/20 1:00 PM, Andrea

Go patch committed: Encode user visible names if necessary

This patch to the Go frontend encodes user visible names if necessary. We already encode the assembler names. With this patch, we also avoid putting weird characters into the user visible name. Doing so breaks stabs debugging in particular, and may also cause debugger problems. Instead, we encode

Re: [PATCH] gcc: handle double quotes in symbol name during stabstrings generation

On Thu, Dec 10, 2020 at 9:09 PM Ian Lance Taylor wrote: > > On Tue, Dec 8, 2020 at 5:15 AM CHIGOT, CLEMENT > wrote: > > > > Any news about this bug ? It's not urgent even if it's breaking gcc builds > > with Go language, but I just want to know if you need any inputs/help from > > me. > > I se

c++: Refactor final cleanup

This is a small refactor of the end of decl processing, into which dropping module support will be simpler. gcc/cp/ * decl2.c (c_parse_final_cleanups): Refactor loop. pushing to trunk -- Nathan Sidwell diff --git i/gcc/cp/decl2.c w/gcc/cp/decl2.c index c122017c2fa..b13c9d9f73d 1

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

On 12/9/20 6:12 AM, abebeos via Gcc-patches wrote: > Essence: > > I need a confirmation that the testsuite setup as presented in: > > https://github.com/abebeos/avr-gnu > > works fine. > > The problem with the avr target is that the testsuite cannot be run easily, > mainly because of the need fo

[PATCH v3 1/4] arm: Auto-vectorization for MVE: veor

This patch enables MVE veorq instructions for auto-vectorization. MVE veorq insns in mve.md are modified to use xor instead of unspec expression to support xor3. The xor3 expander is added to vec-common.md 2020-12-11 Christophe Lyon gcc/ * config/arm/iterators.md (supf): Remo

[PATCH v3 2/4] arm: Auto-vectorization for MVE: vbic

This patch enables MVE vbic instructions for auto-vectorization. MVE vbicq insns in mve.md are modified to use 'and not' instead of unspec expression. 2020-12-11 Christophe Lyon gcc/ * config/arm/iterators.md (supf): Remove VBICQ_S and VBICQ_U. (VBICQ): Remove.

[PATCH v3 3/4] arm: Auto-vectorization for MVE: vmvn

This patch enables MVE vmvnq instructions for auto-vectorization. MVE vmvnq insns in mve.md are modified to use 'not' instead of unspec expression to support one_cmpl2. The one_cmpl2 expander is added to vec-common.md. 2020-12-11 Christophe Lyon gcc/ * config/arm/iterators.md

[PATCH v3 4/4] arm: Auto-vectorization for MVE: vneg

This patch enables MVE vneg instructions for auto-vectorization. MVE vnegq insns in mve.md are modified to use 'neg' instead of unspec expression. The neg2 expander is added to vec-common.md. Existing patterns in neon.md are prefixed with neon_. It's not clear why we have different patterns for

Re: [PATCH] c++: Diagnose unstable satisfaction results

On 12/11/20 10:31 AM, Patrick Palka wrote: On Thu, 10 Dec 2020, Patrick Palka wrote: On Thu, 10 Dec 2020, Jason Merrill wrote: On 12/10/20 11:21 AM, Patrick Palka wrote: This implements lightweight heuristical detection and diagnosing of satisfaction results that change at different points i

Re: [PATCH][GCC] aarch64: Add support for Cortex-A78C

Przemyslaw Wirkus writes: > This patch adds support for -mcpu=cortex-a78c command line option. > For more information about this processor, see [0]: > > [0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c > > OK for master ? > > gcc/ChangeLog: > > * config/aarch64/aarch

c++: Final module preparations

This adds the final few preparations to drop modules in. I'd missed a couple of changes to core compiler -- a new pair of preprocessor options, and marking the boundary of fixed and lazy global trees. For C++, we need to add module.cc to the GTY scanner. Parsing final cleanups needs a few twea

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

Στις Παρ, 11 Δεκ 2020 στις 8:32 μ.μ., ο/η Jeff Law έγραψε: > > > On 12/9/20 6:12 AM, abebeos via Gcc-patches wrote: > > Essence: > > > > I need a confirmation that the testsuite setup as presented in: > > > > https://github.com/abebeos/avr-gnu > > > > works fine. > > > > The problem with the avr

Re: [PATCH 2/1] c++: Diagnose self-recursive satisfaction

On 12/10/20 5:02 PM, Patrick Palka wrote: This patch further extends the satisfaction_cache class to diagnose self-recursive satisfaction. With this patch, a few more cmcstl2 tests fail at compile time due apparent self-recursive satisfaction. I didn't analyze these failures individually, but a

Re: [PATCH] PowerPC: Add float128/Decimal conversions

Hi! On Thu, Nov 19, 2020 at 07:05:24PM -0500, Michael Meissner wrote: > If the glibc is not 2.32 or later, this code just compiles to using abort. That is the compile-time target glibc. That is often *not* the glibc your program runs with, as I said before. And this is a huge problem still. >

[PATCH,rs6000] Test cases for p10 fusion patterns

From: Aaron Sawdey This adds some test cases to make sure that the combine patterns for p10 fusion are working. These test cases pass on power10. OK for trunk after the 2 previous patches for the fusion patterns go in? Thanks! Aaron gcc/testsuite/ChangeLog: * gcc.target/powerpc/fusi

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

Hi! Thanks for trying to push this forward. On Fri, Dec 11, 2020 at 09:49:18PM +0200, abebeos via Gcc-patches wrote: > Στις Παρ, 11 Δεκ 2020 στις 8:32 μ.μ., ο/η Jeff Law έγραψε: > > On 12/9/20 6:12 AM, abebeos via Gcc-patches wrote: > saaadhu (1st choice, zero regressions) should have one, has r

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

Στις Παρ, 11 Δεκ 2020 στις 10:02 μ.μ., ο/η Segher Boessenkool < seg...@kernel.crashing.org> έγραψε: > Hi! > > Thanks for trying to push this forward. > > On Fri, Dec 11, 2020 at 09:49:18PM +0200, abebeos via Gcc-patches wrote: > > Στις Παρ, 11 Δεκ 2020 στις 8:32 μ.μ., ο/η Jeff Law > έγραψε: > > >

Re: C++ Module Binding Vector

On 12/2/20 9:19 AM, Nathan Sidwell wrote: This is modified from the original patch.  firstly it contains a few more necessary bits.  But mainly I renamed the entities from 'MODULE_foo' to 'BINDING_foo', as it's a vector of bindings used by modules (not a vector of modules).  It also belongs in

[pushed] c++: Avoid considering some conversion ops [PR97600]

Patrick's earlier patch to check convertibility before constraints for conversion ops wasn't suitable because checking convertibility can also lead to unwanted instantiations, but it occurs to me that there's a smaller check we can do to avoid doing normal consideration of the conversion ops in thi

[PATCH 0/3] VAX: QMATH DImode add/sub fixes

Hi, This small patch series addresses an assertion failure in the handler for DImode addition and subtraction instructions used where QMATH arithmetic has been enabled (which is the default with our currently supported VAX targets) that trigger in regression testing. While at it additional tw

[PATCH 1/3] VAX: Remove unused register allocation from QMATH DImode add/sub handler

An allocation is made for a temporary register, however it is unneeded, as actually explained in the comment preceding the conditional block in question, and consequently never used, so remove it. The `temp' rtx is already used elsewhere in the function, which is possibly why this dead assignm

[PATCH 2/3] VAX: Handle constant 0 with QMATH DImode add/sub

Handle constant 0 passed to the QMATH DImode add/sub handler such as with: #2 0x11d409b0 in gen_adddi3 (operand0=0x75c0a128, operand1=0x75c60480, operand2=0x75c60470) at .../gcc/config/vax/vax.md:755 755 "vax_expand_addsub_di_operands (operands, PLUS); DONE;") (

[PATCH 3/3] VAX: Handle subtracting from self with QMATH DImode add/sub

Remove an assertion the failure of which has not been actually observed, but which appears clearly dangerous, for when the QMATH DImode add/sub handler is invoked with the subtrahend and the minuend both the same. Instead handle the operation by emitting a move of constant 0 to the output operan

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

On Fri, Dec 11, 2020 at 10:16:44PM +0200, abebeos wrote: > Στις Παρ, 11 Δεκ 2020 στις 10:02 μ.μ., ο/η Segher Boessenkool < > seg...@kernel.crashing.org> έγραψε: > > > My understanding of "non-FSF world-legals" is that something that is > > > already released/assigned needs no submission. > > > > It

Re: [PATCH] PowerPC: Set long double size for IBM/IEEE.

Hi! On Thu, Nov 19, 2020 at 07:00:11PM -0500, Michael Meissner wrote: > --- a/gcc/config/rs6000/rs6000.c > +++ b/gcc/config/rs6000/rs6000.c > @@ -4131,8 +4131,13 @@ rs6000_option_override_internal (bool global_init_p) > >/* Use long double size to select the appropriate long double. We use

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

Στις Παρ, 11 Δεκ 2020 στις 11:00 μ.μ., ο/η Segher Boessenkool < seg...@kernel.crashing.org> έγραψε: > On Fri, Dec 11, 2020 at 10:16:44PM +0200, abebeos wrote: > > Στις Παρ, 11 Δεκ 2020 στις 10:02 μ.μ., ο/η Segher Boessenkool < > > seg...@kernel.crashing.org> έγραψε: > > > > My understanding of "no

Re: [PATCH v5] Practical Improvement to libgcc Complex Divide

On 12/10/2020 5:35 PM, Jakub Jelinek wrote: On Thu, Dec 10, 2020 at 10:27:46AM -0600, Patrick McGehearty via Gcc-patches wrote: Thank you for your rapid feedback. I'll fix the various formatting issues (spaces in the wrong places and such as well as revise the Changelog magic) in the next su

Re: [PATCH 00/31] VAX: Bring the port up to date (yes, MODE_CC conversion is included)

> On Dec 11, 2020, at 9:54 AM, Maciej W. Rozycki wrote: > > On Wed, 9 Dec 2020, Paul Koning wrote: > >>> This all sounds great. Do you happen to know if it is cycle-accurate >>> with respect to individual hardware microarchitectures simulated? That >>> would be required for performance ev

Re: [PATCH] c++: Diagnose unstable satisfaction results

On Fri, 11 Dec 2020, Jason Merrill wrote: > On 12/11/20 10:31 AM, Patrick Palka wrote: > > On Thu, 10 Dec 2020, Patrick Palka wrote: > > > > > On Thu, 10 Dec 2020, Jason Merrill wrote: > > > > > > > On 12/10/20 11:21 AM, Patrick Palka wrote: > > > > > This implements lightweight heuristical dete

Re: [PATCH] PowerPC: Map IEEE 128-bit long double built-in functions

On Thu, Dec 10, 2020 at 03:20:01PM -0600, Segher Boessenkool wrote: > Hi! > > On Thu, Nov 19, 2020 at 06:58:14PM -0500, Michael Meissner wrote: > > * config/rs6000/rs6000.c (rs6000_mangle_decl_assembler_name): Add > > support for mapping built-in function names for long double > > buil

Re: [PATCH] PowerPC: Map IEEE 128-bit long double built-in functions

On Fri, Dec 11, 2020 at 05:07:28PM -0500, Michael Meissner wrote: > On Thu, Dec 10, 2020 at 03:20:01PM -0600, Segher Boessenkool wrote: > > > We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this > > > name. We > > > - only do this if the default is that long double is IBM extend

Re: [RFC] [avr] Toolchain Integration for Testsuite Execution (avr cc0 to mode_cc0 conversion)

On Fri, Dec 11, 2020 at 11:20:01PM +0200, abebeos wrote: > Στις Παρ, 11 Δεκ 2020 στις 11:00 μ.μ., ο/η Segher Boessenkool < > seg...@kernel.crashing.org> έγραψε: > > > Ok, to speed things up, is it ok if I simply pick the patch that I've > > > attached to the issue: > > > > > > https://gcc.gnu.org/b

[committed] openmp, openacc: Fix up handling of data regions [PR98183]

Hi! While the data regions (target data and OpenACC counterparts) aren't standalone directives, unlike most other OpenMP/OpenACC constructs we allow (apparently as an extension) exceptions and goto out of the block. During gimplification we place an *end* call into a finally block so that it is