[PATCH] vec_merge + vec_duplicate + vec_concat simplification

Hi all, Another vec_merge simplification that's missing is transforming: (vec_merge (vec_duplicate x) (vec_concat (y) (z)) (const_int N)) into (vec_concat x z) if N == 1 (0b01) or (vec_concat y x) if N == 2 (0b10) For the testcase in this patch on aarch64 this allows us to try matching during c

[PATCH][simplify-rtx] Simplify vec_merge of vec_duplicates into vec_concat

Hi all, Another vec_merge simplification that's missing from simplify-rtx.c is transforming a vec_merge of two vec_duplicates. For example: (set (reg:V2DF 80) (vec_merge:V2DF (vec_duplicate:V2DF (reg:DF 84)) (vec_duplicate:V2DF (reg:DF 81)) (const_int 2))) Can be transformed

[PATCH][AArch64] Add STP pattern to store a vec_concat of two 64-bit registers

Hi all, On top of the previous vec_merge simplifications [1] we can add this pattern to perform a store of a vec_concat of two 64-bit values in distinct registers as an STP. This avoids constructing such a vector explicitly in a register and storing it as a Q register. This way for the code in

[PATCH 0/3] Rework early return and hot/cold label predictors

Hello. As mentioned in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79489#c1 early-return predictors is currenty not much precise. I decided to come up with GIMPLE_PREDICT statement that I put early and thus more precise numbers can be seen. For SPEC 2017 we can improve the predictor from: HEURIS

[PATCH 1/3] Come up with selftests for predict.c.

gcc/ChangeLog: 2017-05-26 Martin Liska * predict.c (struct branch_predictor): New struct. (test_prediction_value_range): New test. (predict_tests_c_tests): New function. * selftest-run-tests.c (selftest::run_tests): Run the function. * selftest.h: Declar

[PATCH 3/3] Rework cold and hot label attributes in predict.c.

gcc/ChangeLog: 2017-05-26 Martin Liska * gimplify.c (gimplify_label_expr): Insert GIMPLE_PREDICT statements on cold and hot labels. * predict.c (tree_estimate_probability_bb): Remove the prediction from this place. gcc/testsuite/ChangeLog: 2017-05-31 Martin L

[PATCH 2/3] Make early return predictor more precise.

gcc/ChangeLog: 2017-05-26 Martin Liska PR tree-optimization/79489 * gimplify.c (maybe_add_early_return_predict_stmt): New function. (gimplify_return_expr): Call the function. * predict.c (tree_estimate_probability_bb): Remove handling of early re

[PATCH, testsuite] Remove NO_LABEL_VALUES

Hi, this patch removes the additional_flags=-DNO_LABEL_VALUES addition, and instead uses the effective target label_values (introduced here: https://gcc.gnu.org/ml/gcc-patches/2014-10/msg02087.html ). Tested on x86_64. Tested on nvptx. Tested on nvptx with the '[istarget nvptx-*-*]' clause

Re: [PATCH v8] add -fpatchable-function-entry=N,M option

On Sun, Jun 04, 2017 at 08:12:49PM -0600, Sandra Loosemore wrote: > On 05/29/2017 04:29 AM, Maxim Kuvyrkov wrote: > > >>diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > >>index 65308c9d933..6cbb77a8dc4 100644 > >>--- a/gcc/doc/invoke.texi > >>+++ b/gcc/doc/invoke.texi > >>@@ -11382,6 +1138

Re: [PATCH,testsuite] Add check_effective_target_rdynamic and use it in g++.dg/lto/pr69589_0.C.

Hi Toma, >> Thanks for fixing this! Do you have plan to backport the fix to gcc-6 branch? > > I am happy to backport it. > I've rebased the patch on top of the gcc-6 branch and attached it below. > > Rainer, is this OK for gcc-6? sure, thanks. Rainer > gcc/ChangeLog: > > Backport

Re: [PATCH][Aarch64] Add vectorized mersenne twister

On Fri, Jun 02, 2017 at 07:13:17PM +0100, Jonathan Wakely wrote: > On 02/06/17 19:19 +0200, Ulrich Drepper wrote: > >On Fri, Jun 2, 2017 at 5:46 PM, Michael Collison > > wrote: > >>This implementation includes "arm_neon.h" when including the optimized > >>. This has the effect of polluting the gl

Re: [PATCH, GCC/LTO, ping3] Fix PR69866: LTO with def for weak alias in regular object file

On 09/05/17 23:36, Jan Hubicka wrote: Ping? Sorry for late reply My turn to apologize now. Hi, This patch fixes an assert failure when linking one LTOed object file having a weak alias with a regular object file containing a strong definition for that same symbol. The patch is twofold: + d

Re: [PATCH][Aarch64] Add vectorized mersenne twister

On 06/06/17 11:07 +0100, James Greenhalgh wrote: On Fri, Jun 02, 2017 at 07:13:17PM +0100, Jonathan Wakely wrote: On 02/06/17 19:19 +0200, Ulrich Drepper wrote: >On Fri, Jun 2, 2017 at 5:46 PM, Michael Collison > wrote: >>This implementation includes "arm_neon.h" when including the optimized .

[PATCH] Another extract_muldiv-induced overflow (PR sanitizer/80932)

Another case of extract_muldiv running off the rails. Here it did a wrong distribution; turning ((A * x) - (B * x)) * -6 into (A' * x) - (B' * x) incurred an overflow in the subtraction. The fix is essentially the same as what I did in sanitizer/80800. Bootstrapped/regtested on x86_64-l

Re: [PATCH 1/3] Come up with selftests for predict.c.

On Tue, 2017-06-06 at 10:55 +0200, marxin wrote: Some minor nits below. > gcc/ChangeLog: > > 2017-05-26 Martin Liska > > * predict.c (struct branch_predictor): New struct. > (test_prediction_value_range): New test. > (predict_tests_c_tests): New function. > * selftest

Re: [PATCH][Aarch64] Add vectorized mersenne twister

On 06/06/17 11:23 +0100, Jonathan Wakely wrote: On 06/06/17 11:07 +0100, James Greenhalgh wrote: On Fri, Jun 02, 2017 at 07:13:17PM +0100, Jonathan Wakely wrote: On 02/06/17 19:19 +0200, Ulrich Drepper wrote: On Fri, Jun 2, 2017 at 5:46 PM, Michael Collison wrote: This implementation include

[RFC][AARCH64]Add 'r' integer register operand modifier. Document the common asm modifier for aarch64 target.

Hi all, In this patch, a new integer register operand modifier 'r' is added. This will use the proper register name according to the mode of corresponding operand. 'w' register for scalar integer mode smaller than DImode 'x' register for DImode This allows more flexibility and would meet peopl

Re: [PATCH] C/C++: fix quoting of "aka" typedef information (PR 62170)

On Mon, Jun 05, 2017 at 03:01:34PM -0400, David Malcolm wrote: > PR 62170 describes a problem with how the quoting in pp_format > interacts with the "aka" information for typedefs in %qT for > the C family of frontends, and also now for %qH and %qI in the > C++ frontend. > > Currently for %qT we p

Re: [Patch, fortran] PR35339 Optimize implied do loops in io statements

On 2017.06.05 at 22:39 +0200, Nicolas Koenig wrote: > With all the style fixes committed as r248877. 171_swim fails now. I didn't bisect, but I suspect your revision. -- Markus

Re: [PING] [PING] Make the OpenACC C++ acc_on_device wrapper "always inline"

Hi Jakub! On Tue, 6 Jun 2017 08:58:21 +0200, Jakub Jelinek wrote: > On Tue, Jun 06, 2017 at 08:35:40AM +0200, Thomas Schwinge wrote: > > > > commit 9cc3a384c17e9f692f7864c604d2e2f9fbf0bac9 > > > > Author: Thomas Schwinge > > > > Date: Tue May 23 13:21:14 2017 +0200 > > > > > > > > Make th

Re: [PING] [PING] Make the OpenACC C++ acc_on_device wrapper "always inline"

On Tue, Jun 06, 2017 at 01:16:03PM +0200, Thomas Schwinge wrote: > On Tue, 6 Jun 2017 08:58:21 +0200, Jakub Jelinek wrote: > > On Tue, Jun 06, 2017 at 08:35:40AM +0200, Thomas Schwinge wrote: > > > > > commit 9cc3a384c17e9f692f7864c604d2e2f9fbf0bac9 > > > > > Author: Thomas Schwinge > > > > > Dat

Re: [PATCH][Aarch64] Add vectorized mersenne twister

On Tue, Jun 6, 2017 at 12:07 PM, James Greenhalgh wrote: > We're a good number of years late to do that without causing some pain. Well, it's pain for those who deserve it. Who thought it to be a smart idea to pollute the global namespace? It's a one-time deal. > So we have a few solutions to

Re: [PATCH][Aarch64] Add vectorized mersenne twister

On Tue, Jun 06, 2017 at 11:47:45AM +0100, Jonathan Wakely wrote: > On 06/06/17 11:23 +0100, Jonathan Wakely wrote: > >On 06/06/17 11:07 +0100, James Greenhalgh wrote: > >>On Fri, Jun 02, 2017 at 07:13:17PM +0100, Jonathan Wakely wrote: > >>>On 02/06/17 19:19 +0200, Ulrich Drepper wrote: > On Fr

Re: [PATCH][Aarch64] Add vectorized mersenne twister

On 06/06/17 12:33 +0100, James Greenhalgh wrote: On Tue, Jun 06, 2017 at 11:47:45AM +0100, Jonathan Wakely wrote: On 06/06/17 11:23 +0100, Jonathan Wakely wrote: >On 06/06/17 11:07 +0100, James Greenhalgh wrote: >>On Fri, Jun 02, 2017 at 07:13:17PM +0100, Jonathan Wakely wrote: >>>On 02/06/17 19

Re: [PATCH][Aarch64] Add vectorized mersenne twister

On 6 June 2017 at 11:07, James Greenhalgh wrote: > If we don't mind that, and instead take a GCC-centric view, we could avoid > namespace polution by using the GCC-internal names for the intrinsics > (__builtin_aarch64_...). As those names don't form a guaranteed interface, > that would tie us to

Re: [PATCH][Aarch64] Add vectorized mersenne twister

On 06/06/17 12:41 +0100, Charles Baylis wrote: On 6 June 2017 at 11:07, James Greenhalgh wrote: If we don't mind that, and instead take a GCC-centric view, we could avoid namespace polution by using the GCC-internal names for the intrinsics (__builtin_aarch64_...). As those names don't form a

RE: [PATCH,testsuite] Add check_effective_target_rdynamic and use it in g++.dg/lto/pr69589_0.C.

Thanks, Rainer. Committed as r248916. Thanks for suggesting a backport, Renlin. Regards, Toma

[nvptx, committed] Use maybe_split_mode in nvptx_print_operand

Hi, this patch uses maybe_split_mode in nvptx_print_operand. Committed as trivial. Thanks, - Tom Use maybe_split_mode in nvptx_print_operand 2017-05-12 Tom de Vries * config/nvptx/nvptx.c (nvptx_print_operand): Use maybe_split_mode. --- gcc/config/nvptx/nvptx.c | 7 +++ 1 file chang

[nvptx, committed] Add and use split_mode_p

Hi, this patch adds and uses new utility function split_mode_p. Committed as trivial. Thanks, - Tom Add and use split_mode_p 2017-05-12 Tom de Vries * config/nvptx/nvptx.c (split_mode_p): New function. (nvptx_declare_function_name, nvptx_print_operand): Use split_mode_p. --- gcc/config

Re: [PATCH] remove incorrect assert

On Mon, Jun 5, 2017 at 1:14 PM, Gaius Mulley wrote: > > Hi, > > here is a tiny patch which removes an assert which I believe is wrong. > I think it is an anomaly as the only callee (determine_max_movement at > gcc/tree-ssa-loop-im.c:749) tests the asserted result against NULL. (If > the assert re

Re: [PATCH] gcc::context creation

On Mon, 5 Jun 2017, Nathan Sidwell wrote: > On 06/05/2017 08:50 AM, Jakub Jelinek wrote: > > > It was the intent that there is no unnecessary gap, the difference > > between those two should be simply the maximum any FE registers. > > So, on your branch you'd bump it to 4 and on trunk when mergin

[PATCH] Fix PR80974

The following fixes PR80974 by not being too clever when preserving SSA info during VN. I didn't want to invent a way to unwind changes done in this hack. Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk. Richard. 2017-06-06 Richard Biener PR tree-optimization/

Re: [PATCH][GCC][AArch64][ARM] Modify idiv costs for Cortex-A53

On Tue, May 02, 2017 at 04:37:21PM +0100, Tamar Christina wrote: > Hi All, > > This patch adjusts the cost model for Cortex-A53 to increase the costs of > an integer division. The reason for this is that we want to always expand > the division to a multiply when doing a division by constant. > >

[nvptx, PATCH, 1/3] Add generic v2 vector mode support

Hi, this patch adds generic v2 vector mode support for nvptx. Tested in nvptx mainkernel mode and x86_64 accelerator mode. OK for trunk? Thanks, - Tom Add generic v2 vector mode support 2017-06-06 Tom de Vries * config/nvptx/nvptx.c (nvptx_print_operand): Handle v2 vector mode. --- gcc

[nvptx, PATCH, 2/3 ] Add v2si support

Hi, this patch adds v2si support to the nvptx target. Tested in nvptx mainkernel mode and x86_64 accelerator mode. OK for trunk? Thanks, - Tom Add v2si support 2017-06-06 Tom de Vries * config/nvptx/nvptx-modes.def: New file. Add V2SImode. * config/nvptx/nvptx.c (nvptx_ptx_type_from_m

[PATCH] libgo: fix support for ia64

This adds support for ia64 in lfstack. Andreas. diff --git a/libgo/go/runtime/lfstack_64bit.go b/libgo/go/runtime/lfstack_64bit.go index b314a3ba21..99dcec02de 100644 --- a/libgo/go/runtime/lfstack_64bit.go +++ b/libgo/go/runtime/lfstack_64bit.go @@ -2,7 +2,7 @@ // Use of this source code is go

Re: [PATCH][GCC][AARCH64]Adjust costs so udiv is preferred over sdiv when both are valid. [Patch (1/2)]

On Tue, May 02, 2017 at 04:37:16PM +0100, Tamar Christina wrote: > Hi All, > > This patch adjusts the cost model so that when both sdiv and udiv are possible > it prefers udiv over sdiv. This was done by making sdiv slightly more > expensive > instead of making udiv cheaper to keep the baseline

[nvptx, PATCH, 3/3] Add v2di support

Hi, this patch adds v2di support to the nvptx target. This allows us to generate 128-bit loads and stores. Tested in nvptx mainkernel mode and x86_64 accelerator mode. OK for trunk? Thanks, - Tom Add v2di support 2017-06-06 Tom de Vries * config/nvptx/nvptx-modes.def: Add V2DImode. *

Re: [PING] Re: [PATCH] Fix-it hints for -Wimplicit-fallthrough

On Fri, May 26, 2017 at 02:13:56PM -0600, Martin Sebor wrote: > On 05/26/2017 01:59 PM, David Malcolm wrote: > > Ping: > > https://gcc.gnu.org/ml/gcc-patches/2017-05/msg00334.html > > > > On Thu, 2017-05-04 at 14:16 -0400, David Malcolm wrote: > > > As of r247522, fix-it-hints can suggest the in

Re: [PATCH][AArch64] Allow const0_rtx operand for atomic compare-exchange patterns

On Tue, Feb 28, 2017 at 12:29:50PM +, Kyrill Tkachov wrote: > Hi all, > > For the testcase in this patch we currently generate: > foo: > mov w1, 0 > ldaxr w2, [x0] > cmp w2, 3 > bne .L2 > stxrw3, w1, [x0] > cmp w3, 0 > .L2:

Re: [PATCH][AArch64] Add STP pattern to store a vec_concat of two 64-bit registers

On Tue, Jun 06, 2017 at 09:40:44AM +0100, Kyrill Tkachov wrote: > Hi all, > > On top of the previous vec_merge simplifications [1] we can add this pattern > to perform > a store of a vec_concat of two 64-bit values in distinct registers as an STP. > This avoids constructing such a vector explicit

Re: [PATCH][GCC][AArch64][ARM] Modify idiv costs for Cortex-A53

On Tue, Jun 6, 2017 at 1:56 PM, James Greenhalgh wrote: > On Tue, May 02, 2017 at 04:37:21PM +0100, Tamar Christina wrote: >> Hi All, >> >> This patch adjusts the cost model for Cortex-A53 to increase the costs of >> an integer division. The reason for this is that we want to always expand >> the

Re: [PATCH][AArch64] Add crypto_pmull attribute

On Fri, Mar 10, 2017 at 06:37:30AM +, Hurugalawadi, Naveen wrote: > Hi James, > > >> You need to do this for all cores which might be affected by this change, > >> i.e. all those which model neon_mul_d_long. > > Thanks for pointing out the missing cores in patch. > Added the support as per yo

Re: [PATCH] Introduce 4-stages profiledbootstrap to get a better profile.

On 05/29/2017 07:04 AM, Markus Trippelsdorf wrote: > On 2017.05.25 at 11:55 +0200, Martin Liška wrote: >> Hi. >> >> As I spoke about the PGO with Honza and Richi, current 3-stage is not ideal >> for following >> 2 reasons: >> >> 1) stageprofile compiler is train just on libraries that are built du

Re: [Patch AArch64] Do not increase data alignment at -Os and with -fconserve-stack.

Ping.. Ramana On Tue, May 2, 2017 at 10:52 AM, Ramana Radhakrishnan wrote: > We unnecessarily align data to 8 byte alignments even when -Os is specified. > This brings the logic in the AArch64 backend more in line with the ARM > backend and helps gain some image size in a few places. Caught by a

Re: [PATCH][GCC][AArch64] Fix subreg bug in scalar copysign

On Wed, Mar 15, 2017 at 04:04:35PM +, Tamar Christina wrote: > Hi All, > > This fixes a bug in the scalar version of copysign where due to a subreg > were generating less than efficient code. > > This patch replaces > > return x * __builtin_copysignf (150.0f, y); > > which used to genera

How to do scan-tree-dump for test.o

[ was: Re: [nvptx, PATCH, 3/3] Add v2di support ] On 06/06/2017 03:12 PM, Tom de Vries wrote: diff --git a/libgomp/testsuite/libgomp.oacc-c/vec.c b/libgomp/testsuite/libgomp.oacc-c/vec.c new file mode 100644 index 000..79c1c17 --- /dev/null +++ b/libgomp/testsuite/libgomp.oacc-c/vec.c @@ -0

Re: [PATCH 0/13] D: Submission of D Front End

On 29 May 2017 at 22:57, Eric Botcazou wrote: >> The upstream DMD compiler that comprises all components of the >> standalone part is now implemented in D programming language itself. >> However here GDC is still using the C++ implementation, it is a future >> goal to switch to being a self-hosted

Re: How to do scan-tree-dump for test.o

On Tue, Jun 6, 2017 at 3:39 PM, Tom de Vries wrote: > [ was: Re: [nvptx, PATCH, 3/3] Add v2di support ] > > On 06/06/2017 03:12 PM, Tom de Vries wrote: >> >> diff --git a/libgomp/testsuite/libgomp.oacc-c/vec.c >> b/libgomp/testsuite/libgomp.oacc-c/vec.c >> new file mode 100644 >> index 000..79

Re: [PATCH 9/13] D: D2 Testsuite Dejagnu files.

On 31 May 2017 at 11:11, Matthias Klose wrote: > On 30.05.2017 16:32, Mike Stump wrote: >> On May 28, 2017, at 2:16 PM, Iain Buclaw wrote: >>> >>> This patch adds D language support to the GCC test suite. >> >> Ok. If you could ensure that gcc without D retains all it's goodness and >> that gcc

Re: [PATCH, testsuite] Remove NO_LABEL_VALUES

On Jun 6, 2017, at 2:23 AM, Tom de Vries wrote: > > OK for trunk? Ok.

[C++/80979] ADL of friends

This fixes 80979, and ICE in the new duplicate lookup matching code. That code is enabled when we discover using declarations are in play. And it was barfing on meeting an already-marked function. That function was in the lookup twice, which was a surprise. That had happened because the functi

[PATCH 00/14] rs6000: Delete SPE things

This series removes most SPE things. Tested (all languages) on powerpc64-linux (power7, {-m32,-m64}); on powerpc64le-linux (power8, all languages); on AIX (power7, default languages); on powerpc-linux (compile only) and on powerpc-linux-gnuspe (compile only). Is this okay for trunk? Segher Se

[PATCH 01/14] rs6000: Remove TARGET_FPRS

Since rs6000 no longer supports SPE, TARGET_FPRS now always is true. This makes TARGET_{SF,DF}_SPE always false. Many patterns in spe.md can now be deleted; which makes it possible to merge e.g. negdd2 with *negdd2_fpr. Finally, e500.h is deleted (it isn't used). 2017-06-06 Segher Boessenkool

[PATCH 03/14] rs6000: Remove -mfloat-gprs

This deletes -mfloat-gprs and the variables that go with it. 2017-06-06 Segher Boessenkool * config/rs6000/rs6000.c: Remove everything related to -mfloat-gprs. * config/rs6000/rs6000.opt: Ditto. * config/rs6000/t-rtems: Ditto. --- gcc/config/rs6000/rs6000.c | 12 +-

[PATCH 02/14] rs6000: Remove TARGET_E500_{SINGLE,DOUBLE}

Similarly, TARGET_E500_{SINGLE,DOUBLE} is always false now. 2017-06-06 Segher Boessenkool * config/rs6000/predicates.md: Replace TARGET_E500_DOUBLE and TARGET_E500_SINGLE by 0, simplify. * config/rs6000/rs6000.c: Ditto. (rs6000_option_override_internal): Delete

[PATCH 04/14] rs6000: Remove rs6000_cbranch_operator

rs6000_cbranch_operator now is just comparison_operator, so just use that directly. 2017-06-06 Segher Boessenkool * config/rs6000/predicated.md (rs6000_cbranch_operator): Delete. * config/rs6000/rs6000.md: Replace rs6000_cbranch_operator by comparison_operator. --- g

[PATCH 05/14] rs6000: Remove output_e500_flip_gt_bit

2017-06-06 Segher Boessenkool * config/rs6000/rs6000-protos.h (output_e500_flip_gt_bit): Delete. * config/rs6000/rs6000.c: Ditto. --- gcc/config/rs6000/rs6000-protos.h | 1 - gcc/config/rs6000/rs6000.c| 18 -- 2 files changed, 19 deletions(-) diff --g

[PATCH 06/14] rs6000: Remove UNSPEC_MV_CR_GT

2017-06-06 Segher Boessenkool config/rs6000/rs6000.md (UNSPEC_MV_CR_GT): Delete. --- gcc/config/rs6000/rs6000.md | 1 - 1 file changed, 1 deletion(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 108ad8f..997d1fe 100644 --- a/gcc/config/rs6000/rs6000.m

[PATCH 08/14] rs6000: Remove -mspe options

2017-06-06 Segher Boessenkool * config/rs6000/rs6000.c (rs6000_option_override_internal): Delete handling of SPE flags. * config/rs6000/rs6000.opt (-mspe, -mspe=no, -mspe=yes): Delete. --- gcc/config/rs6000/rs6000.c | 18 -- gcc/config/rs6000/rs6000.o

[PATCH 09/14] rs6000: Remove reg_or_none500mem_operand

2017-06-06 Segher Boessenkool * config/rs6000/predicates.md (reg_or_mem_operand): Reformat. (reg_or_none500mem_operand): Delete. * config/rs6000/rs6000.md (extendsfdf2): Use reg_or_mem_operand instead of reg_or_none500mem_operand. --- gcc/config/rs6000/predicat

[PATCH 10/14] rs6000: Remove spe.md, spe.h, linuxspe.h

2017-06-06 Segher Boessenkool * config.gcc (powerpc*-*-*): Don't add spe.h to extra_headers. (powerpc*-linux*spe*): Use ${cpu_type} instead of rs6000. * config/rs6000/linuxspe.h: Delete file. * config/rs6000/rs6000.md: Don't include spe.md. * config/rs600

[PATCH 12/14] rs6000: Remove SPE high registers

Now we can remove the SPE high registers. 2017-06-06 Segher Boessenkool * config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE high registers. * config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto. * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER)

[PATCH 11/14] rs6000: Remove type attribute "brinc"

Nothing uses it anymore. 2017-06-06 Segher Boessenkool * config/rs6000/8540.md (ppc8540_brinc): Delete. * config/rs6000/e500mc.md (e500mc_brinc): Delete. * config/rs6000/e500mc64.md (e500mc64_brinc): Delete. * config/rs6000/rs6000.md (type): Remove "brinc". --

[PATCH 13/14] rs6000: Remove spe_acc and spefscr

We can also remove the two other SPE registers. 2017-06-06 Segher Boessenkool * config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE_ACC and SPEFSCR registers. * config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto. (enum rs6000_reg_type): Delete

[PATCH 14/14] rs6000: Remove rs6000_nonimmediate_operand

Now rs6000_nonimmediate_operand is just nonimmediate_operand. 2017-06-06 Segher Boessenkool * config/rs6000/predicates.md (rs6000_nonimmediate_operand): Delete. * config/rs6000/rs6000.md (*movsi_internal1, movsi_from_sf, *mov_softfloat, and an anonymous splitter): Use

Re: RFC: [PATCH] Add warn_if_not_aligned attribute

On 06/05/2017 11:45 AM, H.J. Lu wrote: On Mon, Jun 5, 2017 at 8:11 AM, Joseph Myers wrote: The new attribute needs documentation. Should the test be in c-c++-common This feature does support C++. But C++ compiler issues a slightly different warning at a different location. or does this fe

Re: RFC: [PATCH] Add warn_if_not_aligned attribute

On 06/06/2017 10:07 AM, Martin Sebor wrote: On 06/05/2017 11:45 AM, H.J. Lu wrote: On Mon, Jun 5, 2017 at 8:11 AM, Joseph Myers wrote: The new attribute needs documentation. Should the test be in c-c++-common This feature does support C++. But C++ compiler issues a slightly different warni

Re: Reorgnanization of profile count maintenance code, part 1

Hi! On Thu, Jun 01, 2017 at 01:35:56PM +0200, Jan Hubicka wrote: > + /* FIXME: shrink wrapping violates this sanity check. */ > + gcc_checking_assert ((num >= 0 > + && (num <= REG_BR_PROB_BASE > + || den <= REG_BR_PROB_BASE) > +

Re: Fix PR rtl-optimization/80474

On 06/05/2017 04:40 PM, Eric Botcazou wrote: > This is a regression present on the 6 branch for MIPS (and latent on the 7 > branch and mainline). The reorg pass generates wrong code for the attached > testcase with a combination of options under the form of a double lo_sum(sym) > instruction fo

Re: [PATCH, rs6000] Fold vector shifts in GIMPLE

On Thu, 2017-06-01 at 10:15 -0500, Bill Schmidt wrote: > > On Jun 1, 2017, at 2:48 AM, Richard Biener > > wrote: > > > > On Wed, May 31, 2017 at 10:01 PM, Will Schmidt > > wrote: > >> Hi, > >> > >> Add support for early expansion of vector shifts. Including > >> vec_sl (shift left), vec_sr (s

C PATCH to improve enum and struct redefinition diagnostic (PR c/79983)

This patch brings better enum and struct redefinition diagnostic. In particular, we'll now point to the first definition in the "originally defined here" note, not to the forward declaration. Now, you could argue that we don't have to be setting the location by lookup_tag at all, because we shou

Re: C PATCH to improve enum and struct redefinition diagnostic (PR c/79983)

On Tue, 6 Jun 2017, Marek Polacek wrote: > 2017-06-06 Marek Polacek > > PR c/79983 > * c-decl.c (start_struct): Use the location of TYPE_STUB_DECL of > ref. > (start_enum): Use the location of TYPE_STUB_DECL of enumtype. > > * gcc.dg/pr79983.c: New test. OK. --

Re: [PATCH] handle bzero/bcopy in DSE and aliasing (PR 80933, 80934)

On 06/04/2017 09:36 AM, Bernhard Reutner-Fischer wrote: > On 2 June 2017 13:12:41 CEST, Richard Biener > wrote: > >> Note I'd be _much_ more sympathetic to simply canonicalizing all of >> bzero and bcopy >> to memset / memmove and be done with all the above complexity. > > Indeed and even more

Re: RFC: [PATCH] Add warn_if_not_aligned attribute

On Tue, Jun 6, 2017 at 9:10 AM, Martin Sebor wrote: > On 06/06/2017 10:07 AM, Martin Sebor wrote: >> >> On 06/05/2017 11:45 AM, H.J. Lu wrote: >>> >>> On Mon, Jun 5, 2017 at 8:11 AM, Joseph Myers >>> wrote: The new attribute needs documentation. Should the test be in c-c++-common

Re: [PATCH 01/14] rs6000: Remove TARGET_FPRS

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > Since rs6000 no longer supports SPE, TARGET_FPRS now always is true. > > This makes TARGET_{SF,DF}_SPE always false. Many patterns in spe.md > can now be deleted; which makes it possible to merge e.g. negdd2 with > *negdd2_fpr. > > Fina

Re: [PATCH 02/14] rs6000: Remove TARGET_E500_{SINGLE,DOUBLE}

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > Similarly, TARGET_E500_{SINGLE,DOUBLE} is always false now. > > > 2017-06-06 Segher Boessenkool > > * config/rs6000/predicates.md: Replace TARGET_E500_DOUBLE and > TARGET_E500_SINGLE by 0, simplify. > * config/

Re: [PATCH 03/14] rs6000: Remove -mfloat-gprs

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > This deletes -mfloat-gprs and the variables that go with it. > > > 2017-06-06 Segher Boessenkool > > * config/rs6000/rs6000.c: Remove everything related to -mfloat-gprs. > * config/rs6000/rs6000.opt: Ditto. > *

Re: [PATCH 04/14] rs6000: Remove rs6000_cbranch_operator

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > rs6000_cbranch_operator now is just comparison_operator, so just use > that directly. > > > 2017-06-06 Segher Boessenkool > > * config/rs6000/predicated.md (rs6000_cbranch_operator): Delete. > * config/rs6000/rs6000.md

Re: [PATCH 05/14] rs6000: Remove output_e500_flip_gt_bit

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > 2017-06-06 Segher Boessenkool > > * config/rs6000/rs6000-protos.h (output_e500_flip_gt_bit): Delete. > * config/rs6000/rs6000.c: Ditto. Okay. Thanks, David

Re: [PATCH 06/14] rs6000: Remove UNSPEC_MV_CR_GT

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > 2017-06-06 Segher Boessenkool > > config/rs6000/rs6000.md (UNSPEC_MV_CR_GT): Delete. Okay. Thanks, David

Re: [PATCH 07/14] rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > 2017-06-06 Segher Boessenkool > > * config/rs6000/rs6000-common.c (rs6000_handle_option): Remove > SPE ABI handling. > * config/rs6000/paired.md (paired_negv2sf2): Rename to negv2sf2. > (paired_absv2sf2

Re: [PATCH 08/14] rs6000: Remove -mspe options

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > 2017-06-06 Segher Boessenkool > > * config/rs6000/rs6000.c (rs6000_option_override_internal): Delete > handling of SPE flags. > * config/rs6000/rs6000.opt (-mspe, -mspe=no, -mspe=yes): Delete. Okay. Thanks, D

Re: [PATCH 09/14] rs6000: Remove reg_or_none500mem_operand

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > 2017-06-06 Segher Boessenkool > > * config/rs6000/predicates.md (reg_or_mem_operand): Reformat. > (reg_or_none500mem_operand): Delete. > * config/rs6000/rs6000.md (extendsfdf2): Use reg_or_mem_operand >

Re: [PATCH 10/14] rs6000: Remove spe.md, spe.h, linuxspe.h

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > 2017-06-06 Segher Boessenkool > > * config.gcc (powerpc*-*-*): Don't add spe.h to extra_headers. > (powerpc*-linux*spe*): Use ${cpu_type} instead of rs6000. > * config/rs6000/linuxspe.h: Delete file. >

Re: [PATCH 11/14] rs6000: Remove type attribute "brinc"

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > Nothing uses it anymore. > > > 2017-06-06 Segher Boessenkool > > * config/rs6000/8540.md (ppc8540_brinc): Delete. > * config/rs6000/e500mc.md (e500mc_brinc): Delete. > * config/rs6000/e500mc64.md (e500mc64_brin

Re: [PATCH 12/14] rs6000: Remove SPE high registers

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > Now we can remove the SPE high registers. > > > 2017-06-06 Segher Boessenkool > > * config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE high > registers. > * config/rs6000/rs6000.c (rs6000_reg_names, alt_re

Re: [PATCH 13/14] rs6000: Remove spe_acc and spefscr

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > We can also remove the two other SPE registers. > > > 2017-06-06 Segher Boessenkool > > * config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE_ACC and > SPEFSCR registers. > * config/rs6000/rs6000.c (rs6000_

Re: [PATCH 14/14] rs6000: Remove rs6000_nonimmediate_operand

On Tue, Jun 6, 2017 at 11:56 AM, Segher Boessenkool wrote: > Now rs6000_nonimmediate_operand is just nonimmediate_operand. > > > 2017-06-06 Segher Boessenkool > > * config/rs6000/predicates.md (rs6000_nonimmediate_operand): Delete. > * config/rs6000/rs6000.md (*movsi_internal1,

Re: [PATCH 0/5 v3] Vect peeling cost model

http://gcc.gnu.org/ml/gcc-testresults/2017-06/msg00297.html Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5 "And now for something completely different."

Re: RFC: [PATCH] Add warn_if_not_aligned attribute

On 06/06/2017 10:59 AM, H.J. Lu wrote: On Tue, Jun 6, 2017 at 9:10 AM, Martin Sebor wrote: On 06/06/2017 10:07 AM, Martin Sebor wrote: On 06/05/2017 11:45 AM, H.J. Lu wrote: On Mon, Jun 5, 2017 at 8:11 AM, Joseph Myers wrote: The new attribute needs documentation. Should the test be in

Re: [PATCH 1/1] Remove redundant definition of srcrootpre

On 06/05/2017 01:30 AM, coypu wrote: > This script has the only occurrence of it, and in this line > it defines and exports it. > > --- > config-ml.in | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/config-ml.in b/config-ml.in > index 47f153350..58c80a35c 100644 > --- a/config-ml.in > ++

Re: [PATCH GCC][5/5]Enable tree loop distribution at -O3 and above optimization levels.

On 06/02/2017 05:52 AM, Bin Cheng wrote: > Hi, > This patch enables -ftree-loop-distribution by default at -O3 and above > optimization levels. > Bootstrap and test at O2/O3 on x86_64 and AArch64. is it OK? > > Note I don't have strong opinion here and am fine with either it's accepted > or rej

Re: [PATCH 9/13] D: D2 Testsuite Dejagnu files.

On 31 May 2017 at 01:32, Mike Stump wrote: > On May 28, 2017, at 2:16 PM, Iain Buclaw wrote: >> >> This patch adds D language support to the GCC test suite. > > Ok. If you could ensure that gcc without D retains all it's goodness and > that gcc with D works on 2 different systems, that will hel

Re: MinGW compilation warnings in libiberty's waitpid.c

On 30 May 2017 at 19:10, Joel Brobecker wrote: >> This has been on my todo-list for a little while, as re-syncing is >> something I normally do after pushing D language support updates into >> libiberty. However I decided to give it a wait until I got all >> pending patches in, the last of which

Re: [PATCH 9/13] D: D2 Testsuite Dejagnu files.

On Jun 6, 2017, at 10:48 AM, Iain Buclaw wrote: >> Something this large can be integration tested on a svn/git branch, if you >> need others to help out. >> > > It would probably be easier for me to maintain also, rather than > continuously regenerating patches each time I make an update to > r

Clarify define_insn documentation

This patch tries to clarify some of the restrictions on define_insn conditions, and also on the use of "#". OK to install? Richard 2017-06-06 Richard Sandiford gcc/ * doc/md.texi: Clarify the restrictions on a define_insn condition. Say that # requires an associated define_s

Re: [PATCH][SPARC] PR target/80968 Prevent stack loads in return delay slot.

From: David Miller Date: Mon, 05 Jun 2017 20:54:46 -0400 (EDT) > From: Eric Botcazou > Date: Tue, 06 Jun 2017 00:02:06 +0200 > >>> That seems to work as well, following is going through a testsuite >>> run right now: >>> >>> >>> [PATCH] sparc: Fix stack references in retur

[PATCH] PR c++/80990 use cv-qualifiers in class template argument deduction

This fixes class template argument deduction so that cv-qualifiers are not ignored. Bootstrapped and tested powerpc64le-linux. OK for trunk? PR c++/80990 * pt.c (do_class_deduction): Build qualified type. commit 1a81d74fa9cf32cb33580cc4a5e9a7c5868ce32b Author: Jonathan Wakely D

Re: [gcn][patch] Add -mgpu option and plumb in assembler/linker

On 29/05/17 18:27, Martin Jambor wrote: I apologize for taking so long to reply, I was traveling for two past weeks and just before that we suffered some local infrastructure issues that prevented me from working on this too. And I've just been on vacation for a week. :-) On Fri, Apr 28, 2017

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