Re: [PATCH/libiberty] Remove use of strtod in libiberty/d-demangle.c

On Tue, Aug 4, 2015 at 7:23 AM, Iain Buclaw wrote: > > Fixes PR 18669 raised against gdb/binutils. > > https://sourceware.org/bugzilla/show_bug.cgi?id=18669 > > While it is possible to roll our own strtod that handles hexadecimal > to float conversion, I'm no longer interested taking time out to >

Re: [PR64164] drop copyrename, integrate into expand

On Tue, Aug 04, 2015 at 12:45:28AM +0100, Alexandre Oliva wrote: > On Jul 30, 2015, "H.J. Lu" wrote: > > > aoliva/pr64164 is fine on x32. > > Thanks. I have made a large number of changes since you tested it, > fixing all the reported issues and then some. Now, x86_64-linux-gnu > (-m64 and -m

Re: [PATCH][RTL-ifcvt] Improve conditional select ops on immediates

On 04/08/15 09:44, Kyrill Tkachov wrote: On 03/08/15 18:37, Uros Bizjak wrote: On Mon, Aug 3, 2015 at 7:20 PM, Kyrill Tkachov wrote: Looking at the x86 movcc expansion code (ix86_expand_int_movcc) I don't think this is a good idea. In the expander, there is already quite some target-dependen

Re: [PATCH][RTL-ifcvt] Improve conditional select ops on immediates

On Mon, Aug 10, 2015 at 11:36 AM, Kyrill Tkachov wrote: I'm testing a patch that fix the testcases on x86_64 and does not harm codegen on aarch64. Feel free to file a PR and assign it to me. >>> >>> PR67103 [1] >>> >>> [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67103 >> >> Thanks,

Re: [PATCH][RTL-ifcvt] Improve conditional select ops on immediates

On 10/08/15 10:43, Uros Bizjak wrote: On Mon, Aug 10, 2015 at 11:36 AM, Kyrill Tkachov wrote: I'm testing a patch that fix the testcases on x86_64 and does not harm codegen on aarch64. Feel free to file a PR and assign it to me. PR67103 [1] [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=6

Re: [COMMITTED][AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt

Andreas Schwab writes: > Jiong Wang writes: > >> Index: gcc/ChangeLog >> === >> --- gcc/ChangeLog(revision 226682) >> +++ gcc/ChangeLog(working copy) >> @@ -1,3 +1,16 @@ >> +2015-08-06Ramana Radhakrishnan >> +

Re: [PATCH 2/2][ARM] Use new FPU features representation

Ping. Updated patch attached. Also, retested the series for arm-none-linux-gnueabihf with native bootstrap and make check. On 22/06/15 16:18, Matthew Wahab wrote: Hello, This patch series changes the representation of FPU features to use a simple bit-set and flags, as is done elsewhere. Th

Re: [PATCH 1/2][ARM] Record FPU features as a bit-set

Ping. Updated patch attached. Also, retested the series for arm-none-linux-gnueabihf with native bootstrap and make check. On 22/06/15 16:16, Matthew Wahab wrote: Hello, The ARM backend records FPU features as booleans, one for each feature. This means that adding support for a new feature i

Re: [PATCH 1/2][ARM] Record FPU features as a bit-set

Hi Matthew, On 10/08/15 11:28, Matthew Wahab wrote: Ping. Updated patch attached. Also, retested the series for arm-none-linux-gnueabihf with native bootstrap and make check. On 22/06/15 16:16, Matthew Wahab wrote: Hello, The ARM backend records FPU features as booleans, one for each featur

Re: [PATCH] Fix default_binds_local_p_2 for extern protected data

ping. On 22/07/15 18:01, Szabolcs Nagy wrote: The commit https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=222184 changed a true to false in varasm.c: bool default_binds_local_p_2 (const_tree exp) { - return default_binds_local_p_3 (exp, flag_shlib != 0, true, true); + return defa

Re: [PATCH][ARM][3/3] Expand mod by power of 2

Here is a slight respin. The important parts are the same, just the expander now uses the slightly shorter arm_gen_compare_reg and the rtx costs hunk is moved under an explicit case MOD. Note, the tests still require patch 1/3 that does this for aarch64 that I hope to post a respinned version o

[PATCH 1/5][ARM] Make room for more CPU feature flags.

The ARM backend uses an unsigned long to record CPU feature flags and there are wcurrently 31 bits in use. To be able to support new architecture features, the current representation will need to be replaced so that more flags can be recorded. This series of patches replaces the single unsigned l

[PATCH 2/5][ARM] Add feature set definitions.

The ARM backend uses an unsigned long to record CPU feature flags and there are currently 31 bits in use. This series of patches replaces the single unsigned long with a representation based on an array of values. This patch adds, but doesn't use, type arm_feature_set and macros prefixed with ARM

[PATCH 3/5][ARM] Use new feature set representation.

The ARM backend uses an unsigned long to record CPU feature flags and there are currently 31 bits in use. This series of patches replaces the single unsigned long with a representation based on an array of values. This patch replaces the existing representation of CPU feature sets with the type a

[PATCH 4/5][ARM] Use features sets for builtins.

The ARM backend uses an unsigned long to record CPU feature flags and there are currently 31 bits in use. This series of patches replaces the single unsigned long with a representation based on an array of values. This patch updates the feature flags usage in the builtins description to be able u

[PATCH 5/5][ARM] Move initializer into arm-cores.def and arm-arches.def.

The ARM backend uses an unsigned long to record CPU feature flags and there are currently 30 bits in use. This series of patches replaces the single unsigned long with a representation based on an array of values. This patch updates the entries in the arm-core.def and arm-arches.def files to for

[PATCH 1/2] add GCC_FINAL to ansidecl.h

From: Trevor Saunders Hi, This allows classes and virtual functions to be marked as final if the compiler supports C++11, or is gcc 4.7 or later. bootstrapped + regtested on x86_64-linux-gnu, ok? Trev include/ChangeLog: 2015-08-10 Trevor Saunders * ansidecl.h (GCC_FINAL): New mac

[PATCH 2/2] replace several uses of the anon namespace with GCC_FINAL

From: Trevor Saunders Hi, In many places gcc puts classes in the anon namespace so the compiler can tell they do not get inheritted from to enable better devirtualization. However debugging code in the anon namespace can be a pain, and the same thing can be accomplished more directly by marking

[PATCH 2/4] [MIPS] Add pipeline description for MSA

Hi, The patch adds a pipeline description for MSA to I6400 and P5600 schedulers. Regards, Robert gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_intadd, i6400_fpu_logic) (i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float, i6400_fpu_store) (i6400_fpu_long_pipe, i6400_fpu_log

[PATCH 1/4] [MIPS] Add support for MIPS SIMD Architecture (MSA)

Hi, This series of patches adds the support for MIPS SIMD Architecture (MSA) and underwent a few updates since the last review to address the comments: https://gcc.gnu.org/ml/gcc-patches/2014-05/msg01777.html The series is split into four parts: 0001 [MIPS] Add support for MIPS SIMD Architectur

Re: [COMMITTED][AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt

Jiong Wang writes: > Andreas Schwab writes: > >> Jiong Wang writes: >> >>> Index: gcc/ChangeLog >>> === >>> --- gcc/ChangeLog (revision 226682) >>> +++ gcc/ChangeLog (working copy) >>> @@ -1,3 +1,16 @@ >>> +2015-08-06Ramana

Re: [COMMITTED][AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt

Jiong Wang writes: > And I just finished two round of native aarch64 build/check w/wo my patch. Did you rebuild everything? Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5 "And now for something completely different."

Re: [COMMITTED][AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt

Andreas Schwab writes: > Jiong Wang writes: > >> And I just finished two round of native aarch64 build/check w/wo my patch. > > Did you rebuild everything? No. Just applied the patch, then "make all" and re-check > > Andreas. -- Regards, Jiong

Re: [COMMITTED][AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt

Jiong Wang writes: > Andreas Schwab writes: > >> Jiong Wang writes: >> >>> And I just finished two round of native aarch64 build/check w/wo my patch. >> >> Did you rebuild everything? > > No. Please do. Andreas. -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 58CA 54C7 6D53 94

Re: [PATCH 2/2] replace several uses of the anon namespace with GCC_FINAL

On 2015.08.10 at 08:05 -0400, tbsaunde+...@tbsaunde.org wrote: > > In many places gcc puts classes in the anon namespace so the compiler can tell > they do not get inheritted from to enable better devirtualization. However > debugging code in the anon namespace can be a pain, and the same thing c

Re: PR c/c++/diagnostics/66098 Take -Werror into account when deciding what was the command-line status

PING^2: https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02581.html On 3 August 2015 at 20:47, Manuel López-Ibáñez wrote: > PING: https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02581.html > > Thanks, > > Manuel. > > On 30 July 2015 at 17:35, Manuel López-Ibáñez wrote: >> When I fixed PR59304, I forg

Re: [PATCH 2/2] replace several uses of the anon namespace with GCC_FINAL

On Mon, Aug 10, 2015 at 03:56:02PM +0200, Markus Trippelsdorf wrote: > On 2015.08.10 at 08:05 -0400, tbsaunde+...@tbsaunde.org wrote: > > > > In many places gcc puts classes in the anon namespace so the compiler can > > tell > > they do not get inheritted from to enable better devirtualization.

Re: [PATCH 1/2][ARM] Record FPU features as a bit-set

On Mon, Aug 10, 2015 at 11:28:06AM +0100, Matthew Wahab wrote: > Ping. Updated patch attached. > > Also, retested the series for arm-none-linux-gnueabihf with native > bootstrap and make check. > > On 22/06/15 16:16, Matthew Wahab wrote: > >Hello, > > > >The ARM backend records FPU features as bo

Re: [PATCH 2/2][ARM] Use new FPU features representation

On Mon, Jun 22, 2015 at 04:18:04PM +0100, Matthew Wahab wrote: > Hello, > > This patch series changes the representation of FPU features to use a simple > bit-set and flags, as is done elsewhere. > > This patch uses the new representation of FPU feature sets. > > Tested the series for arm-none-l

Re: [PATCH 2/5][ARM] Add feature set definitions.

On Mon, Aug 10, 2015 at 12:56:59PM +0100, Matthew Wahab wrote: > The ARM backend uses an unsigned long to record CPU feature flags and > there are currently 31 bits in use. This series of patches replaces the > single unsigned long with a representation based on an array of values. > > This patch

Re: [PATCH 1/5][ARM] Make room for more CPU feature flags.

On Mon, Aug 10, 2015 at 12:55:45PM +0100, Matthew Wahab wrote: > The ARM backend uses an unsigned long to record CPU feature flags and > there are wcurrently 31 bits in use. To be able to support new > architecture features, the current representation will need to be > replaced so that more flags c

Re: [PR64164] drop copyrename, integrate into expand

On 08/10/2015 02:23 AM, James Greenhalgh wrote: On Tue, Aug 04, 2015 at 12:45:28AM +0100, Alexandre Oliva wrote: On Jul 30, 2015, "H.J. Lu" wrote: aoliva/pr64164 is fine on x32. Thanks. I have made a large number of changes since you tested it, fixing all the reported issues and then some

Re: Fix offloading machine mode stream reading

Hi! On Sat, 8 Aug 2015 07:25:42 +0200, Richard Biener wrote: > Ok. Committed in r226758 and r226759: commit 7231f6b984806cceb30cacf0e79f8f5ae7a68803 Author: tschwinge Date: Mon Aug 10 15:22:24 2015 + Correctly advance iterator in offloading machine mode stream reading

Empty libgomp for nvptx (was: [WIP] OpenMP 4 NVPTX support)

Hi! On Wed, 22 Jul 2015 18:38:44 +0200, Jakub Jelinek wrote: > On Wed, Jul 22, 2015 at 06:04:20PM +0200, Thomas Schwinge wrote: > > On Tue, 21 Apr 2015 17:58:39 +0200, Jakub Jelinek wrote: > > > Attached is a minimal patch to get at least a trivial OpenMP 4.0 testcase > > > offloading to NVPTX (

Re: [PATCH] PR target/67127: [ARM] Avoiding odd-number ldrd/strd in movdi introduced a regression on armeb-linux-gnueabihf

Yvan Roux wrote: Hi, this patch is a fix for pr27127. It avoids splitting the DI registers into SI ones if it is not allowed, which breaks the introduced loop. I haven't added a testcase as the bug is already exhibited by several regressions (like g++.dg/ext/attribute-test-2.C or g++.dg/eh/simd

Re: Empty libgomp for nvptx

Hi! On Mon, 10 Aug 2015 17:55:57 +0200, I wrote: > On Wed, 22 Jul 2015 18:38:44 +0200, Jakub Jelinek wrote: > > On Wed, Jul 22, 2015 at 06:04:20PM +0200, Thomas Schwinge wrote: > > > On Tue, 21 Apr 2015 17:58:39 +0200, Jakub Jelinek > > > wrote: > > > > Attached is a minimal patch to get at lea

[gomp4] [nvptx] Move GOMP stuff from libgcc to libgomp (was: [WIP] OpenMP 4 NVPTX support)

Hi! On Wed, 22 Jul 2015 18:04:20 +0200, I wrote: > On Tue, 21 Apr 2015 17:58:39 +0200, Jakub Jelinek wrote: > > Attached is a minimal patch to get at least a trivial OpenMP 4.0 testcase > > offloading to NVPTX (the first patch). The second patch is WIP, just first > > few needed changes to make

Re: libgomp: plugin for non-shared memory host execution

Hi! On Fri, 31 Jul 2015 16:16:59 +0200, I wrote: > On Thu, 30 Jul 2015 13:51:17 +0200, Jakub Jelinek wrote: > > On Thu, Jul 30, 2015 at 01:47:37PM +0200, Thomas Schwinge wrote: > > > > Here is such a libgomp plugin plus the infrastructure for initial > > > > support > > > > of non-shared memory

Re: [PATCH] PR target/67127: [ARM] Avoiding odd-number ldrd/strd in movdi introduced a regression on armeb-linux-gnueabihf

Hi Alan, On 10 August 2015 at 18:02, Alan Lawrence wrote: > Yvan Roux wrote: >> >> Hi, >> >> this patch is a fix for pr27127. It avoids splitting the DI registers >> into SI ones if it is not allowed, which breaks the introduced loop. >> I haven't added a testcase as the bug is already exhibited

Re: [Bug fortran/52846] [F2008] Support submodules - part 3/3

On 08/03/2015 02:36 PM, Paul Richard Thomas wrote: Dear Mikael, Thanks for your green light! I have been mulling over the trans-decl part of the patch and having been wondering if it is necessary. Without optimization, private entities can be linked to. Given the discussion concerning the combi

AW: [Bug fortran/52846] [F2008] Support submodules - part 3/3

Hello Toon, all else, a bit unfortunate, in my opinion (I was present at the discussion). I've in the meantime taken some effort to implement what the design pattern experts might call an "abstract factory with full dependency inversion" as a bare-bones framework and have attached an archive w

[committed, PATCH] Update -mtune=knl for Knights Landing

According to: https://software.intel.com/sites/default/files/managed/e9/b5/Knights-Corner-is-your-path-to-Knights-Landing.pdf Knights Landing is “Based on Intel Atom core (based on Silvermont microarchitecture) with many HPC enhancements.” This patch replaces CPU_KNL with CPU_SLM to tune for Kni

Re: [PATCH] Treat model == 0x4f as Broadwell

On Sat, Aug 8, 2015 at 12:42 AM, Uros Bizjak wrote: > On Sat, Aug 8, 2015 at 12:57 AM, H.J. Lu wrote: >> From Intel SDM Vol 3: >> >> Table 35-29 lists MSRs that are common to processors based on the >> Broadwell microarchitectures (including CPUID signatures 06_3DH, 06_47H, >> 06_4FH, and 06_56H)

Re: [gomp4] internal fns for id & nid

Hi! On Mon, 3 Aug 2015 16:43:04 -0400, Nathan Sidwell wrote: > I've committed this to gomp4 branch. It replaces the regular builtins > __builtin_GOACC_nid/__builtin_GOACC_id with internal functions > IFN_OACC_DIM_SIZE > and IFN_OACC_DIM_POS -- moving further away from the PTX-specific naming

Re: [gomp4] OpenACC first private

Hi! On Mon, 3 Aug 2015 10:30:49 -0400, Nathan Sidwell wrote: > I've committed this patch to gomp4. The existing implementation of > firstprivate > presumes the existence of memory at the CTA level. This patch does away with > that, treating firstprivate as thread-private variables initialize

Re: offload data version number

Hi! On Thu, 6 Aug 2015 21:52:43 +0200, Nathan Sidwell wrote: > Ping? > > 1) updated version patch > https://gcc.gnu.org/ml/gcc-patches/2015-08/msg00010.html > > 2) https://gcc.gnu.org/ml/gcc-patches/2015-08/msg00204.html > An infrastructure piece from Thomas, who noticed liboffloadmic didn't h

[optimize 1/3] Fix phi to min/max

Richard, This patch fixes the problem I described earlier about min/max generation propagating incorrect range information (https://gcc.gnu.org/ml/gcc/2015-08/msg00024.html). I went with creating a new name, if the PHI being modified has more than 2 edges. I also modified the testcase that

[optimize 2/3] Simplify vrp abs conversion

Richard, in looking at how simplify_abs_using_ranges was doing its thing as a guide to a min/max vrp optimization, I noticed it was doing more work than necessary. Firstly, it wasn't taking advantage of the range comparison functions only returning TRUE or FALSE nodes when there's a definite a

[optimize3/3] VRP min/max exprs

Richard. this is the patch for the min/max optimization I was trying to implement before getting sidetracked with the phi bug and cleaning the vrp abs optimization. This patch checks both min and max where both operands have a determined range, and the case where the second op is a constant.

Re: [COMMITTED][AArch64] Improve TLS Descriptor pattern to release RTL loop IV opt

Andreas Schwab writes: > Jiong Wang writes: > >> Andreas Schwab writes: >> >>> Jiong Wang writes: >>> And I just finished two round of native aarch64 build/check w/wo my patch. >>> >>> Did you rebuild everything? >> >> No. > > Please do. Andreas, I Just finished several round of rebuil

Re: [PATCH] Fix PR67053

On Wed, 29 Jul 2015, Richard Biener wrote: The following fixes PR67053 by more closely mirror what fold_binary()s STRIP_NOPS does to avoid the C++ FE constexpr code to regress. Bootstrapped on x86_64-unknown-linux-gnu, testing in progress. Yes, I'm thinking on an automated way to more closely

Re: [PR64164] drop copyrename, integrate into expand

On Mon, Aug 10, 2015 at 5:14 PM, Jeff Law wrote: > On 08/10/2015 02:23 AM, James Greenhalgh wrote: >> >> On Tue, Aug 04, 2015 at 12:45:28AM +0100, Alexandre Oliva wrote: >>> >>> On Jul 30, 2015, "H.J. Lu" wrote: >>> aoliva/pr64164 is fine on x32. >>> >>> >>> Thanks. I have made a large num

Re: Fix two more memory leaks in threader

Hello! +2015-08-03 Jeff Law + + PR middle-end/66314 + PR gcov-profile/66899 + * tree-ssa-threadupdate.c (mark_threaded_blocks): Correctly + iterate over the jump threading paths when an element in the + jump threading paths array is eliminated. + 2015-08-03 Segher Boessenkool * Makefile.