ping*3: [PATCH, x86] [PR target/64835] Add TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook

Hi, I'd like to re-ping the following patch for GCC 5.2. It fixes the __attribute__ ((__optimize__ (...))) on x86. Testcase is in the patch. thanks Christian On 04/13/2015 04:24 PM, Christian Bruel wrote: > https://gcc.gnu.org/ml/gcc-patches/2015-02/msg00243.html > > thanks, > > Christian >

Re: [PATCH][PR65823] Fix va_arg ap_copy nop detection

On 22-04-15 15:50, Richard Biener wrote: On Wed, Apr 22, 2015 at 3:38 PM, Tom de Vries wrote: On 22-04-15 10:06, Richard Biener wrote: On Wed, Apr 22, 2015 at 9:41 AM, Tom de Vries wrote: Hi, this patch fixes PR65823. The patches fixes the problem by using operand_equal_p to do the

Re: [PATCH] Fix VRP update_value_range and caller (PR tree-optimization/65875)

On Fri, 24 Apr 2015, Jakub Jelinek wrote: > Hi! > > In vrp_visit_assignment_or_call we try to return SSA_PROP_VARYING > if update_value_range returned true and the new range is VR_VARYING, > but vrp_visit_phi_node fails to do that. > Another thing is that if update_value_range decides to > set_va

Re: [PATCH] Fix VRP update_value_range and caller (PR tree-optimization/65875)

On Mon, Apr 27, 2015 at 10:05:21AM +0200, Richard Biener wrote: > > --- gcc/tree-vrp.c.jj 2015-04-20 14:35:39.0 +0200 > > +++ gcc/tree-vrp.c 2015-04-24 18:10:41.321367440 +0200 > > @@ -892,7 +892,12 @@ update_value_range (const_tree var, valu > > UNDEFINED or from VARYING. */ >

Re: [PATCH][PR65818][bootstrap,hppa] Return side-effect free result in gimplify_va_arg_internal

On Sat, Apr 25, 2015 at 2:35 PM, Tom de Vries wrote: > Hi, > > this patch fixes PR65818, and hppa bootstrap. > > When compiling gcc/libiberty/vprintf-support.c, the following va_arg is > compiled: > ... > (void) __builtin_va_arg(ap, double); > ... > > This results in the following ifn_va_arg at g

Re: [PATCH] Fix VRP update_value_range and caller (PR tree-optimization/65875)

On Mon, 27 Apr 2015, Jakub Jelinek wrote: > On Mon, Apr 27, 2015 at 10:05:21AM +0200, Richard Biener wrote: > > > --- gcc/tree-vrp.c.jj 2015-04-20 14:35:39.0 +0200 > > > +++ gcc/tree-vrp.c2015-04-24 18:10:41.321367440 +0200 > > > @@ -892,7 +892,12 @@ update_value_range (const_t

Fix librayr name of __builtin_allocal_with_align

Hi, build_common_builtin_nodes declares both __builtin_alloca and __builtin_alloca_with_align to have library name "alloca". This actually triggers warning in an updated ODR violation detector on "alloca" being declared twice. __builtin_alloca_with_align IMO do not have library equivalent and I th

Re: [PATCH] Properly valueize values we value-number to

On Fri, 24 Apr 2015, Jeff Law wrote: > On 02/17/2015 07:58 AM, Richard Biener wrote: > [ Restarting a old thread... ] > > > On a closer look the record_const_or_copy_1 hunk is redundant > > (record_equality is really a bit obfuscated...). > Agreed. I'm not entirely sure how it got to this point.

Improve LTO type checking during symtab merging

Hi, this patch strengten ODR checking for requiring match on declarations (if both of them are defined in C++ tranlsation unit). Currently ipa-symtab.c will warn only if declarations are incompatible in useless_type_conversion sense. Now we warn more often, i.e. in the following example: t.C: c

Re: Fix librayr name of __builtin_allocal_with_align

On Mon, 27 Apr 2015, Jan Hubicka wrote: > Hi, > build_common_builtin_nodes declares both __builtin_alloca and > __builtin_alloca_with_align to have library name "alloca". This actually > triggers warning in an updated ODR violation detector on "alloca" being > declared twice. > > __builtin_alloca

Re: Improve LTO type checking during symtab merging

On Mon, 27 Apr 2015, Jan Hubicka wrote: > Hi, > this patch strengten ODR checking for requiring match on declarations > (if both of them are defined in C++ tranlsation unit). Currently > ipa-symtab.c will warn only if declarations are incompatible in > useless_type_conversion sense. Now we warn

[PATCH][combine][obvious] Use std::swap instead of manually swapping

Hi all, This is another one of those std::swap patches, this time I was in the combine neighbourhood Bootstrapped on x86_64 and tested on aarch64. Precedents suggest these changes are considered obvious. So I'll commit this in a couple of days unless someone objects. Thanks, Kyrill 2015-04-27

[PATCH][simplify-rtx][trivial] Use std::swap instead of manually swapping

Hi all, This patch replaces in simplify-rtx.c the manual swapping of values with std::swap. Precedents suggest these are considered obvious changes. Bootstrapped and tested on aarch64, x86_64. Will commit as obvious in a couple of days if no one objects Thanks, Kyrill 2015-04-27 Kyrylo Tkac

[committed] Make arguments to vec::splice const

vec::splice doesn't modify its source vector, so mark the argument as const. Tested on x86_64-linux-gnu. Applied as obvious. Richard gcc/ * vec.h (vec): Make splice arguments const. Update definitions accordingly. Index: gcc/vec.h =

[PATCH][AArch64] Add alternative 'extr' pattern, calculate rtx cost properly

Hi all, We currently have a pattern that will recognise a particular combination of shifts and bitwise-or as an extr instruction. However, the order of the shifts inside the IOR doesn't have canonicalisation rules (see rev16 pattern for similar stuff). This means that for code like: unsigned l

Fix xstormy16 handling of HImode predicates

xstormy16 has: (define_predicate "xs_hi_general_operand" (match_code "const_int,reg,subreg,mem,symbol_ref,label_ref,const") { if ((GET_CODE (op) == CONST_INT) && ((INTVAL (op) >= 32768) || (INTVAL (op) < -32768))) { error ("constant halfword load operand out of range");

Extend list of codes accepted by address_operand

While testing the patch that I'm about to post, I found that the list of address_operand codes in gensupport.c was incomplete. This patch fills in some "obvious" missing entries. It isn't exactly clear which codes are allowed at the top level of an address. decompose_address is known to be gener

Add a build version of inchash.o

The generator patch that I'm about to post wants to use inchash.c, so this patch adds it to the list of files that are built for the build system as well as the host. Tested on x86_64-linux-gnu. OK to install? Thanks, Richard gcc/ * inchash.h, inchash.c: Include bconfig.h for build obj

Remove redudant tests in icf_handled_component_p

handled_component_p comprises both REALPART_EXPR and IMAGPART_EXPR. Tested on x86_64-suse-linux, applied on the mainline as obvious. 2015-04-27 Eric Botcazou * ipa-icf.c (icf_handled_component_p): Remove redundant tests. -- Eric BotcazouIndex: ipa-icf.c ===

Re: [PATCH][expr.c] PR 65358 Avoid clobbering partial argument during sibcall

On 22/04/15 12:51, Kyrill Tkachov wrote: On 21/04/15 18:33, Kyrill Tkachov wrote: On 21/04/15 15:09, Jeff Law wrote: On 04/21/2015 02:30 AM, Kyrill Tkachov wrote: From reading config/stormy16/stormy-abi it seems to me that we don't pass arguments partially in stormy16, so this code would

Mostly rewrite genrecog

I think it's been the case for a while that parallel builds of GCC tend to serialise around the compilation of insn-recog.c, especially with higher --enable-checking settings. This patch tries to speed that up by replacing most of genrecog with a new algorithm. I think the main problems with the

Re: Add a build version of inchash.o

On Mon, Apr 27, 2015 at 12:09 PM, Richard Sandiford wrote: > The generator patch that I'm about to post wants to use inchash.c, > so this patch adds it to the list of files that are built for the > build system as well as the host. > > Tested on x86_64-linux-gnu. OK to install? Ok. THanks, Rich

RE: [PATCH, combine] Try REG_EQUAL for nonzero_bits

> From: Jeff Law [mailto:l...@redhat.com] > Sent: Saturday, April 25, 2015 3:00 AM > Do you have a testcase where this change can result in better generated > code. If so please add that testcase. It's OK if it's ARM specific. Hi Jeff, Last time I tried I couldn't reduce the code to a small tes

Minor tweak to size functions

The size functions are used by the Ada compiler to factor out the large size computations in self-referential types (dynamic types whose size depends on a discriminant in the object). We generate useless leaf size functions for size expressions involving discriminants: _Global.Sz4_Q (ada__str

RE: [PATCH] [1/2] [ARM] [libgcc] Support RTABI half-precision conversion functions.

> -Original Message- > From: Ramana Radhakrishnan [mailto:ramana@googlemail.com] > Sent: Wednesday, April 22, 2015 5:00 PM > To: Hale Wang > Cc: Ramana Radhakrishnan; Joseph Myers; GCC Patches > Subject: Re: [PATCH] [1/2] [ARM] [libgcc] Support RTABI half-precision > conversion function

Re: [ARM] Fix RTX cost for vector SET

Hi Kugan, On 25/04/15 00:30, Kugan wrote: Thanks for the review. I have updated the patch based on the comments with some other minor changes. Bootstrapped and regression tested on aarch64-none-linux-gnu with no-new regressions. Is this OK for trunk? Thanks, Kugan gcc/ChangeLog: 2015-04-24

RE: [PATCH 1/2, combine] Try REG_EQUAL for nonzero_bits

> From: Jeff Law [mailto:l...@redhat.com] > Sent: Saturday, April 25, 2015 2:57 AM > > +static rtx > > +sign_extend_short_imm (rtx src, machine_mode mode, unsigned int > prec) > > +{ > > + if (GET_MODE_PRECISION (mode) < prec && CONST_INT_P (src) > > + && INTVAL (src) > 0 && val_signbit_know

[Patch, fortran] Simplify lbound for array subcomponents

Hello, while reviewing Thomas' bound simplification patch, I noticed that the {l,u}bound simplification code wasn't handling array subcomponents. Fixed by the attached patch, regression tested. OK for trunk? Mikael 2015-04-27 Mikael Morin * simplify.c (simplify_bound_dim): Tight

Re: Hide _S_n_primes from user code

On 22/04/15 22:11 +0200, François Dumont wrote: +constexpr auto __n_primes + = sizeof(__prime_list) / sizeof(unsigned long) - 1; Normally I'd say sizeof(__prime_list) / sizeof(*__prime_list) - 1 would be better, but since it's very unlikely we'll change the element type in the

Re: [PR64164] drop copyrename, integrate into expand

On Fri, Apr 24, 2015 at 3:56 AM, Alexandre Oliva wrote: > On Apr 6, 2015, Jeff Law wrote: > So the bulk of the changes into this routine are really about picking a good leader, which presumably is how we're able to get the desired effects on debuginfo that we used to get from tree

Re: [PATCH] Fix LTO option streaming

On Thu, 23 Apr 2015, Richard Biener wrote: > On Thu, 23 Apr 2015, Jan Hubicka wrote: > > > > > > > It looks like when transitioning to using target and optimization > > > option nodes for compile-time to link-time option streaming you > > > didn't adjust lto-opts.c nor lto-wrapper.c. The follow

Re: niter_base simplification

On 22/04/15 22:10 +0200, François Dumont wrote: Hello I don't know if I am missing something but I think __niter_base could be simplified to remove usage of _Iter_base. Additionally I overload it to also remove __normal_iterator layer even if behind a reverse_iterator or move_iterator, mig

Re: [Patch] Add regex_constants::__polynomial

On 26/04/15 17:55 -0700, Tim Shen wrote: I didn't test with _GLIBCXX_DEBUG though. Updated the patch for removing DFS restriction for ECMAScript. OK for trunk.

Re: [PATCH, x86] Add TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook

On Wed, Feb 4, 2015 at 2:21 PM, Christian Bruel wrote: > While trying to reduce the PR64835 case for ARM and x86, I noticed that the > alignment flags are cleared for x86 when attribute optimized is used. > > With the attached testcases, the visible effects are twofold : > > 1) Functions compiled

[PATCH, ARM] Alternatives and type attributes fixes.

Hi, This is a follow-up of PR64208 where an LRA loop was due to redundancy in insn's alternatives. I've checked all the insns in the arm backend to avoid latent problems and this patch fixes the issues I've spotted. Only thumb2_movsicc_insn contained duplicated alternatives, and the rest of the

[patch] Add a cross-reference link to libstdc++ manual

Committed to trunk. commit 85b6429ce3410f9e204f7d926f67707556c6a4bf Author: Jonathan Wakely Date: Mon Apr 27 13:27:27 2015 +0100 * doc/xml/manual/extensions.xml: Add cross-reference. * doc/html/manual/ext_compile_checks.html: Regenerate. diff --git a/libstdc++-v3/doc/xml/manual/ex

Re: [PATCH] Properly valueize values we value-number to

On Mon, 27 Apr 2015, Richard Biener wrote: > On Fri, 24 Apr 2015, Jeff Law wrote: > > > On 02/17/2015 07:58 AM, Richard Biener wrote: > > [ Restarting a old thread... ] > > > > > On a closer look the record_const_or_copy_1 hunk is redundant > > > (record_equality is really a bit obfuscated...).

Re: [PATCH][PR65818][bootstrap,hppa] Return side-effect free result in gimplify_va_arg_internal

On 27-04-15 10:17, Richard Biener wrote: This patch fixes that by gimplifying the address expression of the mem-ref >returned by the target hook (borrowing code from gimplify_expr, case >MEM_REF). > >Bootstrapped and reg-tested on x86_64. > >Bootstrapped and reg-tested on hppa2.0w-hp-hpux11.11. >

Re: Fix xstormy16 handling of HImode predicates

Hi Richard, gcc/ * config/stormy16/predicates.md (xs_hi_general_operand): Delete. (xs_hi_nonmemory_operand): Remove error. * config/stormy16/stormy16.md (movhi, movhi_internal): Use general_operand rather than xs_hi_general_operand. Approved - please apply. Che

Re: [PATCH][expr.c] PR 65358 Avoid clobbering partial argument during sibcall

On 2015-04-27 6:12 AM, Kyrill Tkachov wrote: On 22/04/15 12:51, Kyrill Tkachov wrote: On 21/04/15 18:33, Kyrill Tkachov wrote: On 21/04/15 15:09, Jeff Law wrote: On 04/21/2015 02:30 AM, Kyrill Tkachov wrote: From reading config/stormy16/stormy-abi it seems to me that we don't pass argume

Re: [PATCH, ARM] Alternatives and type attributes fixes.

Hi Yvan, On 27/04/15 13:25, Yvan Roux wrote: Hi, This is a follow-up of PR64208 where an LRA loop was due to redundancy in insn's alternatives. I've checked all the insns in the arm backend to avoid latent problems and this patch fixes the issues I've spotted. Only thumb2_movsicc_insn contain

[PATCH][AArch64] Fix operand costing logic for MINUS

Hi all, This fixes a case in aarch64 costs where we forgot to account for one of the operands in the MINUS case. This is important to get right as the mult synthesis code can ask for the cost of a shift+sub operation and put the shift part in any of the MINUS operands, expecting the cost functio

Re: [PATCH, rs6000, testsuite, PR65456] Changes for unaligned vector load/store support on POWER8

On Mon, 2015-04-27 at 14:23 +0800, Bin.Cheng wrote: > On Mon, Mar 30, 2015 at 1:42 AM, Bill Schmidt > wrote: > > > Index: gcc/testsuite/gcc.dg/vect/vect-33.c > > === > > --- gcc/testsuite/gcc.dg/vect/vect-33.c (revision 221118) > >

[PATCH][AArch64] Improve spill code - swap order in shl pattern

Various instructions are supported as integer operations as well as SIMD on AArch64. When register pressure is high, lra-constraints inserts spill code without taking the allocation class into account, and basically chooses the first available pattern that matches. Since this instruction has the

Re: [PATCH][simplify-rtx][trivial] Use std::swap instead of manually swapping

On 04/27/2015 03:55 AM, Kyrill Tkachov wrote: Hi all, This patch replaces in simplify-rtx.c the manual swapping of values with std::swap. Precedents suggest these are considered obvious changes. Bootstrapped and tested on aarch64, x86_64. Will commit as obvious in a couple of days if no one ob

Re: [PATCH][PR65818][bootstrap,hppa] Return side-effect free result in gimplify_va_arg_internal

On Mon, Apr 27, 2015 at 3:06 PM, Tom de Vries wrote: > On 27-04-15 10:17, Richard Biener wrote: >>> >>> This patch fixes that by gimplifying the address expression of the >>> mem-ref >>> >returned by the target hook (borrowing code from gimplify_expr, case >>> >MEM_REF). >>> > >>> >Bootstrapped an

RE: [PATCH][AArch64] Use conditional negate for abs expansion

ping > -Original Message- > From: Wilco Dijkstra [mailto:wdijk...@arm.com] > Sent: 03 March 2015 16:19 > To: GCC Patches > Subject: [PATCH][AArch64] Use conditional negate for abs expansion > > Expand abs into a compare and conditional negate. This is the most obvious > expansion, enable

RE: [PATCH][AArch64] Make aarch64_min_divisions_for_recip_mul configurable

ping > -Original Message- > From: Wilco Dijkstra [mailto:wdijk...@arm.com] > Sent: 03 March 2015 18:06 > To: GCC Patches > Subject: [PATCH][AArch64] Make aarch64_min_divisions_for_recip_mul > configurable > > This patch makes aarch64_min_divisions_for_recip_mul configurable for float >

RE: [PATCH][AArch64] Fix aarch64_rtx_costs of PLUS/MINUS

ping > -Original Message- > From: Wilco Dijkstra [mailto:wdijk...@arm.com] > Sent: 04 March 2015 15:38 > To: GCC Patches > Subject: [PATCH][AArch64] Fix aarch64_rtx_costs of PLUS/MINUS > > Include the cost of op0 and op1 in all cases in PLUS and MINUS in > aarch64_rtx_costs. > Bootstrap

Re: [PATCH, ARM] Alternatives and type attributes fixes.

On 27 April 2015 at 15:20, Kyrill Tkachov wrote: > Hi Yvan, > > > On 27/04/15 13:25, Yvan Roux wrote: >> >> Hi, >> >> This is a follow-up of PR64208 where an LRA loop was due to redundancy >> in insn's alternatives. I've checked all the insns in the arm backend >> to avoid latent problems and thi

Re: [PATCH][AArch64] Fix aarch64_rtx_costs of PLUS/MINUS

Hi Wilco, On 27/04/15 14:43, Wilco Dijkstra wrote: ping -Original Message- From: Wilco Dijkstra [mailto:wdijk...@arm.com] Sent: 04 March 2015 15:38 To: GCC Patches Subject: [PATCH][AArch64] Fix aarch64_rtx_costs of PLUS/MINUS Include the cost of op0 and op1 in all cases in PLUS and MI

Re: [PATCH] [AArch32] Additional bics patterns.

On 24/04/15 16:41, Alex Velenko wrote: Hi, This patch adds rtl patterns to generate bics instructions with shift. Added attribute predicable_short_it since last respin. Done full regression run on arm-none-eabi and arm-none-gnueabihf. Bootstrapped on arm-none-gnueabihf. Is this patch ok? gcc

RE: [PATCH][AArch64] Fix Cortex-A53 shift costs

ping > -Original Message- > From: Wilco Dijkstra [mailto:wdijk...@arm.com] > Sent: 05 March 2015 14:49 > To: gcc-patches@gcc.gnu.org > Subject: [PATCH][AArch64] Fix Cortex-A53 shift costs > > This patch fixes the shift costs for Cortex-A53 so they are more accurate - > immediate shifts >

Re: [PATCH][AArch64] Fix aarch64_rtx_costs of PLUS/MINUS

On 27/04/15 14:53, Kyrill Tkachov wrote: Hi Wilco, On 27/04/15 14:43, Wilco Dijkstra wrote: ping -Original Message- From: Wilco Dijkstra [mailto:wdijk...@arm.com] Sent: 04 March 2015 15:38 To: GCC Patches Subject: [PATCH][AArch64] Fix aarch64_rtx_costs of PLUS/MINUS Include the cost

Re: [PATCH 2/13] musl libc config

On 22/04/15 16:42, Szabolcs Nagy wrote: > yes, i didn't realize that this depends on the target specific parts > > i will prepare an updated patch that works if the target has no musl > dynamic linker name defined > Updated the patch, this time I tested it separately. (The test revealed that -m

Re: [PATCH 3/13] aarch64 musl support

On 21/04/15 15:16, pins...@gmail.com wrote: > > I don't think you need to check if defaulting to little or big-endian here > are the specs always have one or the other passing through. > > Also if musl does not support ilp32, you might want to error out. Or even > define the dynamic linker na

Re: [PATCH 5/13] microblaze musl support

On 20/04/15 19:54, Szabolcs Nagy wrote: > Set up dynamic linker name for microblaze. > Patch v2. (undef MUSL_DYNAMIC_LINKER that comes from config/linux.h) gcc/Changelog: 2015-04-24 Gregor Richards * config/microblaze/linux.h (MUSL_DYNAMIC_LINKER): Define. (DYNAMIC_LINKER):

Re: [PATCH][combine][obvious] Use std::swap instead of manually swapping

On Mon, Apr 27, 2015 at 10:55:17AM +0100, Kyrill Tkachov wrote: > Precedents suggest these changes are considered obvious. > So I'll commit this in a couple of days unless someone objects. Yes it's obvious. One tiny thing... > @@ -9062,7 +9061,7 @@ known_cond (rtx x, enum rtx_code cond, rtx reg,

Re: [PATCH 6/13] mips musl support

On 21/04/15 15:59, Matthew Fortune wrote: > Rich Felker writes: >> On Tue, Apr 21, 2015 at 01:58:02PM +, Matthew Fortune wrote: >>> There does however appear to be both soft and hard float variants Patch v2. Now all the ABI variants musl plans to support are represented. gcc/Changelog: 2

Re: [C/C++ PATCH] Improve -Wlogical-op (PR c/63357)

On Sat, Apr 25, 2015 at 10:18:59PM +0200, Gerald Pfeifer wrote: > In case this example feels too contrived (even though it is an > excerpt of Wine code), we now also warn about the following where > the two types and variables are defined in different places and > the size of one is set implicitly:

Re: [PATCH 8/13] sh musl support

On 20/04/15 21:29, Oleg Endo wrote: > On Mon, 2015-04-20 at 19:56 +0100, Szabolcs Nagy wrote: >> Set up dynamic linker name for sh. >> > > The SH parts are OK for trunk. > Patch v2 It turns out we have to distinguish between hard float and nofpu ABI. I simply listed the options that turn on n

Re: [C/C++ PATCH] Improve -Wlogical-op (PR c/63357)

On Mon, Apr 27, 2015 at 04:47:12PM +0200, Marek Polacek wrote: > On Sat, Apr 25, 2015 at 10:18:59PM +0200, Gerald Pfeifer wrote: > > In case this example feels too contrived (even though it is an > > excerpt of Wine code), we now also warn about the following where > > the two types and variables a

Re: [PATCH 9/13] x86 musl support

On 20/04/15 19:57, Szabolcs Nagy wrote: > Set up dynamic linker name for x86. > Patch v2. (undef MUSL_DYNAMIC_LINKER* before defining it). gcc/Changelog: 2015-04-27 Gregor Richards * config/i386/linux.h (MUSL_DYNAMIC_LINKER): Define. * config/i386/linux64.h (MUSL_DYNAMIC_LI

Re: [PATCH 7/13] powerpc musl support

On 20/04/15 19:55, Szabolcs Nagy wrote: > Set up dynamic linker name for powerpc. Musl only supports powerpc > with secure plt, so appropriate options are passed to the linker by > default. Patch v2. Powerpc does not include the top level linux.h, so I had to repeat the include order fixes from

RE: [PATCH][combine][obvious] Use std::swap instead of manually swapping

On 27/04/15 15:37, Segher Boessenkool wrote: > On Mon, Apr 27, 2015 at 10:55:17AM +0100, Kyrill Tkachov wrote: >> Precedents suggest these changes are considered obvious. >> So I'll commit this in a couple of days unless someone objects. > > Yes it's obvious. One tiny thing... > >> @@ -9062,7 +906

RE: [PATCH] Fix IRA register preferencing

> Jeff Law wrote: > On 12/10/14 06:26, Wilco Dijkstra wrote: > > > > If recomputing is best does that mean that record_reg_classes should not > > give a boost to the preferred class in the 2nd pass? > Perhaps. I haven't looked deeply at this part of IRA. I was relaying > my experiences with (ab)u

Re: [PATCH][PR65818][bootstrap,hppa] Return side-effect free result in gimplify_va_arg_internal

On 27-04-15 15:40, Richard Biener wrote: On Mon, Apr 27, 2015 at 3:06 PM, Tom de Vries wrote: On 27-04-15 10:17, Richard Biener wrote: This patch fixes that by gimplifying the address expression of the mem-ref returned by the target hook (borrowing code from gimplify_expr, case MEM_REF). Bo

Re: [PATCH] libmpx: remove AC_PROG_CXX/GCC_LIBSTDCXX_RAW_CXX_FLAGS from configure.ac

2015-04-23 12:53 GMT+03:00 Steven Noonan : > This causes libmpx to fail the configure stage on my build hosts because > 'xg++' > was invoked with the bogus '-funconfigured-libstdc++-v3' flag, and the > fallback > preprocessor '/lib/cpp' did not exist on my systems. > > Since libmpx has no C++ cod

Re: [PATCH v2 3/4] libcc1: Add 'set compile-gcc'

On 04/23/2015 09:38 PM, Jan Kratochvil wrote: > - configury triplet prefix to the compiler. > + configury triplet prefix to the compiler; TRIPLET_REGEXP can be > + also absolute filename to the computer. "to the computer" is probably a typo for "to the compiler". Also, double space af

Re: [PATCH, rs6000, testsuite] Fix PR target/64579, __TM_end __builtin_tend failed to return transactional state

On Fri, 2015-04-24 at 11:40 -0400, David Edelsohn wrote: > On Fri, Apr 24, 2015 at 11:34 AM, Segher Boessenkool > > All looks great to me now, thanks for the changes, > > Okay for me. In back porting my patch, I see that the patch doesn't apply cleanly to the 4.8/4.9 branch code. Looking at why,

Re: [PATCH] Make wider use of "v" constraint in i386.md

On 17 Apr 10:09, Uros Bizjak wrote: > On Thu, Mar 19, 2015 at 10:24 AM, Ilya Tocar wrote: > > Hi, > > > > There were some discussion about "x" constraints being too conservative > > for some patterns in i386.md. > > Patch below fixes it. This is probably stage1 material. > > > > ChangeLog: > > > >

Re: [C/C++ PATCH] Implement -Wshift-negative-value (PR c/65179)

On Sat, Apr 25, 2015 at 08:13:08PM +, Joseph Myers wrote: > On Sat, 25 Apr 2015, Marek Polacek wrote: > > > + pedwarn (location, OPT_Wshift_negative_value, > > +"left shift of negative value"); > > Use of pedwarn is always suspect for something only undefined at

Re: [C/C++ PATCH] Improve -Wlogical-op (PR c/63357)

On 04/27/2015 08:47 AM, Marek Polacek wrote: On Sat, Apr 25, 2015 at 10:18:59PM +0200, Gerald Pfeifer wrote: In case this example feels too contrived (even though it is an excerpt of Wine code), we now also warn about the following where the two types and variables are defined in different place

Re: [PATCH][combine][obvious] Use std::swap instead of manually swapping

On 04/27/2015 08:37 AM, Segher Boessenkool wrote: On Mon, Apr 27, 2015 at 10:55:17AM +0100, Kyrill Tkachov wrote: Precedents suggest these changes are considered obvious. So I'll commit this in a couple of days unless someone objects. Yes it's obvious. One tiny thing... @@ -9062,7 +9061,7 @

Re: [PATCH 6/n] OpenMP 4.0 offloading infrastructure: option handling

Hi! Ping. On Tue, 10 Mar 2015 13:37:47 +0100, I wrote: > Ping. > > On Thu, 19 Feb 2015 09:39:52 +0100, I wrote: > > On Wed, 18 Feb 2015 18:04:21 +0100, I wrote: > > > On Mon, 13 Oct 2014 14:33:11 +0400, Ilya Verbin wrote: > > > > On 13 Oct 12:19, Jakub Jelinek wrote: > > > > > On Sat, Oct 11, 2

Re: [C/C++ PATCH] Improve -Wlogical-op (PR c/63357)

On Mon, Apr 27, 2015 at 10:06:26AM -0600, Jeff Law wrote: > On 04/27/2015 08:47 AM, Marek Polacek wrote: > >On Sat, Apr 25, 2015 at 10:18:59PM +0200, Gerald Pfeifer wrote: > >>In case this example feels too contrived (even though it is an > >>excerpt of Wine code), we now also warn about the follow

Re: [PATCH][AArch64] Improve spill code - swap order in shl pattern

On Mon, Apr 27, 2015 at 02:37:12PM +0100, Wilco Dijkstra wrote: > Various instructions are supported as integer operations as well as SIMD on > AArch64. When register pressure is high, lra-constraints inserts spill code > without taking the allocation class into account, and basically chooses the >

Re: Offloading compilers' libgcc installation

Hi! Ping. (Or can Bernd just commit this patch, (with my review comment addressed, ), given his nvptx architecture mainta

Re: Offloading compilers' libgcc installation

On Mon, Apr 27, 2015 at 06:14:36PM +0200, Thomas Schwinge wrote: > Hi! > > Ping. (Or can Bernd just commit this patch, > > (with my review comment addressed, >

Re: [PATCH] Properly valueize values we value-number to

On 04/27/2015 06:46 AM, Richard Biener wrote: On Mon, 27 Apr 2015, Richard Biener wrote: On Fri, 24 Apr 2015, Jeff Law wrote: On 02/17/2015 07:58 AM, Richard Biener wrote: [ Restarting a old thread... ] On a closer look the record_const_or_copy_1 hunk is redundant (record_equality is really

Re: [PATCH][AArch64] Use conditional negate for abs expansion

On Mon, Apr 27, 2015 at 02:42:36PM +0100, Wilco Dijkstra wrote: > > -Original Message- > > From: Wilco Dijkstra [mailto:wdijk...@arm.com] > > Sent: 03 March 2015 16:19 > > To: GCC Patches > > Subject: [PATCH][AArch64] Use conditional negate for abs expansion > > > > Expand abs into a compa

Re: [PATCH, combine] Try REG_EQUAL for nonzero_bits

On 04/27/2015 04:26 AM, Thomas Preud'homme wrote: From: Jeff Law [mailto:l...@redhat.com] Sent: Saturday, April 25, 2015 3:00 AM Do you have a testcase where this change can result in better generated code. If so please add that testcase. It's OK if it's ARM specific. Hi Jeff, Last time I tr

Re: [PATCH, RFC]: Next stage1, refactoring: propagating rtx subclasses

On 04/25/2015 05:49 AM, Richard Sandiford wrote: @@ -2099,9 +2107,9 @@ fix_crossing_conditional_branches (void) emit_label (new_label); gcc_assert (GET_CODE (old_label) == LABEL_REF); - old_label = JUMP_LABEL (old_jump); - new

Re: [PATCH][OpenMP] Fix resolve_device with -foffload=disable

On Mon, Apr 20, 2015 at 17:16:03 +0300, Ilya Verbin wrote: > Hi! > > Currently if a compiler is configured with enabled offloading, the 'devices' > array in libgomp is filled properly with a number of available devices. > However, if a program is compiled with -foffload=disable, the resolve_device

Re: var-tracking vs. pseudo registers (was: Option overriding in the offloading code path)

Hi! On Thu, 26 Feb 2015 11:46:00 +0100, Jakub Jelinek wrote: > On Thu, Feb 26, 2015 at 11:27:06AM +0100, Thomas Schwinge wrote: > > Is this not the right way to skip it, or, Bernd, is this because we're > > not yet handling some debug stuff in nvptx? (I tested that > >

Re: [PATCH, RFC]: Next stage1, refactoring: propagating rtx subclasses

Jeff Law writes: > On 04/25/2015 05:49 AM, Richard Sandiford wrote: >> That seems pretty heavy-weight for LRA-local code. Also, the long-term >> plan is for INSN_LIST and rtx_insn to be in separate hierarchies, >> at which point we'd have no alias-safe way to distinguish them. > That's certainly

RE: [PATCH][AArch64] Use conditional negate for abs expansion

> James Greenhalgh wrote: > On Mon, Apr 27, 2015 at 02:42:36PM +0100, Wilco Dijkstra wrote: > > > -Original Message- > > > From: Wilco Dijkstra [mailto:wdijk...@arm.com] > > > Sent: 03 March 2015 16:19 > > > To: GCC Patches > > > Subject: [PATCH][AArch64] Use conditional negate for abs expa

C PATCH to reject va_arg (ap, void) (PR c/65901)

As reported in the PR, va_arg (ap, void) probably doesn't make any sense and should be rejected thus. cc1plus and clang reject va_arg with an incomplete type. This patch makes cc1 reject it as well. Bootstrapped/regtested on x86_64-linux, ok for trunk? 2015-04-27 Marek Polacek PR c/

Re: [Patch, fortran, pr59678, v1] -- [F03] Segfault on equalizing variables of a complex derived type

Hi Paul, hi all, Paul, thanks for the review. I have integrated all your comments (i) to (iii) and commited as r222477. Regards, Andre On Sat, 25 Apr 2015 16:42:52 +0200 Paul Richard Thomas wrote: > Dear Andre, > > The patch is OK with three changes: > (i) Put the PR line in the tests

Re: [commited, Patch, Fortran, pr60322, addendum] was: [Patch 1/2, Fortran, pr60322] [OOP] Incorrect bounds on polymorphic dummy array

Hi all, sorry, I forgot to svn-add the testcases for the patch of pr60322. I fixed this with commit r222478. My apologies for the oversight. Regards, Andre On Thu, 23 Apr 2015 13:34:16 +0200 Andre Vehreschild wrote: > Hi Paul, hi all, > > Paul, thanks for the review. I have commited

Re: C PATCH to reject va_arg (ap, void) (PR c/65901)

On 04/27/2015 11:30 AM, Marek Polacek wrote: As reported in the PR, va_arg (ap, void) probably doesn't make any sense and should be rejected thus. cc1plus and clang reject va_arg with an incomplete type. This patch makes cc1 reject it as well. Bootstrapped/regtested on x86_64-linux, ok for tru

Re: Extend list of codes accepted by address_operand

On 04/27/2015 04:07 AM, Richard Sandiford wrote: While testing the patch that I'm about to post, I found that the list of address_operand codes in gensupport.c was incomplete. This patch fills in some "obvious" missing entries. It isn't exactly clear which codes are allowed at the top level of

Re: [PATCH] Properly valueize values we value-number to

On April 27, 2015 6:24:47 PM GMT+02:00, Jeff Law wrote: >On 04/27/2015 06:46 AM, Richard Biener wrote: >> On Mon, 27 Apr 2015, Richard Biener wrote: >> >>> On Fri, 24 Apr 2015, Jeff Law wrote: >>> On 02/17/2015 07:58 AM, Richard Biener wrote: [ Restarting a old thread... ] > On

Re: [Patch, Fortran] Simplify lbound

Am 25.04.2015 um 20:12 schrieb Mikael Morin: > I've double-checked in the standard, and it seems it is not possible to > simplify after all: > > If ARRAY is a whole array and either ARRAY is an assumed-size > array of rank DIM or dimension DIM of ARRAY has nonzero extent, > LBOU

Re: [PATCH] Properly valueize values we value-number to

On 04/27/2015 12:29 PM, Richard Biener wrote: On April 27, 2015 6:24:47 PM GMT+02:00, Jeff Law n & -n will (of course) get computed into an SSA_NAME. We then propagate that name for the use of "n" in the return statement rather than using the effectively zero cost "n". If we put some smarts i

Re: [PATCH] Add new target h8300-*-linux

On 04/26/2015 12:21 AM, Yoshinori Sato wrote: Updated. Some cleanup. Thanks. Committed to the trunk. jeff

Re: [Patch, Fortran] Simplify lbound

Hello world, here is a slight correction: This patch includes the change to the test case. Regards Thomas Index: fortran/simplify.c === --- fortran/simplify.c (Revision 222431) +++ fortran/simplify.c (Arbeitskopie) @@ -344

Re: [PATCH 2/13] musl libc config

On 04/27/2015 08:30 AM, Szabolcs Nagy wrote: On 22/04/15 16:42, Szabolcs Nagy wrote: yes, i didn't realize that this depends on the target specific parts i will prepare an updated patch that works if the target has no musl dynamic linker name defined Updated the patch, this time I tested it

Re: gcc make clean fixes

On 04/23/2015 09:34 PM, Jim Wilson wrote: I noticed that make clean isn't removing C++ binaries. It was broken here https://gcc.gnu.org/ml/gcc-patches/2007-01/msg00214.html Removing stagestuff accidentally removed those items from the mostlyclean rule. They need to be re-added to the langu

Re: [PATCH libstdc++] Fix for std::uncaught_exception (PR 62258)

On 02/02/15 03:37 +0100, Michael Hanselmann wrote: Calls to `std::uncaught_exception` after calling `std::rethrow_exception' always return `true' when `std::uncaught_exception' should return `false' unless an exception is in flight. `std::rethrow_exception' does not update `__cxa_eh_globals::unca

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