On Mon, Apr 27, 2015 at 02:37:12PM +0100, Wilco Dijkstra wrote: > Various instructions are supported as integer operations as well as SIMD on > AArch64. When register pressure is high, lra-constraints inserts spill code > without taking the allocation class into account, and basically chooses the > first available pattern that matches. Since this instruction has the SIMD > version first it is usually chosen eventhough some of the operands are > eventually allocated to integer registers. The result is inefficient code not > only due to the higher latency of SIMD instructions but also due to the extra > int<->FP moves. Placing the integer variant first in the shl pattern > generates far more optimal spill code. A few more patterns are the wrong way > around, which I'll address in a separate patch. I'm also looking into fixing > lra-constraints to generate the expected code by taking the allocno class > into account in the cost calculations during spilling. > > 2015-04-27 Wilco Dijkstra <wdijk...@arm.com> > > * gcc/config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3): > Place integer variant first.
OK, thanks for the fix. Cheers, James
